JPH08330249A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the occurrence of the constriction of a wiring pattern by piling an inert insulating film on a conductor film, and forming a film for preventing the reflection of photosensitive irradiation light hereon, and forming a photosensitive resist film on this reflection preventive film, and pattering them in the patterns in a specified form. CONSTITUTION: A field oxide film 2 is made in a thickness of about 400nm in the specified region on a silicon substrate 1, and a gate insulating film 4 is made in a thickness of about 8nm in the active region 3 surrounded by this oxide film 2. And, polycide wiring 5 to serve as the gate electrode of a MOS transistor is made. Furthermore, a protective insulating film 6 is accumulated on this polycide wiring 5, and a reflection preventive film pattern 7 is made on the surface of this protective insulating film 6. The polycide wiring 5 is patterned, with this reflection preventive film pattern 7 and the protective insulating film 6 as the masks of dry etching, so as to form a gate electrode pattern 5'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming fine pattern wiring with high accuracy.

[0002]

2. Description of the Related Art Miniaturization and densification of semiconductor elements are still vigorously promoted, and are currently 0.2 μm.
Ultra-highly integrated semiconductor devices such as memory devices or logic devices designed on the basis of dimensional standards have been developed and prototyped. In this way, with the high integration of semiconductor devices, the dimensions of semiconductor elements are further miniaturized. Then, it becomes particularly important to reduce the dimensions of the gate electrode width, the diffusion layer width or the wiring width and the film thickness of the material forming the semiconductor element.

The dimensional variation of the component pattern of the semiconductor element thus miniaturized, and in particular, the variation of the gate electrode width, has the greatest influence on the characteristics of the insulated gate field effect transistor (hereinafter referred to as MOS transistor). give. Further, the reduction of the dimension between the electrode wirings and the increase of the aspect ratio of the wiring pattern make it difficult to secure the reliability of the semiconductor element. Therefore, it is essential for manufacturing semiconductor devices to reduce variations in these dimensions.

As described above, with the miniaturization of semiconductor elements, it is of the utmost importance to highly control the dimensions of the constituent element patterns of the semiconductor element as described above.

Hereinafter, a method of manufacturing a high-precision wiring will be described with reference to FIG. FIG. 6 shows a plan view of a gate electrode pattern and a sectional view thereof. Here, a section taken along line A′-B ′ shown in the plan view of FIG. 6A is a sectional view shown in FIG. 6B.

As shown in FIGS. 6A and 6B, a field oxide film 102 is selectively formed in a predetermined region on a silicon substrate 101. Then, the gate insulating film 104 is formed in the active region 103 surrounded by the field oxide film 102. Next, the polycide wiring 105 which will be the gate electrode of the MOS transistor is formed. Then, a protective insulating film 106 deposited on the polycide wiring 105 is deposited.

The protective insulating film 106 is formed by etching the protective insulating film layer using a photoresist mask formed by photolithography as a dry etching mask. Then, the photoresist mask is removed, and the polycide wiring 105 is patterned by dry etching using the protective insulating film 106 as a mask. In this way, the gate electrode pattern 105 'shown in FIG. 6A is formed. However, FIG.
A constriction 107 of the wiring pattern as shown in (a) is formed around the boundary between the field oxide film 102 and the active region 103.

As described above, in highly accurate patterning of the gate electrode wiring or other wiring, an insulating film is formed on the wiring, the insulating film is patterned, and the patterned insulating film is used as a dry etching mask to form a wiring material. The wiring is formed by dry etching.

As described above, the method of using the insulating film as a dry etching mask is (1) an increase in the aspect ratio of the wiring pattern and an increase in the aspect ratio of the photoresist mask, which increases the difficulty of the dry etching process (2).
It has become important as an effective means for coping with the increasing use of the insulating film having the same pattern as the wiring as seen in the formation of a self-aligned contact.

[0010]

In the wiring manufacturing method as described above, the protective insulating film is formed on the surface of the polycide wiring which constitutes the gate electrode of the MOS transistor. Then, polycide wiring is formed by dry etching using this protective insulating film as a mask. The method of using such a protective insulating film as a mask for dry etching is also used for forming other wiring such as aluminum.

However, in the method of forming the wiring of the gate electrode using the protective insulating film as a mask, the constriction 107 of the finished wiring pattern is generated as described with reference to FIG. This is because the transparent protective insulating film is formed on the wiring, so that the light reflected from the wiring surface increases in the exposure process of the photolithography technique. The details will be described later. The constriction of the wiring pattern of the gate electrode increases variations in the electrical characteristics of the MOS transistor. In particular, when the MOS transistor is miniaturized, this increase in variation becomes more remarkable.

Similarly, in the case of wiring made of aluminum or the like, the amount of light reflected by the protective insulating film increases and the wiring pattern is constricted at the stepped portion of the underlying layer, so that the reliability or yield of the semiconductor device is significantly reduced.

An object of the present invention is to provide a method for forming a wiring with the protective insulating film as a mask by solving the above-mentioned problems and forming a highly precise fine wiring pattern.

[0014]

To this end, a method of forming a wiring pattern according to the present invention comprises a step of forming a conductor material film on a surface portion of a semiconductor substrate, and a semiconductor oxidation by laminating on the conductor material film. A step of depositing an inorganic insulating film composed of a film or a semiconductor nitride film, a step of forming an anti-reflection film for exposing light for use in photolithography for patterning a photosensitive resist film on the inorganic insulating film, Forming the photosensitive resist film on the antireflection film and patterning it into a predetermined shape.

Further, a step of dry etching the antireflection film and the inorganic insulating film using the patterned photosensitive resist film as a mask, a step of removing the patterned photosensitive resist film, and the inorganic insulating film Is used as a mask to dry-etch the conductor material film and the antireflection film.

Here, the antireflection film is formed of an amorphous silicon thin film or titanium nitride thin film.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram for explaining the first embodiment of the present invention, and shows a plan view and a cross-sectional view of a gate electrode pattern as in the case of the conventional technique. Here, FIG.
FIG. 1 shows a section taken along the line AB in the plan view of FIG.
It is a sectional view shown in FIG.

As shown in FIGS. 1A and 1B, a field oxide film 2 is selectively formed in a predetermined region on a silicon substrate 1. Here, the field oxide film 2 is formed by LOCOS (Local Oxidation).
of silicon, and the film thickness is 4
It is set to about 00 nm. Then, the gate insulating film 4 is formed in the active region 3 surrounded by the field oxide film 2. Here, the film thickness of the gate insulating film 4 is set to about 8 nm.

Then, a polycide wiring 5 to be the gate electrode of the MOS transistor is formed. Further, a protective insulating film 6 is deposited and deposited on the polycide wiring 5. An antireflection film pattern 7 is formed on the surface of the protective insulating film 6. The antireflection film pattern 7 is formed of an amorphous silicon film.

Here, the antireflection film pattern 7 and the protective insulating film 6 are formed by dry etching using a photoresist mask formed by photolithography as an etching mask. Further, the photoresist mask is removed, and the polycide wiring 5 is formed by using the antireflection film pattern 7 and the protective insulating film 6 as a dry etching mask.
Is patterned to form a gate electrode pattern 5'as shown in FIG. 1 (a).

As shown in FIG. 1 (a), the gate electrode pattern 5'according to the present invention does not have the constriction of the wiring pattern as described in the prior art, and high-precision fine wiring is formed. Become so.

Next, the manufacturing method of the present invention will be described with reference to FIG. 2A to 2D are cross-sectional views in the order of steps from the step of forming a photoresist mask by the above-mentioned photolithography technique to the step of patterning a gate electrode.

As shown in FIG. 1A, the silicon substrate 1
A gate insulating film 4 having a film thickness of about 8 nm is formed on the surface of the film by thermal oxidation. Then, the gate insulating film 4 is covered to form a Tungsten polycide layer 5a formed of a polysilicon layer containing phosphorus impurities and having a thickness of about 100 nm and a tungsten silicide layer having a thickness of about 150 nm. .

After this, a silicon oxide film layer 6a is deposited on the surface of the tungsten polycide layer 5a by the chemical vapor deposition (CVD) method. Here, the film thickness of the silicon oxide film layer 6a is 100 to 200 nm. Then, a silicon film layer 7a is deposited on the silicon oxide film layer 6a by a sputtering method. Here, the film thickness of the silicon film layer 7a is set to about 50 nm.

Next, a photoresist pattern 8 is formed by a known photolithography technique of photolithography technique.

Next, using the photoresist pattern 8 as a mask for dry etching, the above-mentioned silicon film layer 7a and silicon oxide film layer 6a are sequentially etched. Then, the protective insulating film 6 and the antireflection film pattern 7 shown in FIG. 2B are formed.

Next, using the protective insulating film 6 as a dry etching mask, the tungsten polycide layer 5a is etched. Thus, as shown in FIG. 2C, the polycide wiring 5 is formed on the surface of the gate insulating film 4 on the silicon substrate 1. This Tag Sten Polycide Layer 5
In the etching step of a, the antireflection film pattern 7 described above is used.
Is also etched and removed at the same time. This is because both the tungsten polycide layer 5a and the antireflection film pattern 7 contain silicon atoms and can be etched with the same dry etching gas.

Further, the antireflection film pattern may be formed of a titanium nitride layer here. Alternatively, titanium polycide may be used as the conductive material of the gate electrode. Even in these cases, the antireflection film pattern can be removed at the same time when the gate electrode pattern is formed.

As described above, the wiring of the gate electrode having no constriction in the wiring pattern as described above is formed.

Next, the effect of the present invention and the mechanism of producing the effect will be described with reference to FIGS. 3 and 4. Here, FIG. 3 and FIG. 4 schematically show the state of light exposure in the photolithography process for forming the wiring. FIG. 3 shows the case of the conventional technique, and FIG. 4 shows the present invention. In this case, the irradiated object to be exposed is schematically illustrated. That is, as shown in FIGS. 3 and 4,
A field oxide film 2 is selectively formed on the surface of a silicon substrate 1, and a tungsten polycide layer 5a which is a conductor material having a high reflectance is formed on the silicon substrate via a gate insulating film 4. Then, the silicon oxide film layer 6a is formed so as to cover all of them, and the photoresist film 8a is formed.
Is formed by coating. Here, instead of the silicon oxide film layer, another transparent insulating film such as a silicon nitride film may be used.

As shown in FIG. 3, when the object to be exposed to light is irradiated with the light 9 for exposure through the optical pattern of the gate electrode as in the case of the conventional technique, a part of it is transmitted through the silicon oxide film layer 6a. It is reflected on the surface of the tungsten polycide layer 5a to generate reflected light 10a. Then, a part of the light is reflected by the boundary surface between the silicon oxide film layer 6a and the photoresist film 8a to generate reflected light 10. Here, since the refractive index of the photoresist film 8a is about 1.7 and the refractive index of the silicon oxide film is about 1.45, the phase of the reflected light 10 does not change. On the other hand, the phase of the reflected light 10a reflected by the surface of the tungsten polycide layer 5a of the photosensitive irradiation light 9 that has passed through the silicon oxide film layer 6a is shifted by about 180 °.

For this purpose, the thickness of the silicon oxide film layer 6a is d, the refractive index thereof is n, the wavelength of the photosensitive irradiation light 9 is λ, the reflection angle is θ and m is positive as shown in FIG. When the number is an odd number, when the film thickness of the silicon oxide film layer 6a satisfies the expression (1), the reflected lights 10 and 10a are mutually strengthened by interference and the reflection intensity becomes maximum.

[0033]

For example, when the inclination angle of the surface of the field oxide film 2 is 20 °, that is, when the angle θ in FIG. 3 is about 20 °, the irradiation light 9 for light is the i-line and its wavelength is 365.
In the case of nm, the film thickness of the silicon oxide film layer 6a is 60 n.
The reflection intensity becomes maximum at m or about 180 nm. Such an increase in the intensity of reflected light depends on the inclination angle of the base described above and appears in the region that satisfies the expression (1). And
In the region where the intensity of reflected light increases due to this interference, the photoresist film 8a is overexposed and the above-described constriction of the wiring pattern occurs.

On the other hand, when an antireflection film such as the silicon film layer 7a is formed as shown in FIG. 4, the photosensitive irradiation light 9 is isotropically scattered by this antireflection film and reflected by irregular reflection. It becomes light 10b. Then, the reflection intensity in one direction is significantly reduced, and the increase in the reflection light intensity due to the interference of the two reflection lights as described above is suppressed. Alternatively, in the case of an antireflection film such as a titanium nitride layer that completely absorbs the irradiation light for exposure, no component of the reflected light is generated.

With such a structure as shown in FIG. 4, the increase of the reflected light intensity due to the interference is suppressed in all the regions in the semiconductor device, and the constriction of the wiring pattern is prevented. .

Considering the mechanism of producing such an effect, it is also effective to form an antireflection film by laminating it on a conductor material to be wiring and forming a silicon oxide film layer on the antireflection film. However, in this case, the above-described antireflection film pattern cannot be removed by etching at the same time when the wiring is formed, which complicates the process.

Next, a second embodiment of the present invention will be described with reference to FIG. 5A to 5D are cross-sectional views in the order of steps in the case of forming aluminum fine wiring on the interlayer insulating film. As shown in FIG. 5A, the interlayer insulating film 22 is formed on the surface of the silicon substrate 21.
Is formed of a silicon oxide film deposited by the CVD method.
Here, the film thickness of the interlayer insulating film 22 is set to about 500 nm. Next, alloy thin film 2 which is an alloy of aluminum and copper
3a is deposited by the sputtering method. Here, the alloy thin film 23
The film thickness of a is about 500 nm. Then, the first titanium nitride film layer 24a is formed by laminating on the alloy thin film 23a. The thickness of the first titanium nitride film layer 24a is 15
It is about 0 nm.

After this, the silicon oxide film layer 25a is deposited by the CVD method. Here, the film thickness of the silicon oxide film layer 25a is set to about 200 nm. Then, a second film is formed on the silicon oxide film layer 25a by a sputtering method.
Of titanium nitride film layer 26a is deposited. Here, the film thickness of the second titanium nitride film layer 26a is set to about 50 nm.

Next, a photoresist pattern 27 is formed by a known photolithography technique of photolithography.

Next, the second titanium nitride film layer 26a and the silicon oxide film layer 25a described above are sequentially etched using the photoresist pattern 27 as a mask for dry etching. In this way, the protective insulating film 25 and the antireflection film pattern 26 shown in FIG. 5B are formed.

Next, using the protective insulating film 25 as a dry etching mask, the aluminum-copper alloy thin film 23a and the first titanium nitride film layer 24a are etched. Thus, as shown in FIG. 3C, a fine wiring in which the aluminum alloy wiring 23 and the titanium nitride wiring 24 are laminated is formed on the surface of the interlayer insulating film 22 on the silicon substrate 21. In this case, in the etching process of the first titanium nitride film layer 24a, the antireflection film pattern 26 described above is also etched and removed.

As described above, the laminated wiring containing the aluminum alloy having no constriction in the wiring pattern as described above is formed.

In the above embodiments, the case where the protective insulating film is made of a silicon oxide film has been described. It should be noted that the same effect can be obtained by using a silicon nitride film or a composite film of a silicon oxide film and a silicon nitride film as the protective insulating film.

[0045]

As described above, according to the present invention, the antireflection film is formed on the protective insulating film used as the wiring patterning mask. Therefore, the constriction of the wiring pattern does not occur at all in the region having the underlying step as described above. Further, this antireflection film is removed by etching at the same time as the dry etching for forming the wiring, so that it does not adversely affect the subsequent steps. For example, the number of steps for forming wiring hardly increases.

As described above, according to the present invention, the electrical characteristics of a MOS transistor having a fine gate electrode are stabilized and its variation is greatly reduced. Therefore, the cell operating characteristics of a fine and high-density SRAM or the sense amplifier The operating characteristics will be greatly improved.

Further, the reliability of the process of forming the fine multi-layered wiring is greatly improved, and the yield of the semiconductor device having these multi-layered wiring is greatly improved.

[Brief description of drawings]

FIG. 1 is a wiring diagram for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in the order of manufacturing steps for explaining the first embodiment of the present invention.

FIG. 3 is a light exposure diagram for explaining the effect of the first embodiment of the present invention.

FIG. 4 is a light exposure diagram for explaining the effect of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view in the order of manufacturing steps for explaining the second embodiment of the present invention.

FIG. 6 is a wiring diagram for explaining a conventional technique.

[Explanation of symbols]

 1, 2, 101 Silicon substrate 2, 102 Field oxide film 3, 103 Active region 4, 104 Gate insulating film 5, 105 Polycide wiring 5 ', 105' Gate electrode pattern 5a Tungsten polycide layer 6, 25, 106 Protective insulating film 6a, 25a Silicon oxide film layer 7,26 Antireflection film pattern 7a Silicon film layer 8,27 Photoresist pattern 8a Photoresist film 9 Photosensitive irradiation light 10, 10a, 10b Reflected light 22 Interlayer insulating film 23 Alloy wiring 23a Alloy thin film 24 Titanium Nitride Wiring 24a First Titanium Nitride Film Layer 26a Second Titanium Nitride Film Layer 107 Wiring Pattern Constriction

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/3213 H01L 21/88 D

Claims (3)

[Claims] 1. A step of forming a conductor material film on a surface portion of a semiconductor substrate, and a step of depositing an inorganic insulating film formed of a semiconductor oxide film or a semiconductor nitride film on the conductor material film. A step of forming an anti-reflection film for photo-irradiation light used in photolithography for patterning the photosensitive resist film on the inorganic insulating film; and forming the photosensitive resist film on the anti-reflection film to form a predetermined shape. A step of patterning, and a method of manufacturing a semiconductor device. 2. A step of dry etching the antireflection film and the inorganic insulating film using the patterned photosensitive resist film as a mask, a step of removing the patterned photosensitive resist film, and the inorganic insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of dry etching the conductor material film and the antireflection film using the mask as a mask. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the antireflection film is formed of an amorphous silicon thin film or a titanium nitride thin film.