CN114823294A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

Info

Publication number
CN114823294A
CN114823294A CN202110091020.4A CN202110091020A CN114823294A CN 114823294 A CN114823294 A CN 114823294A CN 202110091020 A CN202110091020 A CN 202110091020A CN 114823294 A CN114823294 A CN 114823294A
Authority
CN
China
Prior art keywords
layer
sacrificial layer
forming
mask
initial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110091020.4A
Other languages
Chinese (zh)
Inventor
赵猛
施雪捷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202110091020.4A priority Critical patent/CN114823294A/en
Publication of CN114823294A publication Critical patent/CN114823294A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched and an initial sacrificial layer positioned on the layer to be etched; forming a patterned structure on the initial sacrificial layer, wherein the patterned structure is internally provided with an opening which exposes a part of the surface of the initial sacrificial layer; removing part of the initial sacrificial layer by taking the graphical structure as a mask, and forming a groove in the initial sacrificial layer, wherein the depth of the groove is less than the thickness of the initial sacrificial layer; modifying the initial sacrificial layers on the side wall surface and the bottom surface of the groove by taking the graphical structure as a mask to form a modified layer, so that the initial sacrificial layer forms a sacrificial layer; after the modified layer is formed, forming a mask structure in the groove, wherein the surface of the mask structure is flush with the surface of the sacrificial layer; and after the mask structure is formed, removing the sacrificial layer, and forming a pattern structure on the layer to be etched, wherein the pattern structure comprises a modification layer and the mask structure positioned on the modification layer. The semiconductor structure formed by the method has a good appearance.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In the semiconductor field, in order to obtain a semiconductor structure having multiple functions, it is necessary to design a relatively complicated mask pattern for pattern transfer. At the front, middle and rear stages of the semiconductor process, one or more combinations of a Self-aligned Multiple patterning (SAMP), a Reverse exposure-etching-exposure-etching process (Reverse lithography-Etch-lithography, RLELE) and an etching process are usually used to form various semiconductor structures meeting the requirements.
With the further reduction of the size of the semiconductor structure, the precision of the existing lithography technology cannot meet the requirement of the size precision of the semiconductor structure. Therefore, a process of modifying a specific material to serve as a pattern transfer mask has been introduced.
However, the existing process of modifying a specific material to be used as a pattern transfer mask is still to be improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the process of modifying a specific material to be used as a pattern transfer mask.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched and an initial sacrificial layer positioned on the layer to be etched; forming a patterning structure on the initial sacrificial layer, wherein the patterning structure is internally provided with an opening, and the opening exposes part of the surface of the initial sacrificial layer; removing part of the initial sacrificial layer by taking the graphical structure as a mask, and forming a groove in the initial sacrificial layer, wherein the depth of the groove is smaller than the thickness of the initial sacrificial layer; modifying the initial sacrificial layers on the side wall surface and the bottom surface of the groove by taking the graphical structure as a mask to form a modified layer, so that the initial sacrificial layers form a sacrificial layer; after the modified layer is formed, forming a mask structure in the groove, wherein the surface of the mask structure is flush with the surface of the sacrificial layer; and after forming the mask structure, removing the sacrificial layer, and forming a pattern structure on the layer to be etched, wherein the pattern structure comprises a modification layer and the mask structure positioned on the modification layer.
Optionally, the material of the initial sacrificial layer comprises an amorphous material; the amorphous material comprises amorphous silicon.
Optionally, the process of modifying the initial sacrificial layer on the surface of the sidewall and the bottom surface of the groove includes an ion implantation process; the parameters of the ion implantation process include: the implanted ions comprise indium ions, the implantation energy is 100-200 kilo-electron volts, the implantation dosage is 1E 13-5E 14 per square centimeter, and the implantation angle is 0-5 degrees.
Optionally, the implanted ions further include carbon ions.
Optionally, the depth of the groove is one third to two thirds of the thickness of the initial sacrificial layer.
Optionally, the process of removing a part of the initial sacrificial layer includes a dry etching process.
Optionally, the patterning structure includes: a pad layer, an anti-reflection layer on the pad layer, and a photoresist layer on the anti-reflection layer.
Optionally, the forming method of the mask structure includes: forming a mask material layer in the groove and on the patterned structure; flattening the mask material layer until the surface of the patterned structure is exposed to form an initial mask structure; after the initial mask structure is formed, removing the graphical structure to expose the surface of the sacrificial layer; and after removing the graphical structure, flattening the initial mask structure until the initial mask structure is flush with the surface of the sacrificial layer to form the mask structure.
Optionally, the process for removing the sacrificial layer includes a dry etching process or a wet etching process.
Optionally, the material of the mask structure and the material of the sacrificial layer have different etching rates.
Optionally, the mask structure includes polysilicon or a dielectric material, and the dielectric material includes: silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, and silicon oxycarbonitride.
Optionally, after removing the sacrificial layer, the method further includes: and etching the layer to be etched by taking the mask structure and the modified layer as masks.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure in the technical scheme, the patterning structure is used as a mask to remove part of the initial sacrificial layer, the groove is formed in the initial sacrificial layer, the depth of the groove is smaller than the thickness of the initial sacrificial layer, then the patterning structure is used as a mask to modify the initial sacrificial layer on the side wall surface and the bottom surface of the groove, a modified layer is formed, and the initial sacrificial layer is made to form the sacrificial layer. The initial sacrificial layer at the bottom of the groove is thin, so that the modification degree of the modification layer formed by modification treatment is uniform, the appearance of the modification layer formed after the sacrificial layer is removed is good, and the size uniformity of the formed semiconductor structure is good when the pattern structure formed by the mask structure and the modification layer is used for pattern transfer.
Further, the implanted ions include indium ions. The lateral diffusion rate of the indium ions is slow, and thus, the thickness of the modified layer formed on the side wall of the groove is thin. And subsequently, when the mask structure and the modified layer are taken as masks to carry out pattern transfer continuously, the difference between the size of the formed semiconductor structure and the design size is smaller.
Further, the implanted ions include a mixture of indium ions and carbon ions. The carbon ions can repair defects generated in the ion implantation process, so that the diffusion effect of the indium ions is weakened.
Drawings
FIGS. 1 and 2 are schematic cross-sectional views illustrating a process for forming a semiconductor structure according to an embodiment;
fig. 3 to 9 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the existing process of modifying a specific material to be used as a pattern transfer mask needs to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment.
Referring to fig. 1, a layer to be etched 100 is provided; forming an initial sacrificial layer 101 on the layer to be etched 100; a patterned layer 102 is formed on the initial sacrificial layer 101, wherein the patterned layer 102 exposes a portion of the surface of the initial sacrificial layer 101.
Referring to fig. 2, ion implantation is performed on the initial sacrificial layer 101 by using the patterned layer 102 as a mask to form a modified layer 103 and a sacrificial layer 104.
In the semiconductor structure, amorphous silicon is generally used as a material of the initial sacrificial layer 101, boron ions are generally used as ions for performing ion implantation on the initial sacrificial layer 101, and the modified layer 103 formed after the ion implantation has a large etching selectivity ratio to the sacrificial layer 104, so that the modified layer 103 can be retained as a pattern in a subsequent process of removing the sacrificial layer 104.
However, since the lateral diffusion rate of the boron ions is fast, on one hand, the lateral diffusion phenomenon of the boron ions in the material of the initial sacrificial layer 101 is severe, so that the size of the formed modified layer 103 is much larger than the size of the initial sacrificial layer 101 exposed by the patterning layer 102, which makes the size of the formed semiconductor structure greatly different from the design size when the pattern of the modified layer 103 is transferred downward; on the other hand, the initial sacrificial layer 101 has a certain thickness, after the implanted ions enter the initial sacrificial layer 101, the energy of the implanted ions is attenuated along with the increase of the implantation depth, so that the implanted ions at the bottom and at the top of the initial sacrificial layer 101 are distributed unevenly, the bottom size of the formed modified layer 103 is uncontrollable, the top size and the bottom size of the modified layer 103 formed by removing the sacrificial layer 104 are uneven, and then the dimensions of the formed semiconductor structure are also uneven by transferring the patterns of the modified layer 103, so that the dimensions of the formed semiconductor structure are also uneven, and the dimensions of the semiconductor structure are affected.
In order to solve the above problems, a technical solution of the present invention provides a method for forming a semiconductor structure, in which a portion of an initial sacrificial layer is removed by using a patterned structure as a mask, a groove is formed in the initial sacrificial layer, a depth of the groove is smaller than a thickness of the initial sacrificial layer, and then the initial sacrificial layer on a sidewall surface and a bottom surface of the groove is modified by using the patterned structure as the mask to form a modified layer, so that the sacrificial layer is formed on the initial sacrificial layer. The initial sacrificial layer at the bottom of the groove is thin, so that the modification degree of the modification layer formed by modification treatment is uniform, the appearance of the modification layer formed after the sacrificial layer is removed is good, and the size uniformity of the formed semiconductor structure is good when the pattern structure formed by the mask structure and the modification layer is used for pattern transfer.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 9 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 3, a layer to be etched 200 and an initial sacrificial layer 201 on the layer to be etched 200 are provided.
The material of the initial sacrificial layer 201 comprises an amorphous material; the amorphous material comprises amorphous silicon.
The layer to be etched 200 includes: a substrate (not shown); a device layer (not shown) on the substrate, the device layer including an isolation structure (not shown) and a device structure (not shown) within the isolation structure, the device structure including a transistor, a diode, a transistor, a capacitor, an inductor, or a conductive structure, etc.
In this embodiment, the layer to be etched 200 further includes: a dielectric layer (not shown) located on the device layer; a conductive layer (not shown) within the dielectric layer, the conductive layer being electrically connected to the device structure.
In this embodiment, the substrate is made of silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
Referring to fig. 4, a patterned structure is formed on an initial sacrificial layer 201, the patterned structure has an opening 204 therein, and the opening 204 exposes a portion of the surface of the initial sacrificial layer 201.
The patterning structure includes: a pad layer 202, an anti-reflective layer 203 over the pad layer 202, and a photoresist layer (not shown) over the anti-reflective layer 203. The photoresist layer is naturally consumed in the process of forming the opening 204.
The forming method of the patterned structure comprises the following steps: forming a pad material layer (not shown) on the initial sacrificial layer 201, an anti-reflective material layer (not shown) on the pad material layer, and a photoresist layer (not shown) on the anti-reflective material layer, the photoresist layer exposing a portion of the surface of the anti-reflective material layer; and etching the anti-reflection material layer and the liner material layer by taking the photoresist layer as a mask until the surface of the initial sacrificial layer 201 is exposed, and forming the patterned structure and an opening 204 positioned in the patterned structure.
The material of the liner layer 202 comprises an amorphous material comprising amorphous silicon or amorphous carbon; the anti-reflective layer 203 comprises a thin silicon anti-reflective layer (Si-ARC), an organic material bottom anti-reflective layer (organic BARC), a dielectric anti-reflective layer (DARC), or a combination of an organic bottom anti-reflective layer and a dielectric anti-reflective layer.
Referring to fig. 5, using the patterned structure as a mask, a portion of the initial sacrificial layer 201 is removed, and a recess 205 is formed in the initial sacrificial layer 201, wherein a depth of the recess 205 is smaller than a thickness of the initial sacrificial layer 201.
The depth of the groove 205 is one third to two thirds of the thickness of the initial sacrificial layer 201. If the depth of the groove 205 is too deep, when the initial sacrificial layer 201 is etched to form the groove 205, the groove 205 with the sidewall plane perpendicular to the bottom plane is not easily obtained, and then, when the sidewall surface and the bottom surface of the groove 205 are subjected to modification treatment, a uniform modified layer is not easily obtained; if the depth of the groove 205 is too shallow, a larger process condition is required for performing subsequent modification treatment on the sidewall surface and the bottom surface of the groove 205, and it is difficult to obtain a uniform modified layer.
In this embodiment, the process of removing a portion of the initial sacrificial layer 201 includes a dry etching process. The dry etching process can form the groove 205 with good sidewall morphology.
Referring to fig. 6, the initial sacrificial layer 201 on the sidewall surface and the bottom surface of the recess 205 is modified by using the patterned structure as a mask to form a modified layer 206, so that the sacrificial layer 207 is formed on the initial sacrificial layer 201.
The materials of the modified layer 206 and the sacrificial layer 207 have a large etching selectivity ratio, so that the modified layer 206 is less damaged when the sacrificial layer 207 is subsequently removed.
In this embodiment, the process of modifying the initial sacrificial layer 201 on the sidewall surface and the bottom surface of the recess 205 includes an ion implantation process; the parameters of the ion implantation process include: the implanted ions comprise indium ions, the implantation energy is 100-200 kilo-electron volts, the implantation dosage is 1E 13-5E 14 per square centimeter, and the implantation angle is 0-5 degrees.
The implanted ions include indium ions. The lateral diffusion rate of the indium ions is slow, and thus the thickness of the modified layer 206 formed on the sidewall of the groove 205 is thin. Subsequently, when the mask structure and the modified layer 206 are used as masks to perform pattern transfer, the difference between the size of the formed semiconductor structure and the design size is small.
In the present embodiment, the implanted ions further include carbon ions, which can repair defects caused to the modified layer 206 by implantation, so that the diffusion degree of indium ions can be reduced.
The initial sacrificial layer 201 at the bottom of the groove 205 is thinner, so that the modification degree of the modified layer 206 formed by modification treatment is uniform, the modified layer 206 formed after the sacrificial layer 207 is subsequently removed has a better morphology, and the size uniformity of the formed semiconductor structure is better when pattern transfer is continued by using a pattern structure formed by the mask structure and the modified layer 206.
Next, after forming the modification layer 206, a mask structure 209 is formed in the recess 205. The forming process of the mask structure 209 please refer to fig. 7 and fig. 8.
Referring to fig. 7, a mask material layer (not shown) is formed in the recess 205 and on the patterned structure; the masking material layer is planarized until the patterned structure surface is exposed, forming an initial masking structure 208.
The mask structure comprises polysilicon or a dielectric material, the dielectric material comprising: silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, and silicon oxycarbonitride.
Referring to fig. 8, after the initial mask structure 208 is formed, the patterned structure is removed to expose the surface of the sacrificial layer 207; after removing the patterned structure, the initial mask structure 208 is planarized until it is flush with the surface of the sacrificial layer 207, forming the mask structure 209.
In this embodiment, the process of removing the patterned structure includes a dry etching process. The process of planarizing the initial mask structure 208 includes a chemical mechanical polishing process.
Referring to fig. 9, after forming the mask structure 209, the sacrificial layer 207 is removed, and a pattern structure is formed on the layer to be etched, where the pattern structure includes the modified layer 206 and the mask structure 209 located on the modified layer 206.
The process for removing the sacrificial layer 207 includes a dry etching process or a wet etching process.
The etching rates of the material of the mask structure 209 and the material of the sacrificial layer 207 are different, and the etching rates of the sacrificial layer 207 and the modification layer 206 are different, so that when the sacrificial layer 207 is removed, the damage of the mask structure 209 and the modification layer 206 is small, and the size accuracy and the appearance of a formed semiconductor structure are good when the pattern transmission is carried out by using a pattern structure formed by the mask structure 209 and the modification layer 206.
After removing the sacrificial layer 207, the method further includes: and etching the layer to be etched by taking the mask structure 209 and the modified layer 206 as masks. The process is a common process in the semiconductor field and is not described herein again.
At this point, the patterning structure is used as a mask to remove a part of the initial sacrificial layer 201, a groove 205 is formed in the initial sacrificial layer 201, the depth of the groove 205 is smaller than the thickness of the initial sacrificial layer 201, and then the patterning structure is used as a mask to modify the initial sacrificial layer 201 on the sidewall surface and the bottom surface of the groove 205 to form a modified layer 206, so that the sacrificial layer 207 is formed on the initial sacrificial layer 201. The initial sacrificial layer 201 at the bottom of the groove 205 is thinner, so that the modification degree of the modification layer 206 formed by modification treatment is uniform, the appearance of the modification layer formed after the sacrificial layer is removed is better, and the size uniformity of the formed semiconductor structure is better when the pattern transfer is continued by using the pattern structure formed by the mask structure 209 and the modification layer 206.
Further, the implanted ions include indium ions. The lateral diffusion rate of the indium ions is slow, and thus the thickness of the modified layer 206 formed on the sidewall of the groove 205 is thin. When the mask structure 209 and the modified layer 206 are used as masks to continue the pattern transfer, the size of the formed semiconductor structure has a small difference from the design size.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A method of forming a semiconductor structure, comprising:
providing a layer to be etched and an initial sacrificial layer positioned on the layer to be etched;
forming a patterning structure on the initial sacrificial layer, wherein the patterning structure is internally provided with an opening, and the opening exposes part of the surface of the initial sacrificial layer;
removing part of the initial sacrificial layer by taking the graphical structure as a mask, and forming a groove in the initial sacrificial layer, wherein the depth of the groove is smaller than the thickness of the initial sacrificial layer;
modifying the initial sacrificial layers on the side wall surface and the bottom surface of the groove by taking the graphical structure as a mask to form a modified layer, so that the initial sacrificial layers form a sacrificial layer;
after the modified layer is formed, forming a mask structure in the groove, wherein the surface of the mask structure is flush with the surface of the sacrificial layer;
and after forming the mask structure, removing the sacrificial layer, and forming a pattern structure on the layer to be etched, wherein the pattern structure comprises a modification layer and the mask structure positioned on the modification layer.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the initial sacrificial layer comprises an amorphous material; the amorphous material comprises amorphous silicon.
3. The method for forming a semiconductor structure according to claim 2, wherein the process for modifying the initial sacrificial layer on the sidewall surface and the bottom surface of the recess comprises an ion implantation process; the parameters of the ion implantation process include: the implanted ions comprise indium ions, the implantation energy is 100-200 kilo-electron volts, the implantation dosage is 1E 13-5E 14 per square centimeter, and the implantation angle is 0-5 degrees.
4. The method of forming a semiconductor structure of claim 3, wherein the implanted ions further comprise carbon ions.
5. The method of claim 1, wherein the depth of the recess is one-third to two-thirds of the thickness of the initial sacrificial layer.
6. The method of forming a semiconductor structure of claim 1, wherein the process of removing a portion of the initial sacrificial layer comprises a dry etching process.
7. The method of forming a semiconductor structure of claim 1, wherein the patterning the structure comprises: a pad layer, an anti-reflection layer on the pad layer, and a photoresist layer on the anti-reflection layer.
8. The method of forming a semiconductor structure of claim 1, wherein the method of forming the mask structure comprises: forming a mask material layer in the groove and on the patterned structure; flattening the mask material layer until the surface of the patterned structure is exposed to form an initial mask structure; after the initial mask structure is formed, removing the graphical structure to expose the surface of the sacrificial layer; and after removing the graphical structure, flattening the initial mask structure until the initial mask structure is flush with the surface of the sacrificial layer to form the mask structure.
9. The method of forming a semiconductor structure of claim 1, wherein the process of removing the sacrificial layer comprises a dry etching process or a wet etching process.
10. The method of claim 9, wherein the material of the mask structure has a different etch rate than the material of the sacrificial layer.
11. The method of forming a semiconductor structure of claim 10, wherein the mask structure comprises polysilicon or a dielectric material, the dielectric material comprising: silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, and silicon oxycarbonitride.
12. The method of forming a semiconductor structure of claim 1, further comprising, after removing the sacrificial layer: and etching the layer to be etched by taking the mask structure and the modified layer as masks.
CN202110091020.4A 2021-01-22 2021-01-22 Method for forming semiconductor structure Pending CN114823294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110091020.4A CN114823294A (en) 2021-01-22 2021-01-22 Method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110091020.4A CN114823294A (en) 2021-01-22 2021-01-22 Method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
CN114823294A true CN114823294A (en) 2022-07-29

Family

ID=82524668

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110091020.4A Pending CN114823294A (en) 2021-01-22 2021-01-22 Method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN114823294A (en)

Similar Documents

Publication Publication Date Title
US7713882B2 (en) Patterning method for a semiconductor substrate
US10211062B2 (en) Semiconductor structures and fabrication methods thereof
CN111370299A (en) Semiconductor structure and forming method thereof
CN107731666B (en) Double patterning method
US10957550B2 (en) Semiconductor structure and formation method thereof
US11114299B2 (en) Techniques for reducing tip to tip shorting and critical dimension variation during nanoscale patterning
CN114823294A (en) Method for forming semiconductor structure
CN210837709U (en) Shallow trench isolation structure and mask structure
CN104064474B (en) The fin structure manufacture method of Dual graphing fin transistor
CN106960816A (en) The method of Dual graphing
CN107785252B (en) Double patterning method
CN114284141A (en) Method for forming semiconductor structure
CN114530369A (en) Method for forming semiconductor structure
CN113808996A (en) Semiconductor structure and method for forming semiconductor structure
CN117936456A (en) Method for forming semiconductor structure
CN113327843B (en) Method for forming semiconductor structure
CN114530373A (en) Method for forming semiconductor structure
CN114823485A (en) Method for forming semiconductor structure
KR20070000719A (en) Method for forming bit line contact of semiconductor device
CN112670168B (en) Method for forming semiconductor structure and transistor
CN113808995A (en) Method for forming semiconductor structure
CN112542376A (en) Semiconductor structure and forming method thereof
CN116313776A (en) Hard mask removing method
KR100607724B1 (en) Method for manufacturing narrow gate line of semiconductor device
CN117954310A (en) Mask layer structure and forming method thereof and forming method of semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination