KR100607724B1 - Method for manufacturing narrow gate line of semiconductor device - Google Patents
Method for manufacturing narrow gate line of semiconductor device Download PDFInfo
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- KR100607724B1 KR100607724B1 KR1020020053620A KR20020053620A KR100607724B1 KR 100607724 B1 KR100607724 B1 KR 100607724B1 KR 1020020053620 A KR1020020053620 A KR 1020020053620A KR 20020053620 A KR20020053620 A KR 20020053620A KR 100607724 B1 KR100607724 B1 KR 100607724B1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 로직 디바이스(logic device)의 반도체 소자 제조에 있어서 고속 디바이스 구현을 위한 쇼트 채널 게이트(short channel gate)를 제조하는 방법에 관한 것이다. 종래의 쇼트 채널 게이트의 제조 공정은 노치 프로파일(notch profile) 형성으로 인해 내로우 게이트(narrow gate) 형성이 가능하게 되나, 노치 프로파일 형성을 위한 식각 공정의 재현성 문제가 대두되며 이로 인한 게이트 CD(Critical Dimension) 콘트롤에 어려움을 유발시키게 된다. 본 발명은 디자인 룰(design rule)이 줄어듬에 따라 내로우 게이트 라인을 형성하는데 있어서 패터닝 형성의 어려움을 보안함으로써 좀더 안정적인 고속 디바이스를 구현할 수 있다.The present invention relates to a method of manufacturing a short channel gate for high speed device implementation in the manufacture of semiconductor devices for logic devices. Conventional manufacturing processes of a short channel gate enable formation of a narrow gate due to formation of a notch profile. However, problems of reproducibility of the etching process for forming the notch profile arise, and the resulting gate CD Dimension control is difficult. The present invention can realize a more stable high-speed device by securing the difficulty of patterning formation in forming a narrow gate line according to reduction of design rule.
내로우, 게이트 산화막, 로직, 측벽Narrow, gate oxide, logic, sidewalls
Description
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 내로우 게이트 라인 제조 방법을 공정 단계별로 나타낸 단면도.1A to 1J are cross-sectional views illustrating a method of manufacturing narrow row gate lines of a semiconductor device according to the present invention.
본 발명은 반도체 소자(semiconductor device)의 내로우 게이트 라인(narrow gate line) 제조 방법에 관한 것으로, 특히, 로직 디바이스(logic device)의 반도체 소자 제조에 있어서 고속 디바이스 구현을 위한 쇼트 채널 게이트(short channel gate)를 제조하는 방법에 관한 것이다.사진 식각 공정만으로는 고속 디바이스 구현을 위한 쇼트 채널 게이트인 0.1um이하의 게이트 라인을 형성하기가 어렵다. 예로, 식각 공정(etching process)을 통한 노치 프로파일(notch profile)을 통해 내로우 게이트를 형성하는 방법은 실제 공정을 콘트롤(control)하기가 어렵기 때문에, 이 방법은 적용되기 어렵다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a narrow gate line of a semiconductor device and, more particularly, to a method of manufacturing a narrow gate line for a semiconductor device of a logic device, gate photolithography process. It is difficult to form a gate line of 0.1um or less which is a short channel gate for a high-speed device realization only by a photolithography process. For example, this method is difficult to apply because the method of forming the narrow gate through a notch profile through an etching process is difficult to control the actual process.
종래의 쇼트 채널 게이트의 제조 공정 예를 보면 다음과 같다.A conventional example of a manufacturing process of a short channel gate is as follows.
먼저, 실리콘 기판(silicon substrate) 위에 게이트 산화막(gate oxide)을 형성한다.First, a gate oxide is formed on a silicon substrate.
전표면에 폴리실리콘(polysilicon)을 증착(deposition)한다.Polysilicon is deposited on the entire surface.
게이트 라인을 형성하기 위하여 표면에 BARC 를 코팅(coating)한 후 게이트 패턴(gate pattern)을 형성한다.A gate pattern is formed after the BARC is coated on the surface to form a gate line.
BARC 를 식각한 후 EPD 장비를 이용하여 폴리실리콘을 식각한다. Etch the BARC and etch the polysilicon using EPD equipment.
오버식각(overetch)을 조절함으로써 노치 프로파일을 형성한다.Thereby forming a notch profile by controlling the overetch.
이와 같은 종래의 쇼트 채널 게이트의 제조 공정은 노치 프로파일 형성으로 인해 내로우 게이트 형성이 가능하게 되나, 노치 프로파일 형성을 위한 식각 공정의 재현성 문제가 대두되며 이로 인한 게이트 CD(Critical Dimension) 콘트롤에 어려움을 유발시키게 된다.In the conventional manufacturing process of the short channel gates, the narrow gate formation is possible due to the formation of the notch profile, but the problem of the reproducibility of the etching process for forming the notch profile arises and it is difficult to control the gate CD (critical dimension) .
본 발명은 상술한 결점을 해결하기 위하여 안출한 것으로, 미니 게이트(mini gate)를 이용하여 내로우 게이트를 안정적으로 콘트롤함과 동시에 이후 나이트라이드(nitride)를 식각하여 전체 폴리실리콘 라인을 형성할 수 있도록 하는 반도체 소자의 내로우 게이트 라인 제조 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in order to solve the aforementioned drawbacks, and it is an object of the present invention to stably control the narrow gate using a mini gate and to etch the nitride thereafter to form an entire polysilicon line. And a method for manufacturing a narrow gate line of a semiconductor device.
이와 같은 목적을 달성하기 위한 본 발명은, 기판 위에 게이트 산화막을 증착하는 제 1 단계; 전표면에 제 1 폴리실리콘을 형성하는 제 2 단계; 상기 제 1 폴리실리콘의 표면 미니 게이트 패턴(mini gate pattern) 영역에 제 1 포토 레지스트(Photo Resist : PR)를 형성하는 제 3 단계; 상기 제 1 포토 레지스트 영역 이외의 상기 제 1 폴리실리콘을 제거하여 게이트를 형성하는 제 4 단계; 상기 제 1 포토 레지스트를 제거하는 제 5 단계; 전표면에 나이트라이드를 형성하는 제 6 단계; 상기 나이트라이드 표면 탑 게이트 패턴(top gate pattern) 영역에 제 2 포토 레지스트를 형성하는 제 7 단계; 상기 제 2 포토 레지스트 영역 이외의 상기 나이트라이드를 상기 제 1 폴리실리콘 표면까지 제거하는 제 8 단계; 상기 제 2 포토 레지스트를 제거하는 제 9 단계; 전표면에 제 2 폴리실리콘을 형성하는 제 10 단계; 상기 제 2 폴리실리콘을 상기 나이트라이드 표면까지 평탄화하는 제 11 단계; 및 상기 나이트라이드에 에치 백 공정을 실시하여 상기 제 1, 제 2 폴리실리콘에 상기 나이트라이드로 이루어지는 측벽(sidewall)을 형성하는 제 12 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: a first step of depositing a gate oxide film on a substrate; A second step of forming a first polysilicon on the entire surface; A third step of forming a first photoresist (PR) in a surface mini gate pattern region of the first polysilicon; A fourth step of removing the first polysilicon except for the first photoresist region to form a gate; A fifth step of removing the first photoresist; A sixth step of forming nitride on the entire surface; A seventh step of forming a second photoresist on the nitride surface top gate pattern region; An eighth step of removing the nitride other than the second photoresist region to the first polysilicon surface; A ninth step of removing the second photoresist; A tenth step of forming second polysilicon on the entire surface; An eleventh step of planarizing the second polysilicon to the nitride surface; And a twelfth step of performing an etch-back process on the nitride to form a sidewall made of the nitride on the first and second polysilicon layers.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 내로우 게이트 라인 제조 방법을 공정 단계별로 나타낸 단면도이다.FIGS. 1A to 1J are cross-sectional views illustrating a method for manufacturing a narrow gate line of a semiconductor device according to the present invention.
먼저, 도 1a와 같이 실리콘 기판(10) 위에 게이트 산화막(12)을 증착한다.First, a
도 1b와 같이 전표면에 제 1 폴리실리콘(14)을 증착시킨다.The
도 1c와 같이 제 1 폴리실리콘(14)의 표면 미니 게이트 패턴 영역에 제 1 포토 레지스트(16)를 형성한다.1C, a
도 1d와 같이 건식 식각 공정을 수행하여 제 1 포토 레지스트(16) 영역 이외의 제 1 폴리실리콘(14)을 제거하여 게이트를 형성한다. 제 1 포토 레지스트(16)를 제거한다.A dry etching process is performed as shown in FIG. 1D to remove the
도 1e와 같이 전표면에 나이트라이드(18)를 증착시킨다.The
도 1f와 같이 나이트라이드(18) 표면 탑 게이트 패턴 영역에 제 2 포토 레지스트(20)를 형성한다.The
도 1g와 같이 건식 식각 공정을 수행하여 제 2 포토 레지스트(20) 영역 이외의 나이트라이드(18)를 제 1 폴리실리콘(14) 표면까지 엔드포인트(endpoint) 장비를 이용하여 제거한다. 제 2 포토 레지스트(20)를 제거한다.도 1h와 같이 전표면에 제 2 폴리실리콘(22)을 증착한다.The dry etching process is performed as shown in FIG. 1G to remove the
도 1i와 같이 에치 백 공정(etch back process) 또는 화학적 기계적 연마(Chemical Mechanical Polishing : CMP) 공정을 통해 제 2 폴리실리콘(22)을 나이트라이드(18) 표면까지 평탄화한다.The
도 1j와 같이 나이트라이드(18)에 에치 백 공정을 실시하여 제 1, 제 2 폴리실리콘(14, 22)에 나이트라이드(18)로 이루어지는 측벽을 형성한다.As shown in FIG. 1J, an etch-back process is performed on the
이상에서 설명한 바와 같이, 본 발명은 디자인 룰(design rule)이 줄어듬에 따라 내로우 게이트 라인을 형성하는데 있어서 패터닝 형성의 어려움을 보안함으로써 좀더 안정적인 고속 디바이스를 구현할 수 있다.As described above, the present invention can realize a more stable high-speed device by securing the difficulty of patterning formation in forming the narrow gate line according to reduction of the design rule.
Claims (5)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964343A (en) * | 1995-08-24 | 1997-03-07 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| KR19980016814A (en) * | 1996-08-29 | 1998-06-05 | 김광호 | How to form a gate line |
| KR19990060020A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Thin film transistor with gate insulating film |
| KR20000003486A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Gate electrode forming method of semiconductor device |
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2002
- 2002-09-05 KR KR1020020053620A patent/KR100607724B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964343A (en) * | 1995-08-24 | 1997-03-07 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| KR19980016814A (en) * | 1996-08-29 | 1998-06-05 | 김광호 | How to form a gate line |
| KR19990060020A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Thin film transistor with gate insulating film |
| KR20000003486A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Gate electrode forming method of semiconductor device |
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