KR20040022345A - Method for manufacturing narrow gate line of semiconductor device - Google Patents
Method for manufacturing narrow gate line of semiconductor device Download PDFInfo
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- KR20040022345A KR20040022345A KR1020020053620A KR20020053620A KR20040022345A KR 20040022345 A KR20040022345 A KR 20040022345A KR 1020020053620 A KR1020020053620 A KR 1020020053620A KR 20020053620 A KR20020053620 A KR 20020053620A KR 20040022345 A KR20040022345 A KR 20040022345A
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- South Korea
- Prior art keywords
- polysilicon
- nitride
- photoresist
- gate
- region
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Abstract
Description
본 발명은 반도체 소자(semiconductor device)의 내로우 게이트 라인(narrow gate line) 제조 방법에 관한 것으로, 특히, 로직 디바이스(logic device)의 반도체 소자 제조에 있어서 고속 디바이스 구현을 위한 쇼트 채널 게이트(short channel gate)를 제조하는 방법에 관한 것이다.사진 식각 공정만으로는 고속 디바이스 구현을 위한 쇼트 채널 게이트인 0.1um이하의 게이트 라인을 형성하기가 어렵다. 예로, 식각 공정(etching process)을 통한 노치 프로파일(notch profile)을 통해 내로우 게이트를 형성하는 방법은 실제 공정을 콘트롤(control)하기가 어렵기 때문에, 이 방법은 적용되기 어렵다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a narrow gate line of a semiconductor device, and more particularly, a short channel gate for implementing a high speed device in manufacturing a semiconductor device of a logic device. A photolithography process alone is difficult to form a gate line of less than 0.1um, which is a short channel gate for high-speed device implementation. For example, the method of forming a narrow gate through a notch profile through an etching process is difficult to control because it is difficult to control the actual process.
종래의 쇼트 채널 게이트의 제조 공정 예를 보면 다음과 같다.An example of a manufacturing process of a conventional short channel gate is as follows.
먼저, 실리콘 기판(silicon substrate) 위에 게이트 산화막(gate oxide)을형성한다.First, a gate oxide film is formed on a silicon substrate.
전표면에 폴리실리콘(polysilicon)을 증착(deposition)한다.Polysilicon is deposited on the entire surface.
게이트 라인을 형성하기 위하여 표면에 BARC 를 코팅(coating)한 후 게이트 패턴(gate pattern)을 형성한다.In order to form a gate line, a coating of BARC on the surface is performed to form a gate pattern.
BARC 를 식각한 후 EPD 장비를 이용하여 폴리실리콘을 식각한다.After etching BARC, polysilicon is etched using EPD equipment.
오버식각(overetch)을 조절함으로써 노치 프로파일을 형성한다.The notch profile is formed by adjusting the overetch.
이와 같은 종래의 쇼트 채널 게이트의 제조 공정은 노치 프로파일 형성으로 인해 내로우 게이트 형성이 가능하게 되나, 노치 프로파일 형성을 위한 식각 공정의 재현성 문제가 대두되며 이로 인한 게이트 CD(Critical Dimension) 콘트롤에 어려움을 유발시키게 된다.In the conventional short channel gate manufacturing process, a narrow gate can be formed due to the formation of a notch profile, but a problem of reproducibility of an etching process for forming a notch profile arises, resulting in difficulty in controlling gate critical dimensions (CD). It is triggered.
본 발명은 상술한 결점을 해결하기 위하여 안출한 것으로, 미니 게이트(mini gate)를 이용하여 내로우 게이트를 안정적으로 콘트롤함과 동시에 이후 나이트라이드(nitride)를 식각하여 전체 폴리실리콘 라인을 형성할 수 있도록 하는 반도체 소자의 내로우 게이트 라인 제조 방법을 제공하는 데 그 목적이 있다.The present invention has been made to solve the above-described drawbacks, and it is possible to stably control the narrow gate using a mini gate and subsequently to nitride to form the entire polysilicon line. It is an object of the present invention to provide a narrow gate line manufacturing method of a semiconductor device.
이와 같은 목적을 달성하기 위한 본 발명은, 기판 위에 게이트 산화막을 증착하는 제 1 단계; 전표면에 제 1 폴리실리콘을 형성하는 제 2 단계; 상기 제 1 폴리실리콘의 표면 미니 게이트 패턴(mini gate pattern) 영역에 제 1 포토 레지스트(Photo Resist : PR)를 형성하는 제 3 단계; 상기 제 1 포토 레지스트 영역 이외의 상기 제 1 폴리실리콘을 제거하여 게이트를 형성하는 제 4 단계; 상기제 1 포토 레지스트를 제거하는 제 5 단계; 전표면에 나이트라이드를 형성하는 제 6 단계; 상기 나이트라이드 표면 탑 게이트 패턴(top gate pattern) 영역에 제 2 포토 레지스트를 형성하는 제 7 단계; 상기 제 2 포토 레지스트 영역 이외의 상기 나이트라이드를 상기 제 1 폴리실리콘 표면까지 제거하는 제 8 단계; 상기 제 2 포토 레지스트를 제거하는 제 9 단계; 전표면에 제 2 폴리실리콘을 형성하는 제 10 단계; 상기 제 2 폴리실리콘을 상기 나이트라이드 표면까지 평탄화하는 제 11 단계; 및 상기 나이트라이드에 에치 백 공정을 실시하여 상기 제 1, 제 2 폴리실리콘에 상기 나이트라이드로 이루어지는 측벽(sidewall)을 형성하는 제 12 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, the first step of depositing a gate oxide film on a substrate; Forming a first polysilicon on the entire surface; A third step of forming a first photo resist (PR) in a surface mini gate pattern region of the first polysilicon; A fourth step of forming a gate by removing the first polysilicon other than the first photoresist region; A fifth step of removing the first photoresist; A sixth step of forming nitride on the entire surface; A seventh step of forming a second photoresist in the nitride surface top gate pattern region; An eighth step of removing the nitride other than the second photoresist region to the surface of the first polysilicon; A ninth step of removing the second photoresist; A tenth step of forming a second polysilicon on the entire surface; An eleventh step of planarizing the second polysilicon to the nitride surface; And a twelfth step of performing an etch back process on the nitride to form sidewalls of the nitride on the first and second polysilicon.
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 내로우 게이트 라인 제조 방법을 공정 단계별로 나타낸 단면도.1A to 1J are cross-sectional views showing a narrow gate line manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 내로우 게이트 라인 제조 방법을 공정 단계별로 나타낸 단면도이다.1A to 1J are cross-sectional views illustrating a narrow gate line manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention.
먼저, 도 1a와 같이 실리콘 기판(10) 위에 게이트 산화막(12)을 증착한다.First, a gate oxide film 12 is deposited on the silicon substrate 10 as shown in FIG. 1A.
도 1b와 같이 전표면에 제 1 폴리실리콘(14)을 증착시킨다.1B, the first polysilicon 14 is deposited on the entire surface.
도 1c와 같이 제 1 폴리실리콘(14)의 표면 미니 게이트 패턴 영역에 제 1 포토 레지스트(16)를 형성한다.As shown in FIG. 1C, the first photoresist 16 is formed in the surface mini gate pattern region of the first polysilicon 14.
도 1d와 같이 건식 식각 공정을 수행하여 제 1 포토 레지스트(16) 영역 이외의 제 1 폴리실리콘(14)을 제거하여 게이트를 형성한다. 제 1 포토 레지스트(16)를 제거한다.As shown in FIG. 1D, a dry etching process is performed to remove the first polysilicon 14 other than the first photoresist 16 region to form a gate. The first photoresist 16 is removed.
도 1e와 같이 전표면에 나이트라이드(18)를 증착시킨다.The nitride 18 is deposited on the entire surface as shown in FIG. 1E.
도 1f와 같이 나이트라이드(18) 표면 탑 게이트 패턴 영역에 제 2 포토 레지스트(20)를 형성한다.As shown in FIG. 1F, the second photoresist 20 is formed in the top gate pattern region of the nitride 18 surface.
도 1g와 같이 건식 식각 공정을 수행하여 제 2 포토 레지스트(20) 영역 이외의 나이트라이드(18)를 제 1 폴리실리콘(14) 표면까지 엔드포인트(endpoint) 장비를 이용하여 제거한다. 제 2 포토 레지스트(20)를 제거한다.도 1h와 같이 전표면에 제 2 폴리실리콘(22)을 증착한다.The dry etching process is performed as shown in FIG. 1G to remove the nitrides 18 other than the second photoresist 20 region to the surface of the first polysilicon 14 using endpoint equipment. The second photoresist 20 is removed. A second polysilicon 22 is deposited on the entire surface as shown in FIG. 1H.
도 1i와 같이 에치 백 공정(etch back process) 또는 화학적 기계적 연마(Chemical Mechanical Polishing : CMP) 공정을 통해 제 2 폴리실리콘(22)을 나이트라이드(18) 표면까지 평탄화한다.As shown in FIG. 1I, the second polysilicon 22 is planarized to the surface of the nitride 18 through an etch back process or a chemical mechanical polishing (CMP) process.
도 1j와 같이 나이트라이드(18)에 에치 백 공정을 실시하여 제 1, 제 2 폴리실리콘(14, 22)에 나이트라이드(18)로 이루어지는 측벽을 형성한다.As shown in FIG. 1J, an etch back process is performed on the nitride 18 to form sidewalls formed of the nitride 18 on the first and second polysilicon 14 and 22.
이상에서 설명한 바와 같이, 본 발명은 디자인 룰(design rule)이 줄어듬에 따라 내로우 게이트 라인을 형성하는데 있어서 패터닝 형성의 어려움을 보안함으로써 좀더 안정적인 고속 디바이스를 구현할 수 있다.As described above, the present invention can implement a more stable high-speed device by securing the difficulty of patterning in forming the narrow gate line as the design rule is reduced.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020053620A KR100607724B1 (en) | 2002-09-05 | 2002-09-05 | Method for manufacturing narrow gate line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020053620A KR100607724B1 (en) | 2002-09-05 | 2002-09-05 | Method for manufacturing narrow gate line of semiconductor device |
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| KR20040022345A true KR20040022345A (en) | 2004-03-12 |
| KR100607724B1 KR100607724B1 (en) | 2006-08-01 |
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| JPH0964343A (en) * | 1995-08-24 | 1997-03-07 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| KR19980016814A (en) * | 1996-08-29 | 1998-06-05 | 김광호 | How to form a gate line |
| KR100580384B1 (en) * | 1997-12-31 | 2006-08-03 | 삼성전자주식회사 | Thin Film Transistor with Gate Insulation |
| KR100321710B1 (en) * | 1998-06-29 | 2002-05-13 | 박종섭 | Method for forming gate electrode of semiconductor device |
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