KR20040003922A - Method of manufacturing gate electrode in non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a gate electrode of a non-volatile memory device is provided to be capable of reducing the thickness increasing phenomenon of an interlayer dielectric. CONSTITUTION: A gate electrode structure is formed at the upper portion of a semiconductor substrate(100), wherein the semiconductor substrate includes a tunnel oxide layer(102). At this time, the gate electrode structure includes the first conductive pattern(104a), an interlayer dielectric pattern(112a), and the second conductive pattern(114a). An oxide layer(122b) is formed at the outer surface of the semiconductor substrate and the gate electrode structure by carrying out the first oxidation process at the resultant structure at the temperature of 600 °C, or less. Then, the second oxidation process is carried out at the resultant structure under oxygen and nitrogen gas atmosphere.

Description

Method of manufacturing gate electrode in non-volatile memory device

The present invention relates to a method of manufacturing a gate electrode, and more particularly, to a method of manufacturing a nonvolatile memory device capable of reducing the size of the gate electrode of the nonvolatile memory device.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output.

Nonvolatile memory devices have an almost indefinite storage capacity, and there is an increasing demand for flash memory capable of electrically inputting and outputting data such as electrically erasable and programmable ROM (EEPROM). Memory cells in these devices generally have a vertically stacked gate structure with floating gates formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate.

In flash memory cells having this structure, data is stored by applying an appropriate voltage to the control gate and the substrate to insert or draw electrons into the floating gate. At this time, the dielectric film functions to maintain a potential on the floating gate.

A method of manufacturing such a nonvolatile memory device is described in US Pat. No. 6,291,297 (issued to Chen Chiou-Feng. Et al) and Japanese Unexamined Patent Publication No. 6-085278 (issued to OJI YUZURU. Et al).

1A to 1C are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device by a conventional method.

Referring to FIG. 1A, a tunnel oxide layer 12 is formed on a semiconductor substrate 10 divided into an active region and a field region. The first silicon layer 14 for floating gate is deposited on the tunnel oxide layer 12 and then doped with a high concentration of N-type. Subsequently, the first oxide layer 16, the nitride layer 18, and the second oxide layer 20 are sequentially formed as the interlayer dielectric layer 22 for insulating the floating gate and the control gate on the first silicon layer. The second silicon layer 24 and the metal-silicide layer 26 for the control gate are deposited on the interlayer dielectric layer 22. A mask pattern 28 for gate patterning is formed on the metal silicide layer 26.

Referring to FIG. 1B, the metal silicide layer 26, the second silicon layer 24, the interlayer dielectric layer 22, and the first silicon layer 14 are continuously formed using the mask pattern 28 as an etching mask. Anisotropic Etch. Then, a stack type of memory cell having a floating gate made of the first silicon layer pattern 14a and a control gate 24a, 26a made of the second silicon layer pattern 24a and the metal-silicide layer pattern 26a. Gates are formed.

Here, the interlayer dielectric film 22 represents a first oxide film pattern 16a, a nitride film pattern 18a, and a second oxide film pattern 20a, respectively.

Referring to FIG. 1C, as described above, the gate patterning process is performed after the gate patterning process. Then, sidewalls of the floating gate 14a and the control gates 24a and 26a are oxidized to form an oxide film 30.

However, in the gate oxidation process, an oxidant penetrates into the side surface of the second oxide layer pattern 20a under the control gates 24a and 26a to form a buzz-beak as illustrated in FIG. 1C. Similarly, an oxidant penetrates into the side surface of the first oxide film pattern 16a on the floating gate 14a to form the buzz-beak. Therefore, the thickness of the interlayer dielectric film 22 is increased by the buzz-beak, thereby causing a problem in that the characteristic distribution of the cell is increased.

That is, in order to reduce the characteristic scatter of the cell, the gate size must be reduced in the photolithography process for gate patterning, and as the line width of the gate decreases, the interlayer due to the buzz-beak in the gate oxidation process performed after the gate patterning is performed. The increase in dielectric film thickness is increased. Since the increase in the thickness of the interlayer dielectric film is increased as the thickness of the oxide film 30 becomes thicker, reducing the thickness of the oxide film 30 may solve a problem in that characteristic scattering of the cell becomes larger. However, since reducing the thickness of the oxide film 30 deteriorates data retention characteristics, there is a limit to reducing the thickness of the oxide film 30.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of improving the spread of cells by reducing the thickness increase phenomenon of the interlayer dielectric film generated during the gate oxidation process.

1A and 1C are cross-sectional views illustrating a method of manufacturing a gate electrode of a nonvolatile memory device according to a conventional method.

2A to 2D are cross-sectional views illustrating a method of manufacturing a gate electrode of a nonvolatile memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel oxide film

104: first conductive layer 106: first oxide film

108: nitride film 110: second oxide film

112: interlayer dielectric film 114: second conductive layer

116 metal-silicide film 118 mask layer

122a, 122b: oxide film

The present invention to achieve the above object,

Forming a gate electrode structure including a first conductive layer pattern, an interlayer dielectric layer pattern, and a second conductive layer pattern on the semiconductor substrate on which the tunnel oxide layer is formed;

By performing the primary oxidation process at a temperature of less than 600 ℃ to the result, to suppress the increase of the thickness due to the bud-beak at the interface between the oxide film pattern and the interlayer dielectric film pattern in contact with the first and second conductive layer pattern Forming an oxide film on an outer surface of the semiconductor substrate and the gate electrode structure; And

The present invention provides a method of manufacturing a gate electrode of a nonvolatile memory device, wherein the secondary oxidation process is performed at a temperature higher than the primary oxidation while providing a gas containing oxygen and nitrogen to the resultant.

According to the present invention, a low-temperature thermal oxide film formation process or an oxide film deposition process is performed on a semiconductor substrate on which a gate structure is formed, thereby reducing the buzz-beak phenomenon of the interlayer dielectric layer pattern and the tunnel oxide film included in the gate structure in a subsequent heat treatment process. You can.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing a gate electrode of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2A, the semiconductor substrate 100 is divided into an active region and a field region through a device isolation process such as shallow trench isolation (STI).

Specifically, after forming the trench by etching the semiconductor substrate 100 to a predetermined depth, an oxide film is deposited by chemical vapor deposition (CVD) to fill the trench. Next, the CVD-oxide film is etched by an etch back or chemical mechanical polishing (CMP) method to form a field oxide film only inside the trench.

In addition, the field region may be formed by a conventional local oxidation of silicon (LOCOS) process, and self-aligned shallow trench isolation that simultaneously forms a floating gate and an active region. And SA-STI) process.

A thermal oxidation process is performed on the semiconductor substrate 100 to form a tunnel oxide film 102 having a thickness of about 50 to about 80 microns.

Subsequently, the first conductive layer 104 for the floating gate is deposited on the tunnel oxide film 102 formed on the semiconductor substrate 100 to a thickness of about 800 to 1400 Å. For example, the first conductive layer 104 uses poly-silicon or amorphous silicon.

In addition, the first conductive layer 104 is implanted with a high concentration of N-type impurities by POCl ₃ diffusion, ion implantation, or in-situ doping, which is a common doping method, and then the first conductive layer on the field region by photolithography. Optionally remove 104.

Subsequently, an interlayer dielectric film 112 having an ONO structure is formed on the first conductive layer 104 and the substrate 100 to insulate the floating gate and the control gate. The interlayer dielectric film 112 is formed by performing a conventional thermal oxidation process or a chemical vapor deposition process.

The interlayer dielectric film 112 formed by the chemical vapor deposition process has a structure in which the first oxide film 106, the nitride film 108, and the second oxide film 110 are sequentially stacked, and specifically, the first conductive layer The first oxide film 106 is deposited on the 104 to a thickness of 40 to 70 kPa by chemical vapor deposition, preferably low pressure chemical vapor deposition (LPCVD), at a temperature of about 700 to 750 ° C. do.

Subsequently, first annealing is performed in an NO or N ₂ O atmosphere to densify the first oxide film 106. After depositing a nitride film 108 having a thickness of about 30 to 80 kPa on the first oxide film 106 by LPCVD, chemical vapor deposition of the second oxide film 110 on the nitride film at a temperature of about 700 to 750 ° C. More preferably, it is deposited to a thickness of about 40 to 60 kPa by the LPCVD method.

Subsequently, a second annealing is performed in an NO or N ₂ O atmosphere to densify the second oxide film 110. Then, an interlayer dielectric film 112 made of LPCVD-ONO is formed. The second conductive layer 114 for the control gate is formed by applying a polysilicon layer doped with an N ⁺ type on the interlayer dielectric film 112 to have a thickness of 700 to 1200 GPa.

In addition, a metal silicide layer 116 such as tungsten silicide (WSix), titanium silicide (TiSix), and tantalum silicide (TaSix), which are low resistance materials, may be formed on the second conductive layer 114 to have a thickness of 100 to 1200 Å. do.

A mask layer 118 for gate patterning is formed on the metal-silicide layer 116. The mask layer 118 is formed of a single film of an oxide film or a nitride film or a composite film of an oxide film and a nitride film.

Referring to FIG. 2B, the mask layer is etched by a photolithography process to form a hard mask layer pattern 118a defining a gate region.

The metal-silicide layer 116, the second conductive layer 114, the interlayer dielectric layer 112, and the first conductive layer 104 are sequentially patterned using the mask layer pattern 118a as an etching mask. A gate electrode including a layer pattern 118a, a metal-silicide layer pattern 116a, a second conductive layer pattern 114a, an interlayer dielectric layer pattern 112a, a first conductive layer pattern 104a, and a tunnel oxide layer 102 Form the structure. Reference numerals 106a, 108a, and 110a denote first oxide film patterns, nitride film patterns, and second oxide film patterns constituting the interlayer dielectric film 112, respectively.

2C to 2D, the resulting gate electrode structure and the conductive material of the floating gate 104a and the control gates 114a and 116a on the entire surface of the exposed semiconductor substrate 100 may be less than about 600 ° C. The low temperature first oxidation process is carried out using active oxygen such as ozone, plasma, and radicals at the temperature. Then, the thermal oxide layer 122a is formed on the outer side of the gate structure and the exposed semiconductor substrate 100.

If the first oxidation process is performed at a high temperature exceeding 600 ° C., the tunnel oxide film 102 in contact with the first conductive layer pattern 104a and the second conductive layer pattern 114a included in the gate structure, The diffusion of the oxidant (Oxidant) proceeds rapidly along the interface between the first oxide layer pattern 106a and the second oxide layer pattern 110a, and the interlayer dielectric layer pattern 112a and the tunnel oxide layer 102 are formed thicker and excessive. Bird's beak phenomenon occurs.

Subsequently, since the low-temperature thermal oxide film 122a formed on the entire surface of the gate structure has lower characteristics than the oxide film formed at high temperature, a second oxidation process of 600 ° C. or higher is subsequently performed under an atmosphere of nitrogen or oxygen gas. Thus, the conductive materials of the first conductive layer pattern 104a and the second conductive layer pattern 114a included in the gate electrode structure are crystallized and suppress the increase in the thickness of the interlayer dielectric layer and the tunnel oxide layer. The thickness of the thermal oxide film 122a may be improved to improve characteristics of the gate electrode.

However, since the oxidation enhancement phenomenon caused by the oxidation process depends on the concentration, oxidation temperature, and type of oxidation of the implanted dopant, the thickness of the oxide film in the ion implanted region and the oxide film in the non-ion implanted region In order to control the thickness ratio of, dopant type and concentration, and oxidation temperature and type should be properly adjusted.

In another embodiment, a chemical vapor deposition method or an atomic layer deposition method may be performed on the resultant gate structure and the exposed semiconductor substrate 100 to form a deposition oxide film 122b having a thickness of 50 mV or less. In addition, by performing a high temperature heat treatment process exceeding 600 ° C. under an atmosphere of nitrogen or oxygen gas, the thickness of the deposition oxide film 122b is improved. Accordingly, the conductive material of the first and second conductive layers included in the gate structure is crystallized, and the thickness of the low-temperature thermal oxide film 122a is improved without increasing the thickness of the interlayer dielectric film and the tunnel oxide film. Characteristics are improved.

As described above, according to the present invention, the oxide film formed outside the gate electrode in a low temperature oxide film forming process may include the first and second conductive layer patterns and the tunnel oxide film included in the gate structure by heat used in a subsequent manufacturing process. It is possible to prevent the oxide material from being diffused along the interface between the first and second oxide film patterns, and to prevent the oxide film from being formed thicker and from excessive bud's beak. Therefore, the increase in the thickness of the interlayer dielectric film 112 may be prevented, thereby improving cell characteristic distribution.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Forming a gate electrode structure including a first conductive layer pattern, an interlayer dielectric layer pattern, and a second conductive layer pattern on the semiconductor substrate on which the tunnel oxide layer is formed; A tunnel oxide film and an interlayer dielectric film contacting the first and second conductive layer patterns by forming an oxide film on an outer surface of the semiconductor substrate and the gate electrode structure by performing a first oxidation process at a temperature of 600 ° C. or less. Suppressing an increase in thickness due to the bud-beak phenomenon at the interface of the pattern; And And performing a secondary oxidation process at a higher temperature than the primary oxidation while providing a gas containing oxygen and nitrogen to the resultant. The method of claim 1, wherein the first conductive layer pattern and the second conductive layer pattern are made of poly-silicon or amorphous silicon. The method of claim 1, further comprising forming a metal-silicide pattern, which is a low resistance material, on the second conductive layer pattern. The method of claim 1, wherein the interlayer dielectric film has a structure in which a first oxide film, a nitride film, and a second oxide film are sequentially stacked. The method of claim 1, wherein the oxide layer is formed by performing a low temperature thermal oxidation process using active oxygen such as ozone, plasma, and radicals. The method of claim 1, wherein the oxide layer is formed by performing a chemical vapor deposition method or an atomic layer deposition method.