CN103137551B - Method for forming holes in grooves - Google Patents
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- CN103137551B CN103137551B CN201110398280.2A CN201110398280A CN103137551B CN 103137551 B CN103137551 B CN 103137551B CN 201110398280 A CN201110398280 A CN 201110398280A CN 103137551 B CN103137551 B CN 103137551B
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Abstract
The invention provides a method for forming holes in grooves. According to the method, a semiconductor substrate is supplied in advance, wherein one surface of the semiconductor substrate sequentially comprises a first etching termination layer and a first polymer layer from bottom to top; a first patterned light-resistance adhesive layer is formed on the surface of the first polymer layer, and the critical dimension (CD) of the grooves is defined in an area covered by the patterned light-resistance adhesive layer; the patterned light-resistance adhesive layer is used as a masking film, and the first polymer layer is etched till the first etching termination layer is exposed; a dielectric layer and a sacrificial layer are sequentially deposited on the first etching termination layer and the surface of the etched first polymer layer; chemical mechanical lapping is conducted on the sacrificial layer and the dielectric layer till the first polymer layer is exposed; the first polymer layer is removed through thermal decomposition to form the grooves, and the first etching termination layer in the grooves is removed; metallic copper is filled in the grooves; and the sacrificial layer is removed, and the holes in the grooves are formed. The invention further provides another method for forming the holes in the grooves. With the method for forming the holes in the grooves, a process window when the metallic copper is aligned with a lower layer connecting hole can be enlarged.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly between a kind of groove, form the method for hole.
Background technology
At present, along with the development of integrated circuit, the number of plies of back segment metal interconnecting layer is more and more intensive, in order to reduce the resistance capacitance (RC) of whole integrated circuit (IC), postpones, the electric property that improves device, prior art provides a kind of method that forms hole between groove:
Step 11, refer to Fig. 1 a, semi-conductive substrate 100 is provided in advance, described Semiconductor substrate 100 surfaces comprise the first etch stop layer 101 and interlayer dielectric layer (Inter-layer dielectric, ILD) 102 from bottom to top successively; Interlayer dielectric layer 102 is carried out to etching, and etching stopping forms groove on the first etch stop layer 101, and in groove, fills metallic copper 103 formation when a layer metal interconnecting layer; Interlayer dielectric layer generally adopts low-k (Low-K) insulation material layer, black diamond (black diamond, BD) material, unadulterated silicate glass (USG) or the fluoride glass (FSG) etc. that for example contain the similar oxide (Oxide) of silicon, oxygen, carbon, protium;
Step 12, refer to Fig. 1 b, form when layer metal interconnecting layer surface deposition second etch stop layer 104;
Step 13, refer to Fig. 1 c, on the second etch stop layer 104 surfaces, form the photoresistance glue-line 105 of patternings, in the opening of the photoresistance glue-line of described patterning, comprise the interlayer dielectric layer between presumptive area metallic copper and metallic copper;
Wherein, the opening of photoresistance glue-line is typically chosen in groove than the region of comparatively dense.
Step 14, refer to Fig. 1 d, the photoresistance glue-line 105 of patterning of take is mask, etching the second etch stop layer 104;
Step 15, refer to Fig. 1 e, second etch stop layer 104 of take is mask, and interlayer dielectric layer 102 to first etch stop layer 101 surfaces between etching metallic copper form a plurality of holes 106 103 of metallic coppers.
In hole, be full of air, the dielectric constant of air is 1, and the dielectric constant of FSG and USG is greater than 3, and the dielectric constant of BD is 2.7～3, and from relatively can finding out of dielectric constant, the formation of hole declines the overall dielectric constant of interlayer dielectric layer.It should be noted that and after step 15, need to deposit the etch stop layer of lower floor and the interlayer dielectric layer of lower floor, and form connecting hole thereon, connecting hole is electrically connected with the metallic copper when layer metal interconnecting layer.Although having reached, said method reduces the object that integrated circuit RC postpones, but the restriction due to manufacturing process itself, for the less semiconductor device of critical size (CD), (space) is less at interval between metallic copper, the connecting hole of lower floor is easy to misalignment when layer metallic copper, and be communicated with the hole on side, the metallic copper of filling in the connecting hole of lower floor is dropped in hole, causes the short circuit problem of device.
Therefore, for small size semiconductor device, how to increase metallic copper and lower floor's connecting hole to punctual process window, become the problem that needs in the industry solution.
Summary of the invention
In view of this, the technical problem that the present invention solves is: how to increase metallic copper and lower floor's connecting hole to punctual process window.
For solving the problems of the technologies described above, technical scheme of the present invention is specifically achieved in that
The invention provides a kind of method that forms hole between groove, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the first etch stop layer and the first polymeric layer from bottom to top successively; On the surface of the first polymeric layer, form the first photoresistance glue-line of patterning, the critical size CD of the first photoresistance glue-line institute overlay area definition groove of patterning; The the first photoresistance glue-line of patterning of take is mask, and etching the first polymeric layer is to manifesting the first etch stop layer;
The first polymeric layer surface after the first etch stop layer and etching is dielectric layer and sacrifice layer successively;
Cmp sacrifice layer and dielectric layer are to manifesting the first polymeric layer;
Thermal decomposition is removed the first polymeric layer and is formed groove, and removes the first etch stop layer in groove;
In groove, fill metallic copper;
Deposit the second etch stop layer; On the second etch stop layer surface, form the second photoresistance glue-line of patterning, the corresponding presumptive area sacrifice layer of opening of the second photoresistance glue-line of described patterning;
The the second photoresistance glue-line of patterning of take is mask, etching the second etch stop layer; Remove sacrifice layer, form the hole between groove.
Described medium thickness 20～200 dusts.
The dielectric constant of described dielectric layer is 2～3.
Described dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2layer or carbonitride of silicium SiNC layer.
After forming the hole between groove, the method further comprises and deposits successively the etch stop layer of lower floor and the interlayer dielectric layer of lower floor.
The present invention also provides a kind of method that forms hole between groove, is applied in the last part technology of semiconductor device, and the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the first etch stop layer and the first polymeric layer from bottom to top successively; On the surface of the first polymeric layer, form the first photoresistance glue-line of patterning, the critical size CD of the first photoresistance glue-line institute overlay area definition groove of patterning; The the first photoresistance glue-line of patterning of take is mask, and etching the first polymeric layer is to manifesting the first etch stop layer;
The first polymeric layer surface after the first etch stop layer and etching is dielectric layer and the second polymer layer successively;
Cmp the second polymer layer and dielectric layer are to manifesting the first polymeric layer;
Thermal decomposition is removed the first polymeric layer and is formed groove, and removes the first etch stop layer in groove;
In groove, fill metallic copper;
Deposit opercular layer cap layer;
See through and have opercular layer thermal decomposition to remove the second polymer layer, form the hole between groove.
The heat decomposition temperature of described the second polymer layer is higher than 40～50 degrees Celsius of the first polymeric layers.
Described medium thickness 20～200 dusts.
The dielectric constant of described dielectric layer is 2～3.
Described dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2layer or carbonitride of silicium SiNC layer.
As seen from the above technical solutions, the dielectric layer that the present invention adds is positioned at the sidewall of metallic copper, increased metallic copper and lower floor's connecting hole to punctual process window, for the less semiconductor device of size, the connecting hole that also can realize lower floor with when a layer metallic copper, aim at.And, only have metallic copper to compare with prior art Hole side, metallic copper sidewall of the present invention is provided with dielectric layer, dielectric layer and metallic copper support the etch stop layer of lower floor and the interlayer dielectric layer of lower floor jointly, mechanical stability is higher, and the etch stop layer of lower floor and more difficult the caving in of the interlayer dielectric layer of lower floor are dropped in hole.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the concrete generalized section that forms the method for hole between prior art groove.
Fig. 2 forms the schematic flow sheet of the method for hole between first embodiment of the invention groove.
Fig. 2 a to Fig. 2 g is the concrete generalized section that forms the method for hole between first embodiment of the invention groove.
Fig. 2 h is that first embodiment of the invention is having the cross-sectional view of lower floor's etch stop layer and lower floor's interlayer dielectric layer when layer metal interconnecting layer surface deposition.
Fig. 3 forms the schematic flow sheet of the method for hole between second embodiment of the invention groove.
Fig. 3 a to Fig. 3 g is the concrete generalized section that forms the method for hole between second embodiment of the invention groove.
Fig. 3 h is that second embodiment of the invention is having the cross-sectional view of lower floor's etch stop layer and lower floor's interlayer dielectric layer when layer metal interconnecting layer surface deposition.
Fig. 4 for forming the schematic top plan view after the connecting hole of lower floor in Fig. 2 h or 3h.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention utilizes schematic diagram have been described in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram that represents structure can be disobeyed local amplification of general ratio work, should not using this as limitation of the invention, in addition,, in actual making, should comprise the three-dimensional space of length, width and the degree of depth.
Core concept of the present invention is to add dielectric layer at metallic copper sidewall, has not only increased metallic copper and lower floor's connecting hole to punctual process window, and has increased the mechanical stability of deposition lower floor's etch stop layer and lower floor's interlayer dielectric layer.Further, the present invention has adopted the method that is different from prior art etching groove, but as forming grating, define the CD of the first polymeric layer, and then the first polymeric layer thermal decomposition is fallen to form groove, forming like this groove is simple and easy to realize, the size of the first photoresistance glue-line of exposing is easily controlled, and there is not the process of etching interlayer dielectric layer in the groove forming like this, the problem that can not bring interlayer dielectric layer K value to raise, the dielectric constant of dielectric layer is very low simultaneously, guarantees the problem that can not bring because of the introducing of dielectric layer K value to raise.
The present invention illustrates by two embodiment the method that forms hole between groove.
Between first embodiment of the invention groove, form the method for hole, its schematic flow sheet as shown in Figure 2, comprises the following steps, and below in conjunction with Fig. 2 a to Fig. 2 g, is elaborated.
Step 21, refer to Fig. 2 a, semi-conductive substrate 100 is provided in advance, described Semiconductor substrate 100 surfaces comprise the first etch stop layer 101 and the first polymeric layer 200 from bottom to top successively; On the surface of the first polymeric layer 200, form the first photoresistance glue-line 201 of patterning, the critical size (CD) of 201 overlay area definition grooves of the first photoresistance glue-line of patterning; The the first photoresistance glue-line 201 of patterning of take is mask, and etching the first polymeric layer 200 is to manifesting the first etch stop layer 101;
Because the first polymeric layer 200 is follow-up, need thermal decomposition to fall, so can be the copolymer of butyl norborene and the silica-based norborene of three ethoxies, also can or be the heat decomposable polymer of other class for similar derivative, generally pass through the many of spin-coating method film forming.
Step 22, refer to Fig. 2 b, the first polymeric layer 200 surfaces after the first etch stop layer 101 and etching are dielectric layer 202 and sacrifice layer 203 successively;
The thickness of the dielectric layer depositing is suitably selected according to the difference of the size of device, also can adjust according to the bore hole size between the groove that will form, and when dielectric layer is thicker, bore hole size will be less; When dielectric layer is thinner, bore hole size will be larger.Usually, the thickness of dielectric layer is 20～200 dusts, and dielectric constant is 2～3, can be silicon oxide carbide (SiOC) layer, silicon dioxide (SiO
2) layer or carbonitride of silicium (SiNC) layer etc.Sacrifice layer is also generally Low-K material layer.
Step 23, refer to Fig. 2 c, cmp sacrifice layer 203 and dielectric layer 202 are to manifesting the first polymeric layer 200;
Step 24, refer to Fig. 2 d, thermal decomposition is removed the first polymeric layer 200 and is formed grooves, and removes the first etch stop layer 101 in groove;
Step 25, refer to Fig. 2 e, in groove, fill metallic copper 204;
Step 26, refer to Fig. 2 f, deposition the second etch stop layer 205; On the second etch stop layer surface, form the second photoresistance glue-line 206 of patterning, the corresponding presumptive area sacrifice layer of opening of the second photoresistance glue-line 206 of described patterning;
Wherein, the opening of the second photoresistance glue-line is typically chosen in groove than the region of comparatively dense, and the corresponding presumptive area sacrifice layer of the opening of the second photoresistance glue-line 206 of patterning, referring to the second photoresistance glue-line 206 all covers in other more sparse region of groove, and in presumptive area, be selected groove than in the region of comparatively dense, the dielectric layer 202 of a covering metal copper 204 and metallic copper sidewall, only can etch into sacrifice layer during etching like this.
Step 27, refer to Fig. 2 g, the second photoresistance glue-line of patterning of take is 206 masks, etching the second etch stop layer 205; Remove sacrifice layer, form the hole 209 between groove.
So far, first embodiment of the invention has realized the method that forms hole between groove.
Further, first embodiment of the invention also comprises step 28, refers to Fig. 2 h, deposits successively the interlayer dielectric layer 208 of the etch stop layer 207He lower floor of lower floor.Those skilled in the art can know, on the interlayer dielectric layer of lower floor, can make groove and connecting hole, and connecting hole can be electrically connected with metallic copper 204, does not repeat them here.
In step 21, as forming grating, define the CD of the first polymeric layer, the CD that this CD is groove is then removed formation groove by thermal decomposition in step 24.Exposure imaging forms the CD of first photoresistance glue-line 201 definition the first polymeric layers of patterning, even be also easy to realize for small size device.And compared with prior art, do not exist etching interlayer dielectric layer to form the process of groove, prior art is in the process of etching interlayer dielectric layer, along with exhausting of interlayer dielectric layer, its phosphorus content reduces, cause K value to increase, and the present invention can find out from Fig. 2 h, dielectric layer 202 is positioned at the sidewall of metallic copper, the dielectric layer 202 with low-k has not only increased metallic copper and lower floor's connecting hole to punctual process window, and has increased the mechanical stability of deposition lower floor's etch stop layer and lower floor's interlayer dielectric layer.
Between second embodiment of the invention groove, form the method for hole, its schematic flow sheet as shown in Figure 3, comprises the following steps, and below in conjunction with Fig. 3 a to Fig. 3 g, is elaborated.
Step 31, refer to Fig. 3 a, semi-conductive substrate 100 is provided in advance, described Semiconductor substrate 100 surfaces comprise the first etch stop layer 101 and the first polymeric layer 200 from bottom to top successively; On the surface of the first polymeric layer 200, form the first photoresistance glue-line 201 of patterning, the critical size CD of 201 overlay area definition grooves of the first photoresistance glue-line of patterning; The the first photoresistance glue-line 201 of patterning of take is mask, and etching the first polymeric layer 200 is to manifesting the first etch stop layer 101;
Because the first polymeric layer 200 is follow-up, need thermal decomposition to fall, so can be the copolymer of butyl norborene and the silica-based norborene of three ethoxies, also can or be the heat decomposable polymer of other class for similar derivative, generally pass through the many of spin-coating method film forming.
Step 32, refer to Fig. 3 b, the first polymeric layer 200 surfaces after the first etch stop layer 101 and etching are dielectric layer 202 and the second polymer layer 300 successively;
The thickness of the dielectric layer depositing is suitably selected according to the difference of the size of device, also can adjust according to the bore hole size between the groove that will form, and when dielectric layer is thicker, bore hole size will be less; When dielectric layer is thinner, bore hole size will be larger.Usually, the thickness of dielectric layer is 20～200 dusts, and dielectric constant is 2～3, can be silicon oxide carbide (SiOC) layer, silicon dioxide (SiO
2) layer or carbonitride of silicium (SiNC) layer etc.
The second polymer layer 300 also can for the similar heat decomposable polymer of the first polymeric layer 200 character.
Step 33, refer to Fig. 3 c, cmp the second polymer layer 300 and dielectric layer 202 are to manifesting the first polymeric layer 200;
Step 34, refer to Fig. 3 d, thermal decomposition is removed the first polymeric layer 200 and is formed grooves, and removes the first etch stop layer 101 in groove;
Step 35, refer to Fig. 3 e, in groove, fill metallic copper 204;
Step 36, refer to Fig. 3 f, deposit opercular layer (cap layer) 301;
Step 37, refer to Fig. 3 g, see through and have opercular layer 301 thermal decompositions to remove the second polymer layers 300, form the hole 209 between groove.
Wherein, having opercular layer is the insulation material layer of gas permeability, while guaranteeing thermal decomposition the second polymer layer, can volatilize away.Because the first polymeric layer 200 is taken off prior to the second polymer layer for 300 minutes, thus require the heat decomposition temperature of the second polymer layer 300 higher than the first polymeric layer 200, and higher than 40～50 degrees Celsius.
So far, second embodiment of the invention has realized the method that forms hole between groove.
Further, second embodiment of the invention also comprises step 38, refers to Fig. 3 h, deposits successively the interlayer dielectric layer 208 of the etch stop layer 207He lower floor of lower floor.Those skilled in the art can know, on the interlayer dielectric layer of lower floor, can make groove and connecting hole, and connecting hole can be electrically connected with metallic copper 204, does not repeat them here.
Fig. 4 for forming the schematic top plan view after the connecting hole of lower floor in Fig. 2 h or 3h.As can be seen from Figure 4, method of the present invention goes for small size semiconductor device, even the connecting hole of lower floor 400 with when a layer metallic copper 204, have deviation a little, the connecting hole 400 of lower floor also can contact dielectric layer 202, and not with hole 209 conductings on side, thereby realized object of the present invention.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (9)
1. between groove, form a method for hole, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the first etch stop layer and the first polymeric layer from bottom to top successively; On the surface of the first polymeric layer, form the first photoresistance glue-line of patterning, the critical size CD of the first photoresistance glue-line institute overlay area definition groove of patterning; The the first photoresistance glue-line of patterning of take is mask, and etching the first polymeric layer is to manifesting the first etch stop layer;
The first polymeric layer surface after the first etch stop layer and etching is dielectric layer and sacrifice layer successively;
Cmp sacrifice layer and dielectric layer are to manifesting the first polymeric layer;
Thermal decomposition is removed the first polymeric layer and is formed groove, and removes the first etch stop layer in groove;
In groove, fill metallic copper;
Deposit the second etch stop layer; On the second etch stop layer surface, form the second photoresistance glue-line of patterning, the corresponding presumptive area sacrifice layer of opening of the second photoresistance glue-line of described patterning; Wherein, the corresponding presumptive area sacrifice layer of opening of the second photoresistance glue-line of described patterning is specially: the second photoresistance glue-line all covers in other more sparse region of groove, and selected groove than the presumptive area of comparatively dense in, the dielectric layer of a covering metal copper and metallic copper sidewall;
The the second photoresistance glue-line of patterning of take is mask, etching the second etch stop layer; Remove sacrifice layer, form the hole between groove.
2. the method for claim 1, is characterized in that, described medium thickness 20～200 dusts.
3. method as claimed in claim 2, is characterized in that, the dielectric constant of described dielectric layer is 2～3.
4. method as claimed in claim 3, is characterized in that, described dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2layer or carbonitride of silicium SiNC layer.
5. the method for claim 1, is characterized in that, after forming the hole between groove, the method further comprises and deposits successively the etch stop layer of lower floor and the interlayer dielectric layer of lower floor.
6. between groove, form a method for hole, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the first etch stop layer and the first polymeric layer from bottom to top successively; On the surface of the first polymeric layer, form the first photoresistance glue-line of patterning, the critical size CD of the first photoresistance glue-line institute overlay area definition groove of patterning; The the first photoresistance glue-line of patterning of take is mask, and etching the first polymeric layer is to manifesting the first etch stop layer;
The first polymeric layer surface after the first etch stop layer and etching is dielectric layer and the second polymer layer successively;
Cmp the second polymer layer and dielectric layer are to manifesting the first polymeric layer;
Thermal decomposition is removed the first polymeric layer and is formed groove, and removes the first etch stop layer in groove;
In groove, fill metallic copper;
Deposit opercular layer;
See through and have opercular layer thermal decomposition to remove the second polymer layer, form the hole between groove;
Wherein, the heat decomposition temperature of described the second polymer layer is higher 40～50 degrees Celsius than the heat decomposition temperature of the first polymeric layer.
7. method as claimed in claim 6, is characterized in that, described medium thickness 20～200 dusts.
8. method as claimed in claim 7, is characterized in that, the dielectric constant of described dielectric layer is 2～3.
9. method as claimed in claim 8, is characterized in that, described dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2layer or carbonitride of silicium SiNC layer.
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| CN101241899A (en) * | 2007-01-25 | 2008-08-13 | 三星电子株式会社 | Semiconductor device having thermally formed air gap in wiring layer and method of fabricating same |
| CN101828249A (en) * | 2007-10-18 | 2010-09-08 | 东京毅力科创株式会社 | Method and system for forming an air gap structure |
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| US20080217730A1 (en) * | 2007-03-07 | 2008-09-11 | Toshiharu Furukawa | Methods of forming gas dielectric and related structure |
| DE102009023377B4 (en) * | 2009-05-29 | 2017-12-28 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Method for producing a microstructure component having a metallization structure with self-aligned air gap |
| US8241991B2 (en) * | 2010-03-05 | 2012-08-14 | Asm Japan K.K. | Method for forming interconnect structure having airgap |
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| CN101241899A (en) * | 2007-01-25 | 2008-08-13 | 三星电子株式会社 | Semiconductor device having thermally formed air gap in wiring layer and method of fabricating same |
| CN101828249A (en) * | 2007-10-18 | 2010-09-08 | 东京毅力科创株式会社 | Method and system for forming an air gap structure |
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