KR101146225B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention not only simplifies the manufacturing process and reduces the manufacturing cost in implementing the MIM capacitor and the TFR in one chip, but also when forming the MIM capacitor using copper wiring, the lower electrode and the upper electrode of the capacitor are formed. To provide a method of manufacturing a semiconductor device that can reduce the height step between the contact plugs to connect, for this purpose, in the present invention, a semiconductor substrate defined by the first region in which the M capacitor is to be formed and the second region in which the thin film resistor is to be formed. Forming a first metal layer, a dielectric film, and a second metal layer on the substrate; and etching the second metal layer, the dielectric film, and the first metal layer on the substrate in the first region. Forming the thin film capacitor on the substrate of the second region at the same time It provides a semiconductor device manufacturing method hereinafter.

 MIM, capacitors, TFR, copper wiring.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a semiconductor device in which a MIM capacitor and a TFR are implemented in one chip.

2 is a cross-sectional view illustrating a MIM capacitor formed using copper wiring.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second preferred embodiment of the present invention.

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third preferred embodiment of the present invention.

6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fifth embodiment of the present invention.

Description of the Related Art

M: MIM capacitor area

T: TFR region

200: semiconductor substrate

210, 311, 411, 511, 611: first metal wiring

211, 215, 313, 315, 416, 513: metal layer

212, 314, 415, 512, 615: dielectric film

214, 316, 322, 417, 424, 514, 521, 617, 622: etch stop film

213a, 315a, 416a, 513a, 616: upper electrode of capacitor

213b, 315b, 416b, 513b, 612b: TFR

211a, 313a, 412a, and 612a: lower electrode of the capacitor

217, 320, 421, 518, 620: MIM capacitor

221, 310, 321, 323, 410, 423, 425, 510, 520, 522, 610, 621, 623

222, 324, 426, 523, 624: contact plug

223, 325, 427, 524, 625: second metal wiring

312: diffusion barrier

412: lower electrode layer of the capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) are used to be applicable to analog, mixed signal, system-on-chip applications, and high frequency circuits of wired and wireless communication. It relates to a semiconductor device manufacturing method implemented in one chip.

In general, analog capacitors applied to CMOS IC logic devices that require high precision are advanced analog MOS technology, especially A / D converters (Analog / Digital converter). Or switching capacitor filters. As the structure of the capacitor, various structures such as polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-metal (PIM), metal-insulator-polysilicon (MIP), and metal-insulator-metal (MIM) have been used.

Among them, the capacitor of the MIM structure is used as a representative structure of the analog capacitor because of the advantages of low series resistance, low thermal budget and low power supply voltage (V _CC ). Such MIM capacitors have been widely used in semiconductor companies in radio frequency (RF) / mixed signal (MS) devices and DRAM cells.

Meanwhile, a thin film resistor (TFR) along with such a MIM capacitor is a typical passive device used in an RF device and is widely used because of its advantage of having a very high linearity. Accordingly, in recent years, technology for implementing a MIM capacitor and a TFR on a single chip has been in the spotlight.

1 is a diagram illustrating a semiconductor device in which a MIM capacitor and a TFR are implemented in one chip according to the related art. Referring to FIG. 1, the MIM capacitor 14 and the TFR 20 are implemented on different wires. For example, the TFR 20 is formed on the metal wiring 17 connecting the MIM capacitor 14. Hereinafter, a method of implementing a MIM capacitor and a TFR in one chip according to the related art will be briefly described.

First, the MIM capacitor 14 including the lower electrode 11, the dielectric film 12, and the upper electrode 13 is formed on the first metal wires 10 and M _n , and then the lower electrode 11 and the upper part are formed. A second metal wire 17 (M _{n + 1} ) connecting the electrode 13 is formed. Then, the TFR 20 is formed on the interlayer insulating film 19 covering the second metal wiring 17, and the third metal wirings 24 and M connecting the TFR 20 and the second metal wiring 17 are then formed. _{n + 2} ). In this case, the first to third metal wires 10, 17, and 24 are typically made of aluminum (Al) or copper (Cu).

However, in order to implement the MIM capacitor 14 and the TFR 20 in one chip as shown in FIG. 1, the process of forming the MIM capacitor 14 and the TFR 20 has to be performed separately, respectively. There is a problem of complexity and increased manufacturing cost.

On the other hand, Figure 2 is a cross-sectional view showing a MIM capacitor formed using a copper wiring according to the prior art. Referring to FIG. 2, a method of forming a MIM capacitor using copper wiring will be described.

When using a copper wire, the copper material nature damascene (Damascene) because it requires a process, first, the first metal line by a damascene process (110, M _n) copper wire (113a) and a first contact plug on To form 113b. Then, the MIM capacitor 120 including the lower electrode 115, the dielectric film 116, and the upper electrode 117 is formed on the copper wiring 113a, and the contact plug 113b and the upper electrode 117 are formed. Second metal wires 124 and M _{n + 1} connected to each other are formed. Here, the lower electrode 115 is connected to the second metal wiring 124 through the copper wiring 113a and the first metal wiring 110 connected thereto. Accordingly, the contact plug 113b + 122 for connecting the lower electrode 115 and the second metal wiring 124 to the contact plug 122 for connecting the upper electrode 115 and the second metal wiring 124. More significantly deeper.

As a result, in order to form the MIM capacitor using the copper wiring, the height step between the contact plug connecting the lower electrode and the upper electrode of the capacitor is significantly increased than when using the aluminum wiring. Therefore, in the case of forming the MIM capacitor using the copper wiring, it is difficult to precisely control the etching end point to the upper portion of the upper electrode when forming the contact plug connecting the upper electrode. This causes a problem of damaging the upper electrode to lower the operating characteristics of the semiconductor device.

In FIG. 1, '15' and '22' which are not described are interlayer insulating films, and '16' and '23' are contact plugs. In addition, in FIG. 2, unexplained '111' and '118' are etch stop films, and '112', 1121 'and' 123 'are interlayer insulating films.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device manufacturing method that can simplify the manufacturing process and reduce the manufacturing cost in implementing a MIM capacitor and a TFR in one chip. Its purpose is to.

In addition, the present invention provides a method of manufacturing a semiconductor device that can improve the operation characteristics of the capacitor by reducing the height step between the contact plug connecting the lower electrode and the upper electrode of the capacitor when forming the MIM capacitor using copper wiring. Has a different purpose.

According to an aspect of the present invention, there is provided a semiconductor substrate including a first region in which an M capacitor is to be formed and a second region in which a thin film resistor is to be formed. Forming a first metal layer, a dielectric film, and a second metal layer; etching the second metal layer, the dielectric film, and the first metal layer to form the MI capacitor on the substrate in the first region; It provides a method for manufacturing a semiconductor device comprising the step of forming the thin film resistor on the substrate of two regions.

According to another aspect of the present invention, there is provided a semiconductor substrate including a first region in which an M capacitor is to be formed and a second region in which a thin film resistor is to be formed. Forming a lower electrode of the capacitor on the substrate in a region; depositing a dielectric film and a metal layer along a step of an upper portion of the entire structure including the lower electrode; and etching the metal layer to etch the metal layer in the first region. And forming the thin film resistor on the dielectric film of the second region while forming an upper electrode of the capacitor on the dielectric film.

In addition, according to another aspect of the present invention, there is provided a semiconductor substrate including a first region in which an M capacitor is to be formed and a second region in which a thin film resistor is to be formed. Depositing a first metal layer on the substrate, etching the first metal layer to form a lower electrode of the capacitor on the substrate of the first region, and simultaneously forming the thin film resistor on the substrate of the second region And depositing a dielectric film along a step of an entire structure including the lower electrode and the thin film resistor, and forming an upper electrode of the capacitor on the dielectric film in the first region. Provided is a device manufacturing method.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example 1

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 3A to 3D are the same components that perform the same function.

First, as shown in FIG. 3A, a MIM capacitor region (M; hereinafter referred to as a first region) in which a MIM capacitor is to be formed and a TFR region in which a resistance including a TFR is formed (T; hereinafter referred to as a second region) A semiconductor substrate 200 is defined, and a predetermined semiconductor structure layer (not shown) is provided. Here, the semiconductor structure layer may be a structure layer formed for the operation of the semiconductor device, such as a transistor, another wiring, an insulating layer.

Subsequently, the first metal wire 210 is deposited on the substrate 200. In this case, the first metal wiring 210 is made of aluminum.

Subsequently, a metal layer 211 (hereinafter referred to as a first metal layer), a dielectric layer 212, a metal layer 213 (hereinafter referred to as a second metal layer), and an etch stop layer 214 are formed on the first metal wiring 210. Deposition sequentially. Here, the first metal layer 211 is formed of TiN, the second metal layer 213 is formed of TaN, and the dielectric film 212 and the etch stop film 214 are formed of SiN.

Subsequently, as shown in FIG. 3B, a photoresist (not shown) is coated on the etch stop layer 214, followed by an exposure and development process using a photomask (not shown) to perform the photoresist pattern 215. To form. Thereafter, an etching process 216 using the photoresist pattern 215 as an etching mask is performed to sequentially etch the etch stop layer 214, the second metal layer 213 (see FIG. 3A), and the dielectric layer 212. . As a result, the MIM capacitor 217 including the upper electrode 213a, the dielectric film 212, and the first metal layer 211 is formed in the first region M, and the TFR 213b is formed in the second region.

Subsequently, as shown in FIG. 3C, a strip process is performed to remove the photoresist pattern 215 (see FIG. 3B), and then the photoresist pattern 219 is formed as shown in FIG. 3B.

Next, an etching process 220 using the photoresist pattern 219 as an etching mask is performed to etch the exposed first metal layer 211 (see FIG. 3B) and the first metal wiring 210. As a result, the first metal layer 211 and the first metal wiring 210 are separated for each of the first and second regions M and T. As a result, the first metal layer 211 of the first region M functions as the lower electrode 211a of the MIM capacitor.

Subsequently, as shown in FIG. 3D, a strip process is performed to remove the photoresist pattern 219 (see FIG. 3C), and then an insulating film 221 is deposited on the entire structure. In this case, the insulating film 221 is formed of an oxide film-based material. For example, the insulating film 221 may be a high density plasma (HDP) oxide film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a plasma enhanced tetra thyle ortho silicate (peteos) film, a plasma enhanced chemical vapor deposition (PECVD) ) Film, USG (Un-doped Silicate Glass) film, Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film using any one layer or laminated film To form.

Subsequently, a mask and an etching process are performed to expose a portion of the lower electrode 211a, the upper electrode 213a, and the TFR 213b formed in the second region T of the MIM capacitor formed in the first region M. FIG. Holes (not shown) are formed respectively.

Subsequently, a contact process and a wiring process are performed to form a contact plug 222 in which contact holes are embedded, and to form second metal wirings 223 connected to the contact plug 222, respectively. As a result, the MIM capacitor 217 and the TFR 213b are electrically connected to the second metal wiring 223.

That is, according to the first preferred embodiment of the present invention, by simultaneously implementing the MIM capacitor and the TFR on the same layer, that is, on the first metal wiring, the manufacturing process of the semiconductor device is simplified and the manufacturing cost is reduced. In addition, the quality (Q) of the capacitor is improved by forming a MIM capacitor formed on Mn on Mn + 1 in the aforementioned prior art to further distance the substrate.

Example 2

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 4A to 4D are the same components that perform the same function. At this time, the second preferred embodiment of the present invention is characterized in that the use of copper wiring, unlike the aluminum wiring in the first embodiment.

First, as illustrated in FIG. 4A, a semiconductor substrate defined by a first region M in which a MIM capacitor is to be formed and a second region T in which a TFR is to be formed, and on which a predetermined semiconductor structure layer (not shown) is formed ( Not shown). Here, the semiconductor structure layer may be a structure layer formed for the operation of the semiconductor device, such as a transistor, another wiring, an insulating layer.

Next, a single damascene process is performed to pass through the insulating film 310 through the first metal wiring 311 for each of the first and second regions M and T on the substrate (hereinafter referred to as a first insulating film). Form). Here, the first metal wiring 311 is formed of copper.

Subsequently, the diffusion barrier 312, the metal layer 313 (hereinafter, referred to as a first metal layer), the dielectric film 314, and the metal layer 315 are disposed on the first insulating layer 310 including the first metal wiring 311. The second metal layer) and the etch stop layer 316 are sequentially deposited. At this time, the diffusion barrier 312 is formed of SiN to prevent the diffusion of copper during the thermal process. In addition, both the first and second metal layers 313 and 315 are formed of TaN, and the dielectric and etch stop layers 314 and 316 are formed of SiN.

Subsequently, as shown in FIG. 4B, after the photoresist is not shown on the etch stop layer 316, the photoresist pattern 317 is formed by performing an exposure and development process. Thereafter, an etching process 318 using the photoresist pattern 317 as an etching mask is performed to expose the etch stop layer 316, the second metal layer 315 (see FIG. 4A), the dielectric layer 314, and the first layer. The metal layer 313 (see FIG. 4A) is sequentially etched. As a result, the MIM capacitor 320 including the lower electrode 313a, the dielectric film 314, and the upper electrode 315a is formed on the diffusion barrier 312 of the first region M. The TFR 315b is formed on the diffusion barrier 312.

Subsequently, as shown in FIG. 4C, a strip process is performed to remove the photoresist pattern 317 (see FIG. 4B), and then an insulating film 321 (hereinafter referred to as a second insulating film) is deposited over the entire structure. . In this case, the second insulating film 321 is formed in the same manner as the insulating film 221 of FIG. 3D.

Subsequently, the etch stop film 322 and the insulating film 323 are sequentially deposited on the second insulating film 321. In this case, the etch stop layer 322 is formed of SiN and the insulating layer 323 is formed of an oxide-based material.

Subsequently, as shown in FIG. 4D, a dual damascene process is performed to form the contact plug 324 and the second metal wiring 325. As a result, the lower electrode 313a, the upper electrode 315a, and the TFR 315b formed in the second region T of the MIM capacitor formed in the first region M are electrically connected to the second metal wiring 325, respectively. do.

Since the effect according to the second preferred embodiment of the present invention is the same as the effect according to the first embodiment, a description thereof will be omitted.

Example 3

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 5A to 5E are the same components that perform the same function.

First, as illustrated in FIG. 5A, a semiconductor substrate defined by a first region M in which a MIM capacitor is to be formed and a second region T in which a TFR is to be formed, and on which a predetermined semiconductor structure layer (not shown) is formed ( Not shown). Here, the semiconductor structure layer may be a structure layer formed for the operation of the semiconductor device, such as a transistor, another wiring, an insulating layer.

Subsequently, a single damascene process is performed to form an insulating film 410 (hereinafter referred to as a first insulating film) having a first metal wiring 411 interposed in the first region M on the substrate. do. Here, the first metal wiring 411 is formed of copper.

Subsequently, the lower electrode layer 412 of the capacitor is deposited on the first insulating layer 410 including the first metal wiring 411. In this case, the lower electrode layer 412 is formed of any one of TaN, TaSiN, WN, and WSiN.

Subsequently, as shown in FIG. 5B, a photoresist (not shown) is applied onto the lower electrode layer 412 (see FIG. 5A), and then an exposure and development process using a photomask (not shown) is performed to form a photoresist pattern. 413 is formed. Then, an etching process 414 using the photoresist pattern 413 as an etching mask is performed to form the lower electrode 412a of the capacitor on the first metal wiring 411 of the first region M. Referring to FIG.

Subsequently, as shown in FIG. 5C, a strip process is performed to remove the photoresist pattern 413 (see FIG. 5B), and then the dielectric film 415, the metal layer 416, and the etch stop are formed along the steps of the entire structure. The film 417 is deposited sequentially. In this case, the metal layer 416 is formed of any one of TaN, TaSiN, WN, and WSiN.

Subsequently, as shown in FIG. 5D, the photoresist pattern 419 is formed on the etch stop layer 417 in the same manner as in FIG. 5B, and an etching process 420 using the same as an etching mask is performed to expose the photoresist pattern 419. The etch stop layer 417 and the metal layer 416 (see FIG. 5C) are etched. As a result, the upper electrode 416a of the capacitor is formed on the dielectric film 415 of the first region M, and the TFR 416b is formed on the dielectric film 415 of the second region T. Through this, the MIM capacitor 421 and the TFR 416b may be simultaneously implemented on the same layer.

Subsequently, as shown in FIG. 5E, a strip process is performed to remove the photoresist pattern 419 (see FIG. 5D), and then an insulating film 423 (hereinafter referred to as a second insulating film) is deposited over the entire structure. In this case, the second insulating layer 423 is formed by layering or stacking an oxide-based material.

Subsequently, the etch stop layer 424 and the insulating layer 425 are deposited on the second insulating layer 423, and then a dual damascene process is performed to form the contact plug 426 and the second metal wiring 427. As a result, the lower electrode 412a, the upper electrode 416a and the TFR 416b of the second region T of the MIM capacitor of the first region M are electrically connected to the second metal wiring 427, respectively.

That is, according to the third preferred embodiment of the present invention, when forming the MIM capacitor using the copper wiring, the lower electrode is formed to have a first width on the copper wiring, and the upper electrode having a second width narrower than the first width is formed on the lower electrode. After that, a contact plug is formed to connect each of them. Therefore, it is possible to improve the operation characteristics of the capacitor by reducing the height step between the contact plug connecting the lower electrode and the upper electrode of the capacitor.

Example 4

6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 6A to 6C are the same components that perform the same function.

First, as shown in FIG. 6A, a semiconductor substrate defined by a first region M in which a MIM capacitor is to be formed and a second region T in which a TFR is to be formed, and on which a predetermined semiconductor structure layer (not shown) is formed ( Not shown). Here, the semiconductor structure layer may be a structure layer formed for the operation of the semiconductor device, such as a transistor, another wiring, an insulating layer.

Subsequently, a single damascene process is performed to form an insulating film 510 (hereinafter, referred to as a first insulating film) having a first metal wiring 511 interposed therebetween in the first region M on the substrate. . Here, the first metal wiring 511 is formed of copper and functions as a lower electrode of the MIM capacitor.

Subsequently, the dielectric film 512, the metal layer 513, and the etch stop film 514 are sequentially deposited on the first insulating film 510 including the first metal wiring 511. In this case, the metal layer 513 is formed of any one of TaN, TaSiN, WN, and WSiN.

Subsequently, as shown in FIG. 6B, a photoresist (not shown) is coated on the etch stop layer 514, followed by an exposure and development process using a photomask (not shown) to perform the photoresist pattern 515. To form.

Subsequently, an etching process 516 using the photoresist pattern 515 as an etching mask is performed to etch the etch stop layer 514 and the metal layer 513 (see FIG. 6A). As a result, the upper electrode 513a of the capacitor is formed on the dielectric film 512 of the first region M, and the TFR 513b is formed on the dielectric film 512 of the second region T. Through this, the MIM capacitor 518 and the TFR 513b may be simultaneously implemented on the same layer.

Subsequently, as illustrated in FIG. 6C, a strip process is performed to remove the photoresist pattern 515, and then an insulating film 520 (hereinafter referred to as a second insulating film) is deposited over the entire structure. In this case, the second insulating layer 520 is formed of a single layer or a stack of an oxide-based material.

Subsequently, the etch stop layer 521 and the insulating layer 522 are deposited on the second insulating layer 520, and then a dual damascene process is performed to form the contact plug 523 and the second metal wiring 524. As a result, the lower electrode 511, the upper electrode 513a and the TFR 513b of the second region T of the MIM capacitor of the first region M are electrically connected to the second metal wiring 524, respectively.

Since the effects according to the fourth preferred embodiment of the present invention are the same as in the third embodiment, the description thereof will be omitted.

Example 5

7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fifth embodiment of the present invention. Here, among the reference numerals illustrated in FIGS. 7A to 7C, the same reference numerals are the same components that perform the same function.

First, as illustrated in FIG. 7A, a semiconductor substrate in which a first region M in which a MIM capacitor is to be formed and a second region T in which a TFR is to be formed is defined, and a predetermined semiconductor structure layer (not shown) is formed ( Not shown). Here, the semiconductor structure layer may be a structure layer formed for the operation of the semiconductor device, such as a transistor, another wiring, an insulating layer.

Subsequently, a single damascene process is performed to form an insulating film 610 (hereinafter referred to as a first insulating film) having a first metal wiring 611 therebetween in the first region M on the substrate. . Here, the first metal wiring 611 is formed of copper.

Subsequently, although not shown, a first metal layer is deposited on the first insulating layer 610 including the first metal wiring 611, and then a photoresist is applied on the first metal layer, followed by an exposure and development process using a photomask. Then, the photoresist pattern 613 is formed. In this case, the first metal layer is formed of any one of TaN, TaSiN, WN, and WSiN.

Subsequently, an etching process 614 using the photoresist pattern 613 as an etching mask is performed to etch the first metal layer. As a result, the lower electrode 612a of the capacitor is formed on the first metal wiring 611 of the first region M, and the TFR 612b is formed on the first insulating layer 610 of the second region T. do.

Subsequently, as shown in FIG. 7B, after the strip process is performed to remove the photoresist pattern 613 (see FIG. 7A), the dielectric film 615, the second metal layer 616, and The etch stop layer 615 is sequentially deposited. In this case, the second metal layer 616 is formed of any one of TaN, TaSiN, WN, and WSiN.

Subsequently, after the photoresist pattern 618 is formed on the etch stop layer 615 in the same manner as in FIG. 7A, an etch process 619 using the photoresist pattern 618 as an etch mask is performed to expose the etched layer. The stop layer 617 and the second metal layer 616 are etched. As a result, the MIM capacitor 620 is formed on the first metal wire 611 of the first region M. FIG. Through this, the MIM capacitor 620 and the TFR 612b may be simultaneously implemented on the same layer.

Subsequently, as shown in FIG. 7C, a strip process is performed to remove the photoresist pattern 618 (see FIG. 7B), and then an insulating film 621 (hereinafter referred to as a second insulating film) is deposited over the entire structure. In this case, the second insulating layer 621 is formed of a single layer or a stack of oxide-based material.

Subsequently, the etch stop layer 622 and the insulating layer 623 are deposited on the second insulating layer 621, and then a dual damascene process is performed to form the contact plug 624 and the second metal wiring 625. As a result, the lower electrode 612a, the upper electrode 616, and the TFR 612b of the second region T of the MIM capacitor of the first region M are electrically connected to the second metal wiring 625, respectively.

Since the effects according to the fifth preferred embodiment of the present invention are also the same as in the third embodiment, the description thereof will be omitted.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has various effects as follows.

First, by simultaneously implementing the MIM capacitor and the TFR on the same layer, that is, on the first metal wiring, the manufacturing process of the semiconductor device is simplified and the manufacturing cost is reduced.

Second, the quality (Q) of the capacitor is improved by forming a MIM capacitor formed on Mn on Mn + 1 in the aforementioned prior art to further distance the substrate.

Third, when forming the MIM capacitor using the copper wiring, the lower electrode is formed to have a first width on the copper wiring, and the upper electrode having a second width narrower than the first width is formed on the lower electrode, and then contact plugs respectively connecting them are formed. By forming, the height step between the lower electrode of the capacitor and the contact plug connecting the upper electrode is reduced. Through this, it is possible to improve the operating characteristics of the capacitor.

Claims (14)

Providing a semiconductor substrate defined by a first region where an M capacitor is to be formed and a second region where a thin film resistor is to be formed; Depositing metal wires on the semiconductor substrate; Forming a first metal layer, a dielectric film, and a second metal layer on the metal wiring; Etching the second metal layer and the dielectric layer to form the M capacitor on the substrate in the first region and simultaneously forming the thin film resistor on the substrate in the second region; And And etching the first metal layer and the metal wire to form metal wires separated from each other. delete The method of claim 1, Forming metal wires separated from each other between the substrate and the first metal layer in the first region and between the substrate and the first metal layer in the second region. The method of claim 3, wherein The metal wiring is a semiconductor device manufacturing method formed of aluminum or copper. The method of claim 4, wherein If the metal wiring is aluminum, the first metal layer is formed of TiN, and the second metal layer is formed of TaN. The method of claim 4, wherein And wherein the first and second metal layers are formed of TaN when the metal wiring is copper. Providing a semiconductor substrate defined by a first region where an M capacitor is to be formed and a second region where a thin film resistor is to be formed; Depositing metal wires on the semiconductor substrate; Forming a lower electrode of the capacitor on the metal wiring in the first region; Depositing a dielectric film and a metal layer along a step of an upper portion of the entire structure including the lower electrode; And Etching the metal layer to form an upper electrode of the capacitor on the dielectric film of the first region and simultaneously forming the thin film resistor on the dielectric film of the second region; And the metal wiring of the first region and the metal wiring of the second region are separated from each other. delete The method of claim 7, wherein The metal wiring is formed of copper semiconductor device manufacturing method. The method of claim 7, wherein The lower electrode, the upper electrode and the thin film resistor is formed of any one of TaN, TaSiN, WN and WSiN. Providing a semiconductor substrate defined by a first region where an M capacitor is to be formed and a second region where a thin film resistor is to be formed; Depositing metal wires on the semiconductor substrate; Depositing a first metal layer on the metal wiring; Etching the first metal layer to form a lower electrode of the capacitor on the metal wiring in the first region and simultaneously forming the thin film resistor on the metal wiring in the second region; Depositing a dielectric film along a step of an entire structure including the lower electrode and the thin film resistor; And Forming an upper electrode of the capacitor on the dielectric film in the first region, And wherein the metal wirings of the first region and the metal wirings of the second region are separated from each other. delete The method of claim 11, The metal wiring is formed of copper semiconductor device manufacturing method. The method of claim 11, The lower electrode, the upper electrode and the thin film resistor is formed of any one of TaN, TaSiN, WN and WSiN.

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