JP5309722B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate; an oxygen-containing insulating film disposed above the semiconductor substrate; a concave portion disposed in the insulating film; a first film containing copper manganese alloy disposed on an inner wall of the concave portion; a copper-containing second film disposed above the first film and filled in the concave portion; and a manganese-containing oxide layer disposed between the first film and the second film. Furthermore, a copper interconnection is formed on the structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80 DEG C to 120 DEG C. The invention can restrain the increase of interconnection impedance caused by Mn.

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a multilayer wiring structure and its manufacture.

  In today's semiconductor integrated circuit devices, an enormous number of semiconductor elements are formed on a common substrate, and a multilayer wiring structure is used to interconnect them.

In a multilayer wiring structure, an interlayer insulating film in which a wiring pattern constituting a wiring layer is embedded is laminated.
In such a multilayer wiring structure, the lower wiring layer and the upper wiring layer are connected to each other by a via contact formed in the interlayer insulating film.

  Particularly in recent ultra-miniaturized and ultra-high-speed semiconductor devices, a low dielectric constant film (so-called low-k film) is used as an interlayer insulating film in order to alleviate the problem of signal delay (RC delay) in a multilayer wiring structure. At the same time, a low resistance copper (Cu) pattern is used as a wiring pattern.

  In such a multilayer wiring structure in which the Cu wiring pattern is embedded in the low dielectric constant interlayer insulating film, patterning by dry etching of the Cu layer is difficult, so that a wiring groove or a via hole is previously formed in the interlayer insulating film. The damascene method or dual damascene method is used. In the damascene method or the dual damascene method, the wiring trench or via hole formed in this way is filled with a Cu layer, and then an excessive Cu layer on the interlayer insulating film is removed by chemical mechanical polishing (CMP).

  At that time, if the Cu wiring pattern is in direct contact with the interlayer insulating film, Cu atoms diffuse into the interlayer insulating film, causing problems such as short circuits. Therefore, the side wall surface of the wiring groove or via hole in which the Cu wiring pattern is formed In general, the bottom surface is covered with a conductive diffusion barrier, a so-called barrier metal film, and a Cu layer is deposited on the barrier metal film. As the barrier metal film, refractory metals such as tantalum (Ta), titanium (Ti), and tungsten (W), or conductive nitrides of these refractory metals are generally used.

  On the other hand, in recent 45 nm generation or later ultra-miniaturized / high-speed semiconductor devices, the size of wiring trenches or via holes formed in an interlayer insulating film has been remarkably reduced with miniaturization.

  Along with this, if it is intended to reduce the desired wiring resistance by using such a barrier metal film having a large specific resistance, the thickness of the barrier metal film formed in these fine wiring grooves or via holes can be made. It is necessary to reduce as much as possible.

  On the other hand, the barrier metal film needs to continuously cover the side wall surface and the bottom surface of the wiring groove or via hole.

  In relation to such circumstances, Patent Document 1 directly covers a wiring trench or a via hole formed in an interlayer insulating film with a copper manganese alloy layer (Cu—Mn alloy layer).

  In Patent Document 1, a manganese silicon oxide layer having a thickness of 2 to 3 nm and a composition of MnSixOy is formed at the interface between the Cu-Mn alloy layer and the interlayer insulating film. A technique for forming a diffusion barrier film by a self-forming reaction with Si and oxygen in an insulating film is described.

  However, in this technique, the self-formed layer has a composition of MnSixOy, and the adhesion to the Cu film is insufficient due to the low concentration of the metal element contained in the film, that is, manganese (Mn). A problem is recognized.

  For this reason, Patent Document 2 describes a barrier metal structure in which a Cu—Mn alloy layer and a refractory metal barrier metal film such as Ta or Ti are combined.

  Thus, in the barrier metal structure in which the Cu—Mn alloy layer and the refractory metal barrier metal film such as Ta and Ti are combined, a preferable feature that the oxidation resistance is improved is as follows.

In recent years, for the purpose of avoiding signal delay (RC delay), the use of a porous low dielectric constant film as a low dielectric constant material constituting an interlayer insulating film has been proposed. However, such a porous low dielectric constant material has a low density and has a problem that it is easily damaged by plasma during production. A damaged film is likely to adsorb moisture on its surface or inside.
Therefore, the barrier metal film formed on such a porous low dielectric constant film is easily oxidized under the influence of moisture adsorbed in the porous dielectric film, and has a performance as a diffusion barrier and Cu wiring. Adhesion to layers or via plugs tends to deteriorate.

  However, when the Cu-Mn alloy layer described above is used as a seed layer in such a structure, Mn in the Cu-Mn alloy layer reacts with the oxidized portion of the barrier metal film, and the performance as a diffusion barrier and Cu High adhesion to the wiring layer or via plug can be maintained.

  By the way, when forming the Cu wiring layer by the electrolytic plating method, it is necessary to form the seed layer so that the seed layer continuously covers the side wall surface and the bottom surface of the wiring groove or the via hole. If the seed layer is discontinuous, voids may occur in the wiring or via plug during electrolytic plating. When such a seed layer is formed by a sputtering method, it is sufficient to re-sputter or the like on the side wall surface of the wiring groove or via hole so as to ensure that the formed seed layer continuously covers the side wall surface and bottom surface of the via hole. It is conceivable to form a seed layer with a sufficient thickness. However, in such a method, the overhang of the seed layer formed on the upper part of the wiring trench or the via hole is also increased. When the overhang becomes large, the embedding margin due to subsequent electrolytic plating is remarkably reduced, and voids are likely to occur during the electrolytic plating.

  On the other hand, as a result of miniaturization of the semiconductor device, the width of the wiring groove or the diameter of the via hole is narrowed, and at the same time, it is necessary to make the seed layer thinner. However, as long as the seed layer is formed by a sputtering method, it is extremely difficult to cover the side walls and bottom surfaces of wiring grooves and via holes with a sufficient film thickness, particularly in a semiconductor device that has been miniaturized. Further, when a low-K material having a low elastic modulus is used for the interlayer insulating film, bowing may occur in the cross-sectional shape of the wiring groove or via hole after etching, and the seed layer is continuous especially in the side wall portion of the wiring groove having a large surface area. Even if it is a film | membrane, a film thickness may reduce locally as a result of the fluctuation | variation of a film thickness.

  If the film thickness of the seed layer locally decreases in the side wall portion of the wiring groove in this manner, the seed layer may be dissolved in the thin film portion at the initial stage of the copper wiring forming process by the electrolytic plating method. When the electrolytic plating process is performed using the seed layer partially dissolved as described above, there may be a problem that a void is generated at a location corresponding to the local thin film portion of the seed in the subsequent heat treatment process.

In the generation of voids due to such a minute dissolution of the seed layer, in general, there is no embedding defect immediately after plating, and it is characteristic that voids are generated only after the heat treatment step. This is because, during electrolytic plating, the wiring pattern itself is formed by a bottom-up fill mechanism, so the Cu plating film is apparently formed without voids, but the Cu plating film and barrier metal are formed where the seed layer is dissolved. It is considered that voids are generated at such locations due to insufficient adhesiveness with the film and rapid stress change caused by subsequent heat treatment.
JP 2003-218198 A JP 2007-27259 A JP 2007-141927 A JP 2007-142236 A JP 2007-173511 A US Pat. No. 6,136,707 JP 2007-281485 A JP 2004-111926 A JP 2006-24943 A JP 2000-91271 A JP 2004-153274 A Japanese Patent Laid-Open No. 2005-51185 JP 2001-160590 A

  By the way, in the Cu-Mn alloy layer that forms a barrier metal structure in combination with such a refractory metal barrier metal film, the higher the Mn concentration in the Cu-Mn alloy layer, the more the wiring reliability is improved. To do.

  FIG. 1A shows the result of investigating the stress migration resistance of the test structure shown in FIG. 1B by conducting a heat treatment in the atmosphere at a temperature of 150 to 200 ° C. for 500 hours.

  First, referring to FIG. 1B, a low-k film 12 such as SiOC is formed on a silicon substrate 11. The low-k film 12 such as SiOC is formed with a wiring trench 12T having a width of 65 nm to 10 μm and a depth of about 150 nm. Further, the wiring trench 12T is filled with a Cu wiring pattern 12C via a barrier metal film 12B made of Ta having a thickness of 3 nm to 15 nm covering the side wall surface and the bottom surface.

  Further, on the low-k film 12 such as SiOC, another low-k film 14 such as SiOC has a thickness of 50 to 150 nm via a silicon carbide film (SiC film) 13 having a thickness of 10 to 100 nm. Is formed. On the low-k film 14 such as SiOC, another low-k film 16 such as SiOC is formed to a thickness of 120 to 180 nm via a SiC film 15 having a thickness of 10 to 100 nm.

  In the low-k film 16 such as SiOC, a wiring groove 16T having a width of 65 nm to 10 μm and a depth of 120 to 180 nm penetrates the SiC film 15 so as to expose the low-k film 14 such as SiOC. Is formed. In the wiring trench 16T, a via hole 14V that penetrates the Low-k film 14 such as SiOC and the SiC film 13 and exposes the Cu wiring pattern 12C is formed with a diameter of 70 nm.

  Further, the wiring grooves 12T and 16T are formed by Cu wiring patterns 12C or 16C through barrier metal films 12B or 16B each having a thickness of 3 to 15 nm made of Ta covering the side walls and bottom of the wiring grooves 12T and 16T. Filled. A portion of the Cu wiring pattern 16C that fills the via hole 14V forms a Cu via plug 16V.

  On the silicon substrate 11, a large number of test structures having such a configuration are formed by changing the width W of the wiring pattern 12C or 16C in the above range correspondingly to the regions I and II. ing.

  At that time, in the test structure of FIG. 1B, a Cu—Mn alloy layer 1216M having a thickness of 60 nm is interposed between the barrier metal films 12B and 16B and the Cu wiring patterns 12C and 16C or the Cu via plug 16V. .

  In the test structure of FIG. 1B, the wiring pattern 12C is formed by a damascene method including seed layer formation, electrolytic plating and chemical mechanical polishing (CMP), and the wiring pattern 16C and the via plug 16V include seed layer formation, electrolytic plating and CMP. It is formed by the dual damascene method. The barrier metal films 12B and 16B and the Cu—Mn alloy layers 12M and 16M are formed at a temperature of room temperature or lower by a sputtering method using a Cu—Mn alloy as a target.

  FIG. 1A shows the results of investigating stress migration resistance under the above conditions using the test structure of FIG. 1B.

  Referring to FIG. 1A, a sample described as “PureCu” is a sample in which the Cu—Mn layers 12M and 16M are not formed in the structure of FIG. 1B, and serves as a reference standard. However, in FIG. 1A, the vertical axis represents the number of detected contact failures and is normalized by the reference standard sample.

  In the sample described as “Cu-0.2 at% Mn” in FIG. 1A, a Cu—Mn alloy containing 0.2 atomic% Mn was used as Cu—Mn 12M, 16M in the structure of FIG. 1B. The sample described as “Cu-0.5 at% Mn” uses a Cu—Mn alloy containing 0.5 atomic% of Mn as the Cu—Mn layers 12M and 16M in the structure of FIG. 1B. In the case of using the Cu-Mn alloy containing 2 atomic% Mn as the Cu-Mn layers 12M, 16M in the structure shown in FIG. Indicates.

  As is clear from FIG. 1A, by providing the Cu—Mn alloy layers 12M and 16M, the number of contact failures is reduced to ¼ or less of the case where the contact failure is not provided. In particular, it can be seen that the number of defects can be further reduced by increasing the concentration of Mn in the Cu-Mn alloy layers 12M and 16M.

  However, when the CuMn alloy layers 12M and 16M are formed adjacent to the high melting point barrier metal films 12B and 16B and the Mn concentration in the CuMn alloy layers 12M and 16M is increased as described above, the Cu wiring patterns 12C and 16C are formed. Alternatively, the Cu via plug 16V contains Mn. As a result of the Cu via plug 16V containing Mn, there arises a problem that the resistance value of the Cu wiring patterns 12C, 16C or the Cu via plug 16V increases.

  By the way, in the wiring pattern 12C or 16C of FIG. 1B, in order to form a favorable copper wiring by electrolytic plating, a seed layer (Cu seed layer or CuMn alloy layer 12M or 16M not shown) serving as an electrode at the time of electrolytic plating is provided. It is necessary to have a sufficient film thickness, to form a continuous film, and to have good step coverage. However, as the wiring width W of the wiring groove 12T or 16T becomes narrower, it becomes extremely difficult to form a Cu seed layer or CuMn alloy layer 12M or 16M (not shown) with a sufficient film thickness and good step coverage. In particular, when a Cu seed layer or CuMn alloy layer 12M or 16M (not shown) is formed by sputtering, the wiring width W becomes 90 nm or less. The film thickness locally decreases at the side wall of the wiring groove 12T or 16T, and the film thickness fluctuates.

  When the film thickness of the Cu seed layer or the CuMn alloy layer 12M or 16M is locally reduced in the side surface of the wiring groove 12T or 16T, the copper wiring is formed on the wiring pattern 12C or 16C by subsequent electrolytic plating. Of the Cu seed layer or CuMn alloy layer 12M or 16M that is not formed, a particularly small local thin film portion is dissolved, and in the subsequent heat treatment process, the Cu seed layer or CuMn alloy layer 12M that is not shown in the side surface of the wiring groove 12T or 16T is shown. Or the problem that a void generate | occur | produces in the location applicable to a 16M local thin film part may arise.

  A characteristic feature of the void generation due to the dissolution of a minute portion of the Cu seed layer or CuMn alloy layer 12M or 16M (not shown) is that the wiring pattern 12C or 16C is embedded by a bottom-up fill mechanism during electrolytic plating. As shown in FIG. 1C, apparently there is no embedding defect, and voids appear as shown in FIG. 1D only after heat treatment. This is presumably because the adhesion between the plating film and the barrier metal film 12B or 16B is inadequate at the minute melting point, and abrupt stress change is applied to the portion by heat treatment thereafter.

According to one aspect, a semiconductor device includes a semiconductor substrate, an insulating film containing oxygen formed above the semiconductor substrate, a recess formed in the insulating film, and a barrier containing manganese formed on the inner wall of the recess. A metal film, a first film including copper formed on the barrier metal film, a second film including copper embedded in the concave portion above the first film, and the first film membrane and possess an oxide layer containing manganese between the second film, the manganese concentration of the barrier metal film is higher than the manganese concentration of said first layer.

According to another aspect a method of manufacturing a semiconductor device forming an insulating film comprising the steps of: forming a transistor having a Gate electrode and the source and drain regions on the semiconductor substrate, the oxygen above the semiconductor substrate, Forming a recess in the insulating film; forming a barrier metal film on the inner wall of the recess; forming a metal film containing copper and manganese on the barrier metal film to a predetermined thickness; A step of forming a copper-containing film above the metal film and filling the recess, and a heat treatment is performed after the formation of the copper-containing film to diffuse manganese in the metal film into the barrier metal film. possess a step, the manganese concentration of the barrier metal film after the heat treatment is higher than the manganese concentration of said metal film after the heat treatment.

According to the present invention, the recess formed in the interlayer insulating film containing oxygen is covered with the metal film containing Cu and Mn, and further, the recess is filled with the Cu layer via the metal film and then heat-treated. Thus, Mn in the metal film can be concentrated at the interface with the interlayer insulating film, and an effective diffusion barrier is formed between the Cu layer filling the recess and the interlayer insulating film. Can do.
At this time, in the present invention, by optimizing the film thickness of the metal film, the metal film contains substantially all of Mn in the metal film after heat treatment while using a metal film containing a high concentration of Mn. Therefore, it is possible to reduce the resistivity of the Cu layer filling the concave portion while ensuring the performance as a high barrier film.

  In such a process, Mn atoms bonded to oxygen contained in the atmosphere on the surface of the initially formed metal film are not changed even after other Mn atoms in the metal film are excluded from the metal film. In the form of an oxide layer that is included, it remains at a position corresponding to the original surface of the metal layer, and a structure showing a characteristic concentration of Mn and oxygen in a SIMS profile or the like is obtained.

  Furthermore, according to the present invention, when the recess formed in the interlayer insulating film is filled with the Cu layer through the metal film by electrolytic plating, a relatively low temperature of 80 to 120 ° C. after the electrolytic plating process. By performing the heat treatment at, the stress in the film is relieved, and the problem of generation of voids due to local dissolution of the metal film can be reduced.

[principle]
The inventor of the present invention investigated changes in wiring resistance when the samples described above with reference to FIG. 1B were formed on the silicon substrate 11 with various pattern widths W and heat-treated in the research that is the basis of the present invention. It was.
As shown in FIG. 2, this research has found that an interesting relationship is established in which the rate of increase in wiring resistance decreases as the wiring pattern width W decreases. However, the relationship of FIG. 2 is for the case where the sample of FIG. 1B is heat-treated at 400 ° C. for 30 minutes in a nitrogen atmosphere.

FIG. 3 shows an outline of the sample used in the experiment of FIG.
However, in FIG. 3, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.
In FIG. 3, only a part of the wiring pattern 16 </ b> B and the barrier metal film 16 </ b> B is shown in the portion shown in FIG. 1B in order to avoid the complexity of the drawing.

  3 shows a case where the width W of the Cu wiring pattern 16C is small as shown in the region II.

  In this case, the ratio of the contact area between the Cu wiring pattern 16C and the interlayer insulating film 16 to the total amount of Cu represented by the cross-sectional area of the Cu wiring pattern 16C is the width W of the Cu wiring pattern 16C as shown in the region I. It can be seen that it is larger than the larger case. Therefore, attention is focused on the relationship shown in FIG. 2 in which the rate of increase in wiring resistance decreases as the wiring pattern width W decreases. It is speculated that some chemical reaction occurs in the Cu wiring pattern 16C and the interface region between the via plug 16V and the interlayer insulating film 14 or 15 (not shown in FIG. 3).

  FIG. 4 is a diagram showing the relationship between the film thickness of the Cu—Mn alloy layer 16M and the rate of increase in resistance when the wiring width W is 3 μm in the sample of FIG. 1B. In FIG. 4, however, the film thickness of the Cu—Mn alloy layer 16M is measured on the upper surface of the interlayer insulating film 16, that is, on the flat surface flattened by the CMP method. The resistance increase rate is based on the case where the Cu-Mn alloy layer 16M is not provided (0%). Further, also in the experiment of FIG. 4, the sample of FIG. 1B was heat-treated at a temperature of 400 ° C. for 30 minutes in a nitrogen atmosphere.

  Referring to FIG. 4, the Cu—Mn alloy layer 16 contains 0.5 atomic% of Mn, but as the film thickness of the Cu—Mn alloy layer 16 increases, the resistance increase rate of the Cu wiring pattern 16 </ b> C. It can also be seen that it increases almost linearly. This is because when a Cu-Mn alloy layer 16M having a large film thickness is interposed between the Cu wiring pattern 16C and the barrier metal film 16B, the resistance of the Cu wiring pattern 16C is affected by Mn in the Cu-Mn alloy layer 16M. Indicates an increase.

  However, from the relationship of FIG. 4, when extrapolating in the direction in which the film thickness of the Cu—Mn alloy layer 16M decreases, the film thickness of the Cu—Mn alloy layer 16M becomes less than the critical film thickness of about 15.5 nm. There is. In this case, even if the Cu—Mn alloy layer 16M containing Mn is formed between the Cu wiring pattern 16C or the Cu via plug 16V and the Ta barrier metal film 16B, the resistance increase rate of the Cu wiring layer 16C is zero. It can be seen that there is no increase in resistance. This means that the influence of Mn on the resistance value of the Cu wiring pattern 16C does not appear.

  Therefore, in order to elucidate the meaning of the relationship in FIG. 2 and the relationship in FIG. 4, a scanning transmission electron microscope (STEM) was used for the sample used in the experiment, and an energy dispersive spectrum (EDS) was used. Elemental analysis was performed.

  5A shows a cross-sectional image of the Cu wiring pattern 16C by the STEM, and FIG. 5B shows a characteristic X-ray intensity distribution of Mn obtained by scanning in the depth direction in FIG. 5A. Show.

  Referring to FIG. 5A, “barrier metal” corresponds to the Ta barrier metal film 16B in the sample of FIG. 1B. On top of that, a Cu—Mn alloy layer 16M is initially formed with a thickness of 15.5 nm so as to be sandwiched between the Cu wiring pattern 16C. It was found that the Cu—Mn alloy layer 16M was assimilated with the Cu wiring pattern 16C by heat treatment at a temperature of 400 ° C. for 30 minutes in the nitrogen atmosphere. Further, as can be seen from the EDS profile of FIG. 5B, it was found that the Mn concentration in the barrier metal film 16B greatly increased.

  As a result of the heat treatment at 400 ° C. for the structure of FIG. 1B, substantially all of the Mn atoms in the Cu—Mn alloy layer 16M move to the barrier metal film 16B, and the Cu—Mn alloy layer 16M This means that the Cu layer is substantially free of Mn. This is also true when the film thickness of the Cu-Mn alloy layer 16M on a flat surface is up to about 15.5 nm when the Mn concentration in the Cu-Mn alloy layer 16M is 0.5 atomic%. This means that Mn atoms in substantially all the film can be moved to the Ta barrier metal film 16B by the heat treatment. As a result, the Mn concentration in the Cu wiring pattern 16C can be lowered to a concentration that does not affect the wiring resistance.

  Thus, the Mn atoms that have moved to the barrier metal film 16B are dissolved in the barrier metal film 16B. However, some of the Mn atoms react with oxygen from the interlayer insulating film 14 or 16 containing oxygen existing adjacent to the barrier metal film 16B to form Mn oxide. This Mn oxide is deposited inside the barrier metal film 16B, at the interface between the barrier metal film 16B and the Cu wiring pattern 16C, or at the interface between the barrier metal film 16B and the interlayer insulating film 14 or 16, and stably. Retained. Also, the etching stopper films 23 and 25 made of SiC actually contain a large amount of oxygen, and such a stable formation of Mn oxide is performed between the barrier metal film 16B and the etching stopper films 23 and 25. It is thought to occur also at the interface.

  The results of FIGS. 4 and 5 are for the case where the Cu—Mn alloy layer 16M contains 0.5 atomic% of Mn and the thickness of the Cu—Mn alloy layer 16M is 15 nm. However, the film thickness of the Cu—Mn alloy layer 16M that can move Mn atoms in substantially all the films to the barrier metal film 16B, that is, the critical film thickness is the Cu—Mn alloy layer. It is thought to be related to the Mn concentration in 16M.

  For this reason, the inventor of the present invention uses Cu-Mn alloy layers having various Mn concentrations as the Cu-Mn alloy layer 16M in the sample having the structure shown in FIG. The resistance increase rate was measured.

  FIG. 6 shows the measurement results of the resistance increase rate for such a Cu wiring pattern 16C having a width W of 3 μm. However, in FIG. 6, the vertical axis represents the rate of increase in resistance relative to the case where the Cu—Mn alloy layer 16M is not provided, and the horizontal axis represents the film thickness of the Cu—Mn alloy layer 16M multiplied by the Mn concentration in the film. This amount corresponds to the total amount of Mn atoms in the Cu—Mn alloy layer 16M.

  Referring to FIG. 6, the rate of increase in resistance of the Cu wiring pattern 16C increases substantially linearly with the total amount of Mn atoms in the Cu—Mn alloy layer 16M. It is considered that the total amount of Mn atoms at the resistance increase rate of zero is a critical amount of Mn that can move into the barrier metal film 16B at the Mn concentration. When the amount of Mn in the Cu—Mn alloy layer 16M exceeds this critical amount of Mn (hereinafter referred to as “consumed Mn amount”), the Cu—Mn alloy layer is formed on the barrier metal film 16B even after heat treatment. 16M remains, causing an increase in resistance of the Cu wiring pattern 16C.

  FIG. 7 shows the relationship between the consumed Mn amount represented by the horizontal axis intercept in FIG. 6 and the Mn concentration in the Cu—Mn alloy layer 16M.

  Referring to FIG. 7, the slope between the consumed Mn amount (y axis) and the Mn concentration (x axis) in the Cu—Mn alloy layer 16M is 15.489, and the equation y = 15.489x. It can be seen that the proportional relationship expressed is established. It should be noted that the slope of this FIG. 7 has a thickness dimension (nm).

That is, the relational expression y = 15.489x in FIG. 7 increases in proportion to the Mn concentration x in the film when the consumed Mn amount is the Cu—Mn alloy layer 16M having a thickness of 15.489 nm.
Further, if the film thickness on the flat surface of the Cu-Mn alloy layer 16M is set to 15.489 nm or less, Mn atoms in substantially all the films are removed by heat treatment at any Mn concentration. This means that it can be moved to the Ta barrier metal film 16B. This thickness of 15.489 nm corresponds to the critical film thickness of the Cu—Mn alloy layer 16M of about 15.5 nm, which was previously estimated from the relationship of FIG.

FIG. 8 shows the relationship of Mn consumption when Ta barrier and Ti barrier are used.
As shown in this figure, the existence of critical Mn consumption as shown in FIG. 6 is observed not only when a Ta film is used as the barrier metal film 16B but also when a Ti film is used. Yes.
As shown in the figure, the difference in Mn consumption is within the experimental error range indicated by the arrow near the horizontal axis intercept and is very close. This is because the amount of oxygen generated from the interlayer insulating film does not depend on the type of barrier metal formed on the interlayer insulating film. Therefore, it was found that the above conclusion is not limited to the Ta barrier film.

  In FIG. 8, ♦ indicates an example in which a Ta barrier metal film is used as the barrier metal film 16B already shown in FIG. 6, and the Mn concentration in the Cu—Mn alloy layer 16M is 0.5 atomic%. Show. On the other hand, a black square indicates an example in which a Ti barrier metal film is used as the barrier metal film 16B. Also in this case, the Mn concentration in the Cu—Mn alloy layer 16M is set to 0.5 atomic%.

  Referring to FIG. 8, even when a Ti film is used as the barrier metal film 16B, the rate of increase in resistance of the Cu wiring pattern decreases as the amount of Mn in the Cu-Mn alloy film 16M decreases. However, it can be seen that the presence of Mn does not appear in the resistance increase in the range of Mn amount from 0 to about 7 at% · nm.

  Next, the Mn concentration range to which the relationship of FIG. 7 can be applied will be examined using the phase equilibrium diagram of the Cu—Mn binary system shown in FIG.

  Referring to FIG. 9, it can be seen that in the temperature range of 400 °, the Cu—Mn alloy can take a single phase in the composition range where the Mn concentration in the Cu—Mn alloy is up to 30 atomic%. However, when the Mn concentration in the Cu—Mn alloy increases to 30 atomic% or more, Mn begins to precipitate and a two-phase state of Cu—Mn alloy phase and Mn appears.

  For this reason, as shown in FIG. 10A, the relationship in which the Mn consumption in FIG. 7 increases with the Mn concentration in the Cu—Mn alloy layer 16M is effective because the Mn concentration in the Cu—Mn alloy layer 16M is effective. It is a concentration range until the maximum value of about 30 atomic% and Mn consumption reaches 465 at% · nm, and beyond that, the value of Mn consumption becomes constant at the maximum value of 465 at% · nm.

Therefore, as shown in FIG. 10B , the maximum film thickness y on the flat surface of the Cu—Mn alloy layer 16M that does not increase the resistance of the Cu wiring pattern 16C is the Mn concentration in the Cu—Mn alloy layer 16M. When x is in the range up to about 30 atomic%, it is 15.489 nm, or about 15 nm. When the Mn concentration in the Cu—Mn alloy layer 16M exceeds the concentration of about 30 atomic%, hyperbolically, y = Follow the 465 / x relationship. In other words, it decreases according to a relationship (x × y = 465) that maintains 465 at% · nm as the total amount (x × y) of Mn in the Cu—Mn alloy layer 16M.

  From this, the recesses formed in the interlayer insulating film or insulating films 12, 14 to 16 as shown in FIG. 1B are formed into the refractory metal barrier metal films 12B and 16B and the Cu-Mn alloy layer 12M thereon. In a damascene or dual damascene Cu wiring pattern filled with Cu wiring patterns 12C and 16C through 16M, the Mn concentration in the Cu-Mn alloy layer 12M or 16M is 30 atomic% or less, for example, FIG. , 7, the film thickness on the flat surface of the Cu-Mn alloy layer 12M or 16M is 15.489 nm or about 15 nm or less, for example, 1 nm. To 15 nm, by setting M in the Cu-Mn alloy layer 12M or 16M. Atomic substantially all, it can be seen that it is possible to move each of the refractory metal barrier layer 12B or 16B. As a result, the Mn atom concentration in the Cu-Mn alloy layer 12M or 16M is lowered to a concentration that does not affect the resistance of Cu, and an increase in resistance of the Cu wiring patterns 12C and 16C is avoided.

  Further, even when the Mn atom concentration x in the Cu-Mn alloy layer 12M or 16M exceeds about 30 atomic%, the Cu-Mn alloy layer 12M or 16M on the flat surface expressed in nm unit. By setting the film thickness y to be equal to or less than the film thickness given by the relationship y ≦ 465 / x, substantially all of the Mn atoms in the Cu—Mn alloy layer 12M or 16M are made of the refractory metal barrier film 12B or It becomes possible to move to 16B, respectively, and an increase in resistance of the Cu wiring pattern 12C or 16C is avoided. For example, when the Cu—Mn alloy layer 16M contains 50 atomic% of Mn, the Cu—Mn alloy layer 16M is formed so that the film thickness measured on a flat surface is 9.3 nm or less. Good. When the Cu—Mn alloy layer 16M contains 80 atomic% of Mn, the Cu—Mn alloy layer 16M is formed so that the film thickness measured on a flat surface is 5.8 nm or less. Good. When the Cu—Mn alloy layer 16M contains 100 atomic% of Mn, the Cu—Mn alloy layer 16M is formed so that the film thickness measured on a flat surface is 4.7 nm or less. Good. That is, when the Cu—Mn alloy layer 16M is formed to a thickness of 4.7 nm or less, the Mn concentration in the Cu—Mn alloy layer 16M is set to an arbitrary value of 0 atomic% to 100 atomic%. The concentration can be set.

  6 to 8 are for the Cu wiring pattern 16C having a width W of 3 μm, it is clear that the above results can be applied to wiring patterns having other wiring widths or via plug diameters. It is.

  Further, the barrier metal films 12B and 16B are not limited to the Ta film as described above, but are metal films containing at least one of refractory metal elements such as Ta and Ti, and Zr and Ru. There may be.

  Furthermore, the heat treatment step is not limited to heat treatment at 400 ° C. in a nitrogen atmosphere, and can be performed by heat treatment at a temperature in the range of 100 ° C. to 400 ° C. in an inert atmosphere such as nitrogen or Ar. .

FIG. 11 shows a structure obtained by forming a Cu—Mn alloy layer 16M having a Mn concentration in the range of 0.2 atomic% to 30 atomic% with a film thickness of 15 nm in the structure of FIG. 1B. The structure typically obtained when heat-treated at 400 ° C. in a nitrogen atmosphere is shown.
However, in FIG. 11, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  Referring to FIG. 11, as for the Cu—Mn alloy layers 12M and 16M, as a result of the heat treatment, substantially all of the Mn atoms in the Cu—Mn alloy layers 12M and 16M are Ta barrier metal films 12B and 16B. Respectively, and the Mn concentration does not affect the resistance. The region where the Cu-Mn alloy layer 16M was initially formed is replaced by Cu films 12c1 and 16c1 continuous to the Cu wiring patterns 12C and 16C as a result of such desorption of Mn.

  However, as shown in FIG. 11, the oxide layers 12Ox and 16Ox formed by combining oxygen atoms with Mn atoms remain thinly on the portions that were originally the surfaces of the Cu-Mn alloy layers 12M and 16M. . The Cu wiring patterns 12C and 16C are divided into the regions 12c1 and 16c1 where the original Cu-Mn alloy layers 12M and 16M existed and the regions 12c2 and 16c2 where the original Cu wiring patterns 12C and 16C existed. Divided.

  FIG. 12 is a secondary ion mass spectroscopy (SIMS) profile showing the distribution of Cu, Mn, and oxygen atoms. In this figure, the region including the region where the Cu—Mn layer 12M originally exists in the Cu wiring pattern 12C of FIG. 11 after the heat treatment is obtained.

Referring to FIG. 12, a strong concentration of oxygen concentration reaching 10 ²⁰ / cm ³ was observed in the portion that was originally the surface of the Cu—Mn layer 12M, and with the concentration of oxygen, Mn was concentrated at the same position. You can see that there is concentration.

  FIG. 13A shows the structure of FIG. 1B in which a Cu-Mn alloy layer 12M is further formed in the wiring trench 12T after the formation of the Ta barrier metal film 12B. The state conveyed to the film-forming chamber of Cu film | membrane through the chamber is shown.

  FIG. 13B shows the structure of FIG. 1B, in which a Cu-Mn alloy layer 16M is further formed in the wiring trench 16T and the via hole 14V after the formation of the Ta barrier metal film 16B. The state which conveyed to the film-forming chamber of Cu film | membrane through the vacuum conveyance chamber of this is shown.

  Referring to FIGS. 13A and 13B, the vacuum transfer chamber of the single-wafer substrate processing apparatus cannot completely exclude oxygen even in a vacuum state, and actually a considerable concentration of oxygen is in the vacuum atmosphere. Is usually included. For this reason, oxygen in the atmosphere is adsorbed on the surfaces of the Cu—Mn alloy layers 12M and 16M, and reacts with Mn atoms in the Cu—Mn alloy layers 12M and 16M, respectively. As a result, the Mn oxide layers 12Ox and 16Ox are formed thin on the surface by being separated from the surfaces of the barrier metal films 12B and 16B by a distance corresponding to the film thickness of the Cu-Mn alloy layer. become. Such Mn oxide layers 12Ox and 16Ox remain in their original positions as shown in FIG. 12, even if the recesses in FIGS. 13A and 13B are filled with Cu wiring patterns 12C and 16C, respectively, and then heat-treated.

  That is, as shown in FIG. 11, in the Cu wiring patterns 12C and 16C, the presence of the thin Mn oxide layers 12Ox and 16Ox at positions separated from the surfaces of the barrier metal films 12B and 16B, respectively, In this example, Cu-Mn alloy layers 12M and 16M are formed on 16B, and Mn atoms in the Cu-Mn alloy layers 12M and 16M are moved to the barrier metal films 12B and 16B, respectively. Become.

  In the above experiment, as the barrier metal films 12B and 16B, a Ta film is formed with a thickness of about 6 nm. However, when the thickness of the barrier metal films 12B and 16B is at least 3 nm to 15 nm, Removal of Mn atoms from the Cu—Mn alloy layers 12M and 16M to the barrier metal films 12B and 16B by the above mechanism works effectively.

  FIG. 14 is a diagram showing the result (“present invention” in the figure) of the sample having the structure of FIG. 11 superimposed on the graph of FIG. 1A. However, in FIG. 14, the sample of the “present invention” is for the case where the Cu—Mn alloy layers 12M and 16M contain 2 atomic% of Mn.

  Referring to FIG. 14, it can be seen that the configuration of FIG. 11 can effectively suppress disconnection due to stress migration.

  FIG. 15 is a graph showing a change in stress with respect to heat treatment time when a copper plating film formed by an electrolytic plating method is subjected to heat treatment at temperatures of 150 ° C., 120 ° C., 100 ° C., and 80 ° C. However, in FIG. 15, the change in stress is obtained by measuring the warpage of the wafer at room temperature.

  Referring to FIG. 15, it can be seen that the stress change occurs in the copper plating film by the heat treatment, but the stress change decreases with time, and the film is stabilized. This is considered due to the growth of Cu crystal grains in the copper plating film. From the relationship of FIG. 15, in order to achieve stability of the crystal grains by stress relaxation, at least the heat treatment temperature is required to be 80 ° C. or higher, particularly, the processing time of 120 ° C. or higher is 60 seconds or longer, more preferably 90 seconds. I know that there is. From the viewpoint of manufacturing throughput of the semiconductor device, it is desirable to complete the process in a shorter time. However, in the case where the heat treatment is performed at a temperature of 100 ° C. or higher, it is understood that a heat treatment time of 250 seconds is sufficient. On the other hand, if the temperature is lower than 80 ° C., the desired film cannot be stabilized within a realistic time.

  FIG. 16 shows a case where the Cu—Mn alloy layers 12M and 16M contain Mn at an arbitrary concentration in the sample of FIG. 1B, after the wiring patterns 12C and 16C are filled with the Cu layer by electrolytic plating, The wiring pattern 12C obtained by heat treatment at a temperature of 25 ° C. and 25 ° C. (actually no heat treatment is performed in the experiment of “25 ° C.”) and the excess Cu layer is removed by the CMP method is shown in FIG. It is a figure which shows the result of investigating the number of defects after the CMP process similar to that shown, and further examining the number of defects due to stress migration for the test structure shown in FIG. 1B.

  It can be seen from FIG. 16 that the number of defects after the CMP process can be reduced as the heat treatment temperature is lowered. For example, when the heat treatment temperature is 100 ° C., it is possible to reduce defects of 30% or more when the heat treatment temperature is 150 ° C., and 20% or more when the heat treatment temperature is 120 ° C.

  On the other hand, with respect to stress migration resistance, although a large difference is not observed between samples subjected to heat treatment at 150 ° C. and 100 ° C., a slight improvement is observed near 100 ° C. on the low temperature side. It can also be seen that the stress migration resistance is significantly degraded only when no heat treatment is performed.

Above, from the results of FIG. 16, in a sample of FIG. 1B, when Cu-Mn alloy layer 12M, 16M includes a Mn of any density, wiring patterns 12C, the 16C, after filling in the Cu layer by electrolytic plating, 100 by carrying out heat treatment at a temperature range of ~ 0.99 ° C., defects resistance to stress migration was slightly improved, also due to local dissolution of the seed layer by performing heat treatment at a temperature range of 100 to 120 ° C. 0.99 It was shown that the temperature can be reduced by 20% to 30% compared to the case of ° C.

Referring to FIG. 17A, a wiring groove 22T corresponding to a predetermined wiring pattern is formed in an insulating film 22 formed on a semiconductor substrate 21 on which a transistor and a tungsten plug (not shown) are formed.
Furthermore, a barrier metal film 22B containing at least one refractory metal element such as Ta, Ti, Zr, or Ru is formed on the insulating film 22 so as to cover the side wall surface and the bottom surface of the wiring groove 22T. By an (atomic layer deposition) method or the like, a film having a thickness of 1 to 15 nm is formed in a shape matching the cross-sectional shape of the wiring groove 22T. The barrier metal film 22B is not limited to a metal film, but other than a metal film containing one or more metal elements selected from Ta, Ti, Zr, Ru, such as TaN and TiN, conductive metal nitridation. It may be a membrane.

Next, as shown in FIG. 17B, a Cu—Mn alloy film 22M containing Mn is formed on the barrier metal film 22B shown in FIG. 17A so as to match the cross-sectional shape of the wiring groove 22T. It is formed by applying a plasma power of 10 kW at a substrate temperature of room temperature or lower in an Ar atmosphere of 10 ⁻¹ Pa by a sputtering method using a Mn alloy target. At that time, when the Mn concentration in the Cu—Mn alloy film 22M is about 30 atomic% or less, for example, between 0.2 atomic% and 30 atomic%, the Cu—Mn alloy film 22M has a flat surface. It is formed so as to have a film thickness of about 15 nm or less, for example, in the range of 1 to 15 nm. On the other hand, when the Mn concentration in the Cu—Mn alloy film 22M exceeds 30 atomic%, the Cu—Mn alloy film 22M has a film thickness on a flat surface of x in the Cu—Mn alloy film 22M. It is formed so that the film thickness is less than or equal to the film thickness y given by the equation y = 465 / x.

  Next, as shown in FIG. 17C, a Cu film 22C1 is formed on the structure of FIG. 17B as a plating seed layer, for example, by a sputtering method or a CVD method so as to match the cross-sectional shape of the wiring groove 22T. It is formed in a film thickness.

  Next, as shown in FIG. 17D, a Cu layer 22C2 is formed on the structure of FIG. 17C using the Cu film 22C1 as a plating seed layer so as to fill the wiring trench 22T. Further, as shown in FIG. 17E, the structure of FIG. 17D is polished by CMP until the surface of the insulating film 22 is exposed, and a structure in which the wiring trench 22T is filled with the Cu wiring pattern 22C is obtained.

  Further, on the structure of FIG. 17E, as shown in FIG. 17F, an etching stopper film 23 made of SiC is formed to a thickness of 10 to 100 nm so as to cover the Cu wiring pattern 22C. The film formation of the etching stopper film 23 is typically performed at a temperature of 400 ° C. As a result, the Cu film 22C1 and the Cu film 22C2 constituting the Cu wiring pattern 22C are fused to form a single film. A Cu film is formed. Further, Mn atoms in the Cu-Mn alloy layer 22M move into the barrier metal film 22B by the thermal heat treatment at that time. Accordingly, the original Cu—Mn alloy layer 22M disappears in the Cu wiring pattern 22C, but a thin layer of Mn oxide is formed at a position corresponding to the surface of the original Cu—Mn alloy layer 22M. As indicated by a broken line 22Ox in 17F, the barrier metal film 22B is formed away from the surface by a distance corresponding to the initial film thickness of the Cu—Mn alloy layer 22M. As a result, the Cu wiring pattern 22C includes a region 22c1 where the original Cu-Mn alloy layer 22M was present and a region 22c2 where the original Cu layers 22C1 and 22C2 were present.

Next, as shown in FIG. 17G, an interlayer insulating film 24 having a thickness of 100 to 300 nm, an etching stopper film 25 made of SiC or SiN film having a thickness of 10 to 100 nm, and a thickness on the structure of FIG. 17F. Are sequentially formed by, for example, a plasma CVD method. Further, a wiring groove 26T exposing the etching stopper film 25 is formed in the interlayer insulating film 26 with a desired width by a dry etching process.
As the interlayer insulating films 24 and 26, a silicon oxide film formed by the plasma CVD method using TEOS described above as a raw material, or formed by a plasma CVD method or a coating method, and having a relative dielectric constant of 3 or less. It may be an organic or inorganic insulating film. For example, even when organic polymer films of the registered trade name SiLK are used as the interlayer insulating films 24 and 26, these films contain a substantial amount of oxygen (moisture) due to damage caused by etching or the like. .

  Next, as shown in FIG. 17H, an opening 25V corresponding to a predetermined via hole is formed in the etching stopper film 25 exposed in the wiring trench 26T. Further, as shown in FIG. 17I, using the etching stopper film 25 as a hard mask, a via hole 24V is formed in the interlayer insulating film 24 so that the etching stopper film 23 is exposed.

  Further, as shown in FIG. 17J, the etching stopper film 23 is removed at the bottom of the via hole 24V to expose the Cu wiring pattern 22C. Thereafter, as shown in FIG. 17K, a barrier made of Ta or Ti is formed on the interlayer insulating film 26 so as to continuously cover the sidewall surface and bottom surface of the wiring groove 26T and the sidewall surface and bottom surface of the via hole 24V. The metal film 26B is formed to a thickness of about 1 to 15 nm by a sputtering method or an ALD method in a shape that matches the cross-sectional shape of the wiring groove 26T and the via hole 24V. The barrier metal film 26B is not limited to a metal film, but other than a metal film containing one or more metal elements selected from Ta, Ti, Zr, and Ru, such as TaN and TiN, a conductive metal nitride. It may be a membrane.

  Next, as shown in FIG. 17L, on the structure of FIG. 17K, the Cu—Mn alloy layer 26M covers the barrier metal film 26B with a shape that matches the cross-sectional shape of the wiring groove 26T and the via hole 26V. A film thickness of about 1 to 15 nm is formed by sputtering.

  Further, as shown in FIG. 17M, on the structure of FIG. 17L, a sputtering method is used in a shape matching the cross-sectional shape of the wiring groove 26T and the via hole 24V so that the Cu layer 26C1 covers the Cu—Mn alloy layer 26M. Or it forms in the film thickness of 25-65 nm by CVD method. On the structure of FIG. 17M, as shown in FIG. 17N, a Cu layer 26C2 is formed so as to fill the wiring trench 26T and the via hole 24V by electrolytic plating using the Cu layer 26C1 as a plating seed layer. .

  Further, as shown in FIG. 17O, the Cu layers 26C1, 26C2, the Cu—Mn alloy layer, and the barrier metal film 26B on the interlayer insulating film 26 are polished and polished by CMP until the surface of the interlayer insulating film 26 is exposed. Removed. As shown in FIG. 17P, a cap layer 27 made of a SiN film or a SiC film is formed on the structure of FIG. 17O by a plasma CVD method typically performed at a substrate temperature of 400.degree.

  Due to the heat associated with the formation of the cap layer 27, the Cu layer 26C1 and the Cu layer 26C2 are fused in the wiring groove 26T and the via hole 24V, and extend continuously from the single Cu wiring pattern 26C. A Cu via plug 26V is formed.

  Also, Mn atoms in the Cu-Mn alloy layer 26M move to the barrier metal film 26B due to heat accompanying the formation of the cap layer 27, and the interlayer insulating films 24 and 26 and the etching stopper film 23, 25, oxygen in the form of Mn oxide in the barrier metal film 26B, or at the interface between the barrier metal film 26B and the Cu wiring pattern 26C or the Cu via plug 26V, or between the barrier metal film 26B and the interlayer insulating film 24. Alternatively, it is stably deposited at the interface of 26 or at the interface between the barrier metal film 26B and the etching stopper film 23 or 25.

  Further, when there is a defect in the barrier metal film 26B, the defect is self-repaired by the Mn oxide thus deposited.

Further, as Mn atoms in the Cu-Mn metal layer 26M move to the barrier metal film 26B in this way, the positions corresponding to the original surface of the Cu-Mn metal layer 26M are described above. The Mn oxide layer 26Ox corresponding to the oxide layer formed on the surface of the Cu-Mn metal layer 26M in the step of FIG. 17L is formed from the surface of the barrier metal film 26B to the initial film thickness of the Cu-Mn alloy layer 26M. Are spaced apart by a distance corresponding to.
As a result, as shown in FIG. 17P, the Cu wiring pattern 26C includes the Cu layer formed in the region 26c1 where the original Cu-Mn alloy layer 26M was present, and the original Cu layers 26C1 and 26C2. And a Cu layer formed in the region 26c2.

  By repeating such steps on a semiconductor substrate such as a silicon substrate on which a transistor and a tungsten plug are formed, the present invention makes it possible to manufacture the semiconductor device 40 shown in FIG.

  Referring to FIG. 18, an element region 41A is defined on a silicon substrate 41 by an element isolation structure 41I. In the element region 41A, gate insulating films 42A, 42B, and 42C are formed on the silicon substrate 41, respectively. Gate electrodes 43A, 43B, and 43C are formed through the.

  In the element region 41A, p-type or n-type diffusion regions 41a, 41b, 41c are formed in the silicon substrate 41 adjacent to the gate electrodes 43A, 43B, 43C.

  The gate electrodes 43A, 43B, 43C are covered with insulating films 44A, 44B, 44C such as SiON, respectively. Further, an insulating film 44 made of a silicon oxide film or the like is formed on the silicon substrate 41 so as to cover the gate electrodes 43A to 43C through the insulating films 44A to 44C, respectively. The insulating film 44 is formed with a via hole V1 that exposes the diffusion region 41b and a via hole 44V2 that exposes the diffusion region 41c. The sidewall surfaces and bottom surfaces of these via holes 44V1 and 44V2 are continuously covered with a barrier metal film 46B1 made of TiN, for example, and the via holes V1 and V2 are filled with tungsten 46V1 and 64V2, respectively.

  On the insulating film 44, an interlayer insulating film 46 made of an inorganic or organic insulating film including a porous film is formed via an etching stopper film 45 made of SiN or SiC. In the interlayer insulating film 46, wiring grooves 46T1 and 46T2 are formed along a predetermined wiring pattern.

  The side wall surface and the bottom surface of the wiring trench 46T1 are continuously covered with a barrier metal film 46B1 containing at least one refractory metal element such as Ta, Ti, Zr, or Ru. The wiring trench 46T1 is filled with a Cu wiring pattern 46C1 through the barrier metal film 46B1.

  Similarly, the side wall surface and the bottom surface of the wiring trench 46T2 are continuously covered with a barrier metal film 46B2 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. The wiring trench 46T2 is filled with a Cu wiring pattern 46C2 through the barrier metal film 46B2.

  On the interlayer insulating film 46, an interlayer insulating film 48 made of an inorganic or organic insulating film including a porous film is formed via an etching stopper film 47 made of SiN or SiC. On the interlayer insulating film 48, an interlayer insulating film 50 made of an inorganic or organic insulating film including a porous film is formed via an etching stopper film 49 made of SiN or SiC.

  In the interlayer insulating film 50, wiring trenches 50T1, 50T2, and 50T3 are formed along a predetermined wiring pattern. Further, a via hole 48V1 is formed in the insulating film 48 so as to penetrate the etching stopper film 49 and expose the Cu wiring pattern 46C1 corresponding to the wiring groove 50T1. Further, a via hole 48V2 is formed in the insulating film 48 so as to penetrate the etching stopper film 49 and expose the Cu wiring pattern 46C1 corresponding to the wiring groove 50T2. A via hole 48V3 is formed in the insulating film 48 so as to penetrate the etching stopper film 49 and expose the Cu wiring pattern 46C2 corresponding to the wiring groove 50T3.

  The side walls and bottom of the wiring trench 50T1 and the via hole 48V1 are continuously covered with a barrier metal film 50B1 that contains at least one refractory metal element such as Ta, Ti, Zr, or Ru. The wiring trench 50T1 and the via hole 48V1 are filled with a Cu wiring pattern 50C1 and a Cu via plug 50V1 continuous therewith via the barrier metal film 50B1.

  Similarly, the side wall surface and bottom surface of the wiring trench 50T2 and the via hole 48V2 are continuously covered with a barrier metal film 50B2 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. . The wiring trench 50T2 and the via hole 48V2 are filled with a Cu wiring pattern 50C2 and a Cu via plug 50V2 continuous therewith via the barrier metal film 50B2.

  Similarly, the side wall surface and bottom surface of the wiring trench 503 and the via hole 48V3 are continuously covered with a barrier metal film 50B3 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. The wiring trench 50T3 and the via hole 48V3 are filled with a Cu wiring pattern 50C3 and a Cu via plug 50V3 continuous therewith via the barrier metal film 50B3.

An interlayer insulating film 52 made of an inorganic or organic insulating film including a porous film is formed on the interlayer insulating film 50 via an etching stopper film 51 made of SiN or SiC.
On the interlayer insulating film 52, an interlayer insulating film 54 made of an inorganic or organic insulating film including a porous film is formed via an etching stopper film 53 made of SiN or SiC.

  In the interlayer insulating film 54, wiring grooves 54T1 and 54T2 are formed along a predetermined wiring pattern. Further, a via hole 52V1 is formed in the insulating film 52 so as to penetrate the etching stopper film 53 and expose the Cu wiring pattern 50C2 corresponding to the wiring groove 54T1. Further, a via hole 52V2 is formed in the insulating film 52 so as to penetrate the etching stopper film 53 and expose the Cu wiring pattern 50C3 corresponding to the wiring groove 54T2.

  The side wall surface and bottom surface of the wiring groove 54T1 and the via hole 52V1 are continuously covered with a barrier metal film 54B1 containing at least one refractory metal element such as Ta, Ti, Zr, or Ru. The wiring trench 54T1 and the via hole 52V1 are filled with a Cu wiring pattern 54C1 and a Cu via plug 54V1 continuous therewith via the barrier metal film 54B1.

  Similarly, the side wall surface and the bottom surface of the wiring groove 54T2 and the via hole 52V2 are continuously covered with a barrier metal film 54B2 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. . The wiring trench 54T2 and the via hole 52V2 are filled with a Cu wiring pattern 54C2 and a Cu via plug 54V2 continuous therewith via the barrier metal film 54B2.

  An interlayer insulating film 56 made of an inorganic or organic insulating film including a porous film is formed on the interlayer insulating film 54 via an etching stopper film 55 made of SiN or SiC. On the interlayer insulating film 56, an interlayer insulating film 58 made of an inorganic or organic insulating film including a porous film is formed via an etching stopper film 57 made of SiN or SiC.

  In the interlayer insulating film 58, wiring grooves 58T1 and 58T2 are formed along a predetermined wiring pattern. Furthermore, a via hole 56V1 is formed in the insulating film 56 so as to penetrate the etching stopper film 57 and expose the Cu wiring pattern 54C1 corresponding to the wiring groove 58T1. In addition, a via hole 56V2 is formed in the insulating film 56 so as to penetrate the etching stopper film 57 and expose the Cu wiring pattern 54C1 corresponding to the wiring groove 58T2. Similarly, a via hole 56V3 is formed in the insulating film 56 so as to penetrate the etching stopper film 57 and expose the Cu wiring pattern 54C2 corresponding to the wiring groove 58T3.

  The side wall surface and bottom surface of the wiring groove 58T1 and the via hole 56V1 are continuously covered with a barrier metal film 58B1 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. The wiring trench 58T1 and the via hole 56V1 are filled with a Cu wiring pattern 58C1 and a Cu via plug 58V1 continuous therewith via the barrier metal film 58B1.

  Similarly, the side wall surface and the bottom surface of the wiring groove 54T2 and the via hole 52V2 are continuously covered with a barrier metal film 54B2 containing at least one refractory metal element such as Ta, Ti, Zr or Ru. . The wiring trench 54T2 and the via hole 52V2 are filled with Cu wiring patterns 54C2 and 54V2 through the barrier metal film 54B2.

Further, an interlayer insulating film 60 made of an inorganic or organic insulating film including a porous film is formed on the interlayer insulating film 58 via an etching stopper film 59 made of SiN or SiC. On the interlayer insulating film 60, another interlayer insulating film 62 such as SiO ₂ is formed via an etching stopper film 61 made of SiN or SiC.

  In the another interlayer insulating film 62, a wiring trench 62T is formed along a predetermined wiring pattern. Further, a via hole 60V1 is formed in the interlayer insulating film 60 so as to penetrate the etching stopper film 59 and expose the Cu wiring pattern 58C3 corresponding to the wiring groove 62T.

  The side walls and bottom of the wiring trench 62T and the via hole 60V1 are continuously covered with a barrier metal film 68B containing at least one refractory metal element such as Ta, Ti, Zr or Ru. The wiring trench 62T and the via hole 61V1 are filled with a wiring pattern 62C made of Al or Cu and a via plug 62V made of Cu or Al which is continuous with the wiring pattern 62C via the barrier metal film 62B.

  Further, a cap film 63 made of SiN or the like is formed on the other interlayer insulating film 62 by plasma CVD or the like so as to cover the wiring pattern 62C.

In the semiconductor device 40 of FIG. 18 , when the Cu wiring patterns 46C1 to 46C2, 50C1 to 50C3, 54C1 to 54C2, 58C1 to 58C3. The Cu—Mn alloy layer corresponding to the obtained Cu—Mn alloy layer 22M or 26M has a film thickness capable of transferring substantially all of the Mn atoms in the Cu—Mn alloy layer to the adjacent barrier metal film, and / Or formed at a concentration.
For this reason, when the cap film 63 is formed, substantially all of the Mn atoms move to the adjacent barrier metal film, and Mn oxidation is performed only on a portion corresponding to the surface of the original Cu—Mn alloy layer. thin layer 46Ox1~46Ox2,50Ox1~50Ox3,54Ox1~54Ox2,58Ox1~58Ox3 is the object, characteristic cross-sectional structure remaining as indicated by the broken line is obtained in FIG. 18.

  In the semiconductor device 40 having such a multilayer wiring structure, as described above with reference to FIG. 14, by providing the Cu—Mg alloy layer having a high Mn concentration, the stress migration resistance is greatly improved, and the wiring made of Mn is also provided. An increase in resistance can be suppressed.

  In the present embodiment, the wiring trench 26T and the via hole 24V can also be executed by depositing a Cu layer by single or plural times, for example, MOCVD, in the step of FIG. 17M. In this case, the wiring trench 26T and the via hole 24V are filled with a Cu layer deposited by the MOCVD method, so that the electrolytic plating process of FIG. 17N can be omitted.

  In the present embodiment, in the step of forming the Cu—Mn alloy layer 22M or 26M in FIG. 17B or FIG. 17L, if the film thickness of the Cu—Mn alloy layer 22M or 26M is set to 1 nm or more and 4.5 nm or less, From the relationship of FIG. 10B described above, a Cu—Mn alloy film or Mn film containing Mn at a concentration of 0.2 atomic% to 100 atomic% is used for the Cu—Mn alloy layer 22M or 26M. It is understood that is possible.

  Further, in this embodiment, the Cu film 22C1 in the wiring groove 22T shown in FIG. 17C, and further the wiring groove 26T and the Cu layer 26C1 in the via hole 24V shown in FIG. 17M are formed by sputtering, and the wiring groove After the 22T, the wiring groove 26T, and the via hole 24V are filled by electrolytic plating, heat treatment at 80 ° C. to 120 ° C. is performed.

Similarly, in the semiconductor device 40 of FIG. 18, when the Cu wiring patterns 46C1 to 46C2, 50C1 to 50C3, 54C1 to 54C2, 58C1 to 58C3, etc. are formed, the Cu layer Cu film 22C1 described above or A similar heat treatment is also performed when a Cu layer corresponding to the Cu layer 26C1 is formed by a sputtering method, and when the Cu layer is filled by an electrolytic plating method.

[Second Embodiment]
FIG. 19A to FIG. 19P are views showing a process for forming a multilayer wiring structure using a dual damascene method according to the first embodiment of the present invention.

Referring to FIG. 19A, a wiring trench 82T corresponding to a predetermined wiring pattern is formed in an insulating film 82 formed on a semiconductor substrate 81 on which a transistor and a tungsten plug (not shown) are formed.
Further, a barrier metal film 82B containing at least one refractory metal element such as Ta, Ti, Zr, or Ru is formed on the insulating film 82 so as to cover the side wall surface and the bottom surface of the wiring groove 82T. By an (atomic layer deposition) method or the like, a film having a thickness of 1 to 15 nm is formed in a shape matching the cross-sectional shape of the wiring groove 82T. The barrier metal film 82B is not limited to a metal film, and other than a metal film containing one or more metal elements selected from Ta, Ti, Zr, Ru, such as TaN and TiN, conductive metal nitridation. It may be a membrane.

  Next, as shown in FIG. 19B, a Cu—Mn alloy film 22M containing Mn is formed on the barrier metal film 82B shown in FIG. 19A so as to match the cross-sectional shape of the wiring groove 22T. By sputtering using a Mn alloy target, a plasma power of 10 kW is applied at a substrate temperature of room temperature or lower in an Ar atmosphere of 10-1 Pa to form an arbitrary thickness of, for example, 30 nm.

  In the step of FIG. 19B, when the Mn concentration in the Cu—Mn alloy film 82M thus formed is about 30 atomic% or less, for example, between 0.2 atomic% and 30 atomic%, The film thickness of the Cu—Mn alloy film 82M is adjusted by an etching process such as Ar ion etching so as to have a film thickness of about 15 nm or less, for example, in the range of 0 to 15 nm, on a flat surface.

  When the Mn concentration in the Cu—Mn alloy film 82M exceeds 30 atomic%, the Cu—Mn alloy film 82M has a film thickness on a flat surface of x in the Cu—Mn alloy film 82M. Assuming the atomic concentration of Mn, the film thickness is adjusted by the same etching process so as to be equal to or less than the film thickness y given by the equation y = 465 / x.

  Next, as shown in FIG. 19C, a Cu film 82C1 is formed on the structure of FIG. 19B as a plating seed layer, for example, by a sputtering method or a CVD method so as to match the cross-sectional shape of the wiring groove 82T. It is formed to a thickness of 80 nm.

  Next, as shown in FIG. 19D, a Cu layer 82C2 is formed on the structure of FIG. 19C using the Cu film 82C1 as a plating seed layer so as to fill the wiring trench 82T. Further, as shown in FIG. 19E, the structure of FIG. 19D is polished by CMP until the surface of the insulating film 82 is exposed. As a result, a structure in which the wiring groove 82T is filled with the Cu wiring pattern 82C is obtained.

Further, on the structure of FIG. 19E, as shown in FIG. 19F, an etching stopper film 83 made of SiN or SiC is formed to a thickness of 10 to 100 nm so as to cover the Cu wiring pattern 82C. Such an etching stopper film 83 is typically formed at a temperature of 400 ° C. As a result, the Cu film 82C1 and the Cu film 82C2 constituting the Cu wiring pattern 82C are fused to form a single Cu film. Further, Mn atoms in the Cu-Mn alloy layer 82M move into the barrier metal film 82B by the thermal heat treatment at that time. Accordingly, the original Cu—Mn alloy layer 82M disappears in the Cu wiring pattern 82C. However, at a position corresponding to the surface of the original Cu—Mn alloy layer 82M, a thin layer of Mn oxide is formed from the surface of the barrier metal film 82B, as indicated by a broken line 82Ox in FIG. The alloy layers 82M are formed apart by a distance corresponding to the film thickness.
As a result, the Cu wiring pattern 82C includes a region 82c1 where the original Cu-Mn alloy layer 82M was present and a region 82c2 where the original Cu layers 82C1 and 82C2 were present.

  Next, as shown in FIG. 19G, an interlayer insulating film 84 having a thickness of 100 to 300 nm, an etching stopper film 85 made of SiC or SiN film having a thickness of 10 to 100 nm, and a thickness on the structure of FIG. 19F. Are sequentially formed by, for example, a plasma CVD method. Further, a wiring groove 86T exposing the etching stopper film 85 is formed in the interlayer insulating film 86 with a desired width by a dry etching process. As the interlayer insulating films 84 and 86, a silicon oxide film formed by the plasma CVD method using TEOS described above as a raw material, or formed by a plasma CVD method or a coating method, and having a relative dielectric constant of 3 or less. It may be an organic or inorganic insulating film. For example, even when an organic polymer film of the registered trade name SiLK is used as the interlayer insulating films 84 and 86, these films contain a substantial amount of oxygen (moisture) due to etching damage or the like. .

  Next, as shown in FIG. 19H, an opening 85V corresponding to a predetermined via hole is formed in the etching stopper film 85 exposed in the wiring groove 86T. Further, as shown in FIG. 19I, using the etching stopper film 85 as a hard mask, a via hole 84V is formed in the interlayer insulating film 84 so that the etching stopper film 83 is exposed.

  Further, as shown in FIG. 19J, the etching stopper film 83 is removed at the bottom of the via hole 84V to expose the Cu wiring pattern 82C. Thereafter, as shown in FIG. 19K, a barrier made of Ta or Ti is formed on the interlayer insulating film 86 so as to continuously cover the side wall surface and bottom surface of the wiring groove 86T and the side wall surface and bottom surface of the via hole 84V. The metal film 86B is formed to a thickness of 1 to 15 nm by a sputtering method or an ALD method in a shape that matches the cross-sectional shape of the wiring groove 86T and the via hole 84V. The barrier metal film 86B is not limited to a metal film, and other than a metal film containing one or more metal elements selected from Ta, Ti, Zr, Ru, such as TaN and TiN, conductive metal nitridation. It may be a membrane.

  Next, as shown in FIG. 19L, on the structure of FIG. 19K, a Cu—Mn alloy layer 86M covers the barrier metal film 86B with a shape that matches the cross-sectional shape of the wiring groove 86T and the via hole 86V. A film thickness of 1 to 15 nm is formed by sputtering.

  Further, as shown in FIG. 19M, in the structure of FIG. 19L, the sputtering method is performed in a shape that matches the cross-sectional shape of the wiring groove 86T and the via hole 84V so that the Cu layer 86C1 covers the Cu—Mn alloy layer 86M. Or it forms in the film thickness of 25-65 nm by CVD method. Further, on the structure of FIG. 19M, as shown in FIG. 19N, a Cu layer 86C2 is formed so as to fill the wiring groove 86T and the via hole 84V by electrolytic plating using the Cu layer 86C1 as a plating seed layer. The

  Further, as shown in FIG. 19O, the Cu layers 86C1 and 86C2, the Cu—Mn alloy layer 86M, and the barrier metal film 86B on the interlayer insulating film 86 are polished by CMP until the surface of the interlayer insulating film 86 is exposed. -Removed. Further, as shown in FIG. 19P, a cap layer 87 made of a SiN film or a SiC film is formed on the structure of FIG. 19O by a plasma CVD method typically performed at a substrate temperature of 400.degree.

  Due to the heat accompanying the formation of the cap layer 87, the Cu layer 86C1 and the Cu layer 86C2 are fused in the wiring groove 86T and the via hole 84V, and extend continuously from the single Cu wiring pattern 86C. A Cu via plug 86V is formed.

  Further, Mn atoms in the Cu—Mn alloy layer 86M move to the barrier metal film 86B due to the heat accompanying the formation of the cap layer 87. The Mn atoms moved in this way are in the form of Mn oxide in the barrier metal film 86B or the barrier metal film 86B by oxygen from the interlayer insulating films 84 and 86 and the etching stopper films 83 and 85. Stablely deposits at the interface with the Cu wiring pattern 86C or the Cu via plug 86V, the interface between the barrier metal film 86B and the interlayer insulating film 84 or 86, or the interface between the barrier metal film 86B and the etching stopper film 83 or 85. .

  Further, when there is a defect in the barrier metal film 86B, the defect is self-repaired by the Mn oxide thus precipitated.

  Further, as the Mn atoms in the Cu—Mn metal layer 86M move to the barrier metal film 26B in this way, the positions corresponding to the initial surface of the Cu—Mn metal layer 86M are described above. In FIG. 19L, the Mn oxide layer 26Ox corresponding to the oxide layer formed on the surface of the Cu-Mn metal layer 86M is formed from the surface of the barrier metal film 86B to the original film thickness of the Cu-Mn alloy layer 86M. Are spaced apart by a distance corresponding to. As a result, as shown in FIG. 19P, the Cu wiring pattern 86C includes the Cu layer formed in the region 86c1 where the original Cu-Mn alloy layer 86M was present, and the original Cu layers 86C1 and 86C2. And a Cu layer formed in the region 86c2.

  By repeating such steps on a semiconductor substrate such as a silicon substrate on which a transistor is formed, the semiconductor device 40 described above with reference to FIG. 18 can be manufactured also in this embodiment.

  In the present embodiment, the wiring trench 86T and the via hole 84V can be performed by depositing a Cu layer by single or plural times, for example, by MOCVD, in the step of FIG. 19M. In this case, the wiring groove 86T and the via hole 84V are filled with a Cu layer deposited by the MOCVD method, so that the electrolytic plating process of FIG. 19N can be omitted.

  In this embodiment, in the step of forming the Cu—Mn alloy layer 82M or 86M in FIG. 19B or FIG. 19L, if the film thickness of the Cu—Mn alloy layer 82M or 86M is 1 nm or more and 4.5 nm or less, From the relationship of FIG. 10B described above, a Cu—Mn alloy film or Mn film containing Mn at a concentration of 0.2 atomic% to 100 atomic% is used for the Cu—Mn alloy layer 82M or 86M. It is understood that is possible.

  In this embodiment, the etching process of FIG. 19B can be performed until the barrier metal 82B at the bottom of the wiring trench 82T is exposed as shown in FIG. 20A.

In this case, the Cu—Mn alloy layer 82M is removed from the bottom of the wiring groove 82T, and the Cu—Mn alloy layer 82M has a Mn concentration in the film of 0.2 atomic% or more and 30 atomic% or less. In this case, it is formed with the film thickness of 1 to 15 nm only on the side wall surface of the wiring groove 82T.
When the Mn concentration in the Cu—Mn alloy layer 82B exceeds 30 atomic%, the Cu—Mn alloy layer 82M is a film whose film thickness on the side wall surface is defined by the relationship shown in FIG. 10B. For example, the film thickness is in the range of 1 nm to 4.5 nm so as to be less than or equal to the thickness.

  For this reason, when the heat treatment of FIG. 19F is performed, the Mn oxide layer 82Ox showing the trace of the presence of the original Cu—Mn alloy layer 82M is formed from the barrier metal film 82B along the side wall surface of the wiring groove 82T. The Cu—Mn alloy layer 82 </ b> M is formed at a distance corresponding to the film thickness. The present invention also includes such a structure.

  In this embodiment, the seed Cu film 82C1 in the wiring groove 82T shown in FIG. 19C, the wiring groove 86T and the Cu layer 86C1 of the via hole 84V shown in FIG. 19M are formed by sputtering, When the wiring groove 82T, the wiring groove 86T, and the via hole 84V are filled by an electrolytic plating method, a heat treatment at 80 ° C. to 120 ° C. is subsequently performed after plating.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A semiconductor substrate;
An insulating film containing oxygen formed above the semiconductor substrate;
A recess formed in the insulating film;
A first film containing copper formed on the inner wall of the recess;
A second film comprising copper embedded in the recess above the first film;
A semiconductor device having an oxide layer containing manganese between the first film and the second film.
(Appendix 2)
The semiconductor device according to appendix 1, wherein a diffusion prevention film is provided between the insulating film and the first film.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the diffusion preventing film includes at least one element selected from Ta, Ti, Zr, and Ru.
(Appendix 4)
4. The semiconductor device according to appendix 2 or 3, wherein the diffusion preventing film contains manganese.
(Appendix 5)
The semiconductor device according to appendix 1 or 2, wherein the thickness of the first film is in the range of 1 nm to 15 nm.
(Appendix 6)
Forming a transistor having at least a gate electrode and source / drain regions on a semiconductor substrate;
Forming an insulating film containing oxygen above the semiconductor substrate;
Forming a recess in the insulating film;
Forming a metal film containing copper and manganese on the inner wall of the recess to a predetermined thickness;
Forming a film including copper above the metal film and filling the recess;
And a step of performing a heat treatment after the formation of the film containing copper.
(Appendix 7)
The method for manufacturing a semiconductor device according to appendix 6, including a step of forming a diffusion prevention film between the insulating film and the metal film.
(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the metal film has a Mn concentration of 0.2 atomic% to 30 atomic% and a film thickness of 1 nm to 15 nm.
(Appendix 9)
8. The method for manufacturing a semiconductor device according to appendix 6 or 7, wherein the metal film has a Mn concentration of 0.2 atomic% to 100 atomic% and a film thickness of 1 nm to 4.5 nm.
(Appendix 10)
10. The manufacturing method of a semiconductor device according to any one of appendices 6 to 9, wherein the diffusion preventing film is a refractory metal film containing at least one element selected from Ta, Ti, Zr, and Ru. Method.
(Appendix 11)
The method for manufacturing a semiconductor device according to appendix 6, further comprising a step of forming the metal film into a predetermined film thickness by etching.
(Appendix 12)
The method for manufacturing a semiconductor device according to appendix 6, further comprising the step of etching to form a predetermined thickness on the inner surface of the recess side wall after the metal film is formed.
(Appendix 13)
14. The method for manufacturing a semiconductor device according to any one of appendices 6 to 13, wherein a seed film containing copper is formed on the metal film.
(Appendix 14)
14. The method of manufacturing a semiconductor device according to any one of appendices 6 to 13, wherein the metal film is formed by a sputtering method.
(Appendix 15)
The step of forming the copper-containing film filling the concave portion includes a step of filling the concave portion and forming the copper-containing film by an electrolytic plating method, and a heat treatment after the formation of the copper-containing film by the electrolytic plating method. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed at a temperature of 120 ° C. 10.
(Appendix 16)
Forming a transistor having a gate electrode and source / drain regions on a semiconductor substrate;
Forming an insulating film containing oxygen above the semiconductor substrate;
Forming a recess in the insulating film;
Forming a metal film containing copper and manganese on the inner wall of the recess;
Forming a film including copper above the metal film and filling the recess;
Performing a heat treatment after the formation of the film containing copper;
Have
The film thickness of the metal film is
When the Mn concentration x expressed in atomic% in the metal film is 0 atomic% <x <30 atomic%, it is set to 15 nm or less, and the Mn concentration x is 30 atomic% ≦ x ≦ 100 atomic%. In this case, the semiconductor device manufacturing method is characterized in that the film thickness y [nm] given by the equation y = 465 [atomic% · nm] / x is set.
(Appendix 17)
The step of forming the copper-containing film filling the concave portion includes a step of filling the concave portion and forming the copper-containing film by an electrolytic plating method, and a heat treatment after the formation of the copper-containing film by the electrolytic plating method. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed at a temperature of 120 ° C. 10.
(Appendix 18)
18. The method of manufacturing a semiconductor device according to appendix 15 or 17, wherein the heat treatment step is performed for 60 to 250 seconds.

It is a figure which shows the effect of the Cu-Mn alloy layer in the conventional barrier metal structure. It is a figure which shows the structure of the test piece used in this invention. It is a figure which shows the copper wiring immediately after electrolytic plating. It is a figure explaining the phenomenon at the time of performing the conventional heat processing immediately after electrolytic plating. It is a figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. (A), (B) is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is a Cu-Mn type phase equilibrium diagram. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is another figure explaining the principle of this invention. It is a figure explaining the effect of this invention. It is another figure explaining the effect of this invention. It is another figure explaining the effect of this invention. FIG. 6 is a view (No. 1) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a view (No. 3) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a view (No. 4) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention; FIG. 8 is a view (No. 5) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention; It is FIG. (6) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (8) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. 1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment. It is FIG. (1) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. FIG. 11 is a diagram (No. 2) for illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention; It is FIG. (3) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is FIG. (1) which shows the modification of the 2nd Embodiment of this invention. It is a figure (the 2) which shows the modification of the 2nd Embodiment of this invention.

Explanation of symbols

11, 21, 41, 81 Substrate 12, 14, 16, 22, 24, 26, 82, 84, 86 Interlayer insulating film 12B, 16B, 26B, 82B, 86B Barrier metal film 12C, 16C, 22C, 82C Cu wiring pattern 12T, 16T, 22T, 26T, 82T, 86T Wiring groove 13, 15, 23, 25, 83, 85 Etching stopper film 14V, 24V, 84V Via hole 16c1, 16c, 22c1, 22c2, 26c1, 26c2, 82c1, 82c2 Cu region 12M, 16M, 22M, 26M, 82M, 86M Cu-Mn alloy layer 12Ox, 16Ox, 22Ox, 26Ox, 82Ox, 86Ox oxide layer 16V, 26V Cu via plug 26C1 Cu seed layer 26C2 Cu electroplating layer 26c1, 26c2 Cu region 27 , 87 ki Layer 40 semiconductor device 41A element region 41I element isolation structure 41a, 41b, 41c diffusion region 42A, 42B, 42C gate insulating film 43A, 43B, 43C gate electrode 44, 44A, 44B, 44C insulating film 44V1-44V2, 48V1 48V3, 56V1 to 56V2, 60V Via hole 45, 47, 49, 51, 53, 57, 59, 61 Etching stopper film 46, 48, 50, 52, 54, 56, 58, 60 Interlayer insulating film 46C1 to 46C2, 50C1 50C3, 54C1-54C2, 58C1-58C3
Cu wiring pattern 46T1 to 46T2, 50T1 to 50T3, 54T1 to 54T2, 58T1 to 58T3, 62T wiring groove 46V1 to 46V2 tungsten plug 48V1 to 48V3, 54V1 to 54V2, 58V1 to 58V3, 62V Cu via plug 46B1 to 46B2, 50B1 to 50B3 54B1-54B2, 58B1-58B3, 62B Barrier metal film 63 Cap layer

Claims (8)

A semiconductor substrate;
An insulating film containing oxygen formed above the semiconductor substrate;
A recess formed in the insulating film;
A barrier metal film containing manganese formed on the inner wall of the recess;
A first film containing copper formed on the barrier metal film;
A second film comprising copper embedded in the recess above the first film;
Have a oxide layer containing manganese between said first film and said second film,
The semiconductor device according to claim 1, wherein the manganese concentration of the barrier metal film is higher than the manganese concentration of the first film .   2. The semiconductor device according to claim 1, wherein the thickness of the first film is in the range of 1 nm to 15 nm. Forming a transistor having a Gate electrode and the source and drain regions in the semiconductor substrate,
Forming an insulating film containing oxygen above the semiconductor substrate;
Forming a recess in the insulating film;
Forming a barrier metal film on the inner wall of the recess;
Forming a metal film containing copper and manganese on the barrier metal film to a predetermined thickness;
Forming a film including copper above the metal film and filling the recess;
By heat treatment after formation of the film containing the copper, have a, a step of diffusing a manganese of the metal film to the barrier metal film,
A method for manufacturing a semiconductor device , wherein a manganese concentration of the barrier metal film after the heat treatment is higher than a manganese concentration of the metal film after the heat treatment . Mn concentration of the metal film before the heat treatment is 0.2 atomic% to 30 atomic%, and a thickness of a semiconductor device according to claim 3 Symbol mounting, characterized in that in the range of 1nm~15nm Production method. Mn concentration of the metal film before the heat treatment, 0.2 atom% to 100 atom%, and The method according to claim 3 Symbol mounting of the semiconductor device, wherein the film thickness is 1nm~4.5nm . The Mn concentration of the metal film before the heat treatment is 0.2 atomic% to 30 atomic%, and the metal film is formed to have a film thickness of 15 nm or less by etching after forming an arbitrary film thickness. The method of manufacturing a semiconductor device according to claim 3 . Step of forming the film containing copper to fill the recess, a step of forming a film of the electrolytic plating method comprising the copper filling the recess, the heat treatment after formation by electrolytic plating film containing the copper, 100 The method of manufacturing a semiconductor device according to claim 3 , wherein the method is performed at a temperature of 150 ° C. The thickness of the previous Symbol metal film,
When the manganese concentration x expressed in atomic% in the metal film before the heat treatment is 0 atomic% <x <30 atomic%, it is set to 15 nm or less, and the manganese concentration x is 30 atomic% ≦ x 4. The method of manufacturing a semiconductor device according to claim 3, wherein when ≦ 100 atomic%, the thickness is set to be equal to or less than the film thickness y [nm] given by the equation y = 465 [atomic% · nm] / x.