KR20000042980A - Method for forming metal wiring of semiconductor device - Google Patents

Method for forming metal wiring of semiconductor device Download PDF

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Publication number
KR20000042980A
KR20000042980A KR1019980059279A KR19980059279A KR20000042980A KR 20000042980 A KR20000042980 A KR 20000042980A KR 1019980059279 A KR1019980059279 A KR 1019980059279A KR 19980059279 A KR19980059279 A KR 19980059279A KR 20000042980 A KR20000042980 A KR 20000042980A
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South Korea
Prior art keywords
nitride film
metal wiring
plug
contact hole
forming
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KR1019980059279A
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Korean (ko)
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KR100511092B1 (en
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문병오
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

PURPOSE: A dual damascene method for forming metal wiring of a semiconductor device is provided to reduce a permittivity of a dielectric layer and to prevent an etch-stop. CONSTITUTION: In a dual damascene process, a buffer layer(30) is deposited on a semiconductor substrate(10) having a metal wiring(20) formed therein. Next, a nitride layer is formed on the buffer layer(30), and then selectively etched to form a nitride plug(40'). The etch process of the nitride layer is performed while power is applied in a range of 300 to 700 W and pressure is in a range of 100 to 200 mTorr. In addition, CHF<SB POS="POST">3</SB> gas is supplied with a flow rate in a range of 30 to 60 sccm(standard cubic cm per minute), CF<SB POS="POST">4</SB> gas is supplied with a flow rate in a range of 10 to 30 sccm, and Ar gas is supplied with a flow rate in a range of 50 to 100 sccm. Next, a dielectric layer(50) is formed on the buffer layer(30) to the same thickness than the nitride plug(40'). Then, a photoresist layer(60) is deposited on the dielectric layer(50) and etched to form a first contact hole for exposing the nitride plug(40'). The nitride plug(40') exposed through the first contact hole is then removed, and therefore a second contact hole is formed in the dielectric layer(50) while exposing the metal wiring(20). The first and second contact holes are then filled with a copper layer.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 금속배선을 형성하기 위한 이중상감법에 관한 것으로서, 특히, 이중콘택홀을 새로운 이중상감법으로 형성하고, 이 콘택홀내에 구리배선을 형성하므로 콘택시 에치스톱(Etch-Stop)을 없애고, 절연막의 유전율을 낮추어 금속배선을 안정적으로 형성하게 되어 소자의 전기적인 특성과 신뢰성을 향상시키도록 하는 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double damascene method for forming a metal wiring, and in particular, a double contact hole is formed by a new double damascene method, and copper wiring is formed in the contact hole, thereby eliminating an etch stop during contact. In addition, the present invention relates to a method for forming a metal wiring of a semiconductor device to lower the dielectric constant of the insulating film to stably form a metal wiring to improve electrical characteristics and reliability of the device.

일반적으로, 반도체소자를 제조하는 데 있어, 선폭의 길이가 0.25㎛이하의 세대로 접어듬에 따라 기존의 제조방식에 한계점을 드러내게 되었다. 특히, 비메모리소자의 경우에는 RC지연시간(RC Delay Time)을 줄이고 소자의 속도 향상을 위하여서는 저유전막의 저유전율화 및 금속배선의 재료로써 기존의 알루미늄 대신에 구리배선을 사용하려는 연구가 최근에 활발하게 진행되고 있다.In general, in manufacturing a semiconductor device, as the length of the line width is folded into a generation of 0.25 μm or less, a limitation of the existing manufacturing method is revealed. In particular, in the case of non-memory devices, a study of using copper wiring instead of aluminum as a material of low dielectric constant and metal wiring to reduce RC delay time and improve device speed has recently been made. Is actively underway.

그런데, 이 구리를 사용하기 위하여서는 에칭방법을 개선하여야 하는 점이 주된 안점으로 대두되었으며, 이중에 종래에 금속배선을 형성하기 위하여 주로 사용되던, RIE(Reactive Ion Etching)방식으로는 구리배선을 형성하기 어렵다는 점이 다.However, in order to use the copper, the main point has been to improve the etching method, and among them, to form the copper wiring by the RIE (Reactive Ion Etching) method, which is mainly used to form metal wiring in the past. It is difficult.

따라서, 최근에 상감법(Damascence)으로 금속배선을 형성하도록 하는 시도가 이루어지고 있으며, 이 상감법은 먼저, 기판상에 절연층을 패터닝한 후 금속을 증착하여 화학기계적연마(CMP; Chemical Mechanical Polishing)방법을 진행하여 금속배선을 형성하는 방법이다. 특히, 이중상감법(Dual Damascence)은 콘택 혹은 비아홀을 금속배선과 같이 패터닝한 후 금속을 증착하므로 제조비용 및 신뢰성 측면에서 유리한 공정이다.Therefore, in recent years, attempts have been made to form metal interconnections by damascene, which is first patterned with an insulating layer on a substrate, followed by deposition of metal to chemical mechanical polishing (CMP). It is a method of forming metal wiring by going through the method. In particular, the dual damascene method is advantageous in terms of manufacturing cost and reliability because the metal is deposited after the contact or via hole is patterned like metal wiring.

그런데, 상기한 이중상감법에 해결하여야 할 과제가 있는 데, 첫 번째로 절연막 중간에 얇은 차단층(Stopping Layer, 주로 실리콘질화막을 사용함)을 사용하는 경우 절연막의 유전율을 높이게 되며, 또한, 식각공정의 측면에서는 실리콘질화막의 선택비가 높은 식각조건이 필요하고 식각되는 절연막의 두께가 깊어짐에 따라 상대적으로 감광막에 대한 높은 선택비를 요구하며 에칭 스톱(Etching-Stop)이 발생되는 문제점이 있었다.However, there is a problem to be solved in the double damascene method. First, when a thin blocking layer (mainly a silicon nitride film) is used in the middle of the insulating film, the dielectric constant of the insulating film is increased, and the etching process In terms of, an etching condition requiring a high selectivity of the silicon nitride film is required, and as the thickness of the insulating film to be etched is increased, a relatively high selectivity for the photoresist film is required and an etching stop occurs.

또한, 소자의 선폭이 0.25㎛이하인 경우에는 오버레이 마진(Overlay Margin)이 타이트(Tight)하기 때문에 마스크공정에서 부정합(Misalign)이 발생되어 콘택저항(비아저항) 증가 및 신뢰성에 문제점이 발생하였다.In addition, when the line width of the device is 0.25 μm or less, since the overlay margin is tight, misalignment occurs in the mask process, thereby causing problems in increasing contact resistance (via resistance) and reliability.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 하부에 형성된 금속배선을 상부로 연결하는 데 있어, 기판 상에 버퍼층 및 질화막을 순차로 적층한 후 질화막을 식각하여 질화막플러그를 형성한 후 절연막을 적층하여 제1,콘택홀을 형성하고, 노출된 질화막플러그를 제거하므로 금속배선으로 연결되는 이중콘택홀을 형성하고, 이 콘택홀내에 금속층을 적층하여 금속배선을 형성하므로 콘택시 에치스톱을 없애고, 절연막의 유전율을 낮추어 금속배선을 안정적으로 형성하는 것이 목적이다.The present invention has been made in view of this point, and in order to connect the metal wiring formed on the lower portion of the semiconductor substrate to the top, the buffer layer and the nitride film are sequentially stacked on the substrate, the nitride film is etched to form a nitride film plug, and then the insulating film To form a first contact hole and to remove the exposed nitride film plug to form a double contact hole connected to the metal wiring, and to form a metal wiring by stacking a metal layer in the contact hole to eliminate the etch stop during contact The purpose is to lower the dielectric constant of the insulating film and to stably form the metal wiring.

도 1 내지 도 4는 본 발명에 따른 금속배선 형성방법을 순차적으로 도시한 상태를 보인 도면.1 to 4 are views showing a state in which the metal wiring forming method according to the invention sequentially showing.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

10 : 반도체기판 20 : 금속배선10: semiconductor substrate 20: metal wiring

30 : 버퍼층 40 : 질화막30 buffer layer 40 nitride film

40' : 질화막플러그 45 : 감광막40 ': nitride film plug 45: photosensitive film

50 : 절연막 60 : 감광막50: insulating film 60: photosensitive film

70 : 제1콘택홀 80 : 제2콘택홀70: first contact hole 80: second contact hole

이러한 목적은 반도체기판의 하부층에 금속배선을 형성한 후 상기 결과물 상에 버퍼층을 적층하는 단계와; 상기 단계 후에 버퍼층 상에 질화막을 적층한 후 플러그가 형성될 부위에 감광막을 형성하는 단계와; 상기 단계 후에 질화막을 식각하여 질화막플러그를 형성한 후 이 질화막플러그와 동일한 높이로 버퍼층 상에 절연막을 적층하도록 하는 단계와; 상기 단계 후에 질화막플러그를 개방하는 상태로 감광막을 적층한 후 식각으로 질화막플러그의 일부가 노출되도록 제1콘택홀을 형성하는 단계와; 상기 단계 후에 제1콘택홀로 노출된 질화막플러그를 식각하여 하부층의 금속배선으로 연결되는 제2콘택홀을 형성하는 단계를 포함하는 반도체소자의 금속배선형성방법을 제공함으로써 달성된다.The object is to form a metal wiring on the lower layer of the semiconductor substrate and then deposit a buffer layer on the resultant; Stacking a nitride film on the buffer layer after the step, and then forming a photosensitive film on a portion where a plug is to be formed; Etching the nitride film after the step to form a nitride film plug, and then stacking an insulating film on the buffer layer at the same height as the nitride film plug; Forming a first contact hole to expose a portion of the nitride film plug by etching after stacking the photoresist with the nitride film plug open; After the step is achieved by providing a method for forming a metal wiring of the semiconductor device comprising the step of etching the nitride film plug exposed to the first contact hole to form a second contact hole connected to the metal wiring of the lower layer.

그리고, 상기 버퍼층(Buffer Layer)은 실리콘산화막을 이용하고, 500 ∼ 1000Å의 두께로 형성하도록 하고, 상기 질화막은 15000 ∼ 20000Å의 두께로 형성하도록 한다.The buffer layer is formed to have a thickness of 500 to 1000 GPa using a silicon oxide film, and the nitride film is to be formed to a thickness of 15000 to 20000 GPa.

그리고, 상기 질화막을 식각하여 질화막플러그를 형성할 때 건식식각을 이용하여 300 ∼ 700Watt의 전력과, 100 ∼ 200mtorr의 압력으로 공정을 진행하고, 또한, CHF3가스를 30 ∼ 60 sccm의 유량으로, CF4가스를 10 ∼ 30sccm의 유량으로, Ar가스를 50 ∼100 sccm의 유량으로 공급하여 진행하도록 한다.When the nitride film is etched to form the nitride film plug, the process is performed using a dry etching at a power of 300 to 700 Watts and a pressure of 100 to 200 mtorr, and the flow of CHF 3 gas at a flow rate of 30 to 60 sccm, The CF 4 gas is supplied at a flow rate of 10 to 30 sccm, and the Ar gas is supplied at a flow rate of 50 to 100 sccm to proceed.

한편, 상기 제1콘택홀을 형성할 때 절연막을 7000 ∼ 9000Å의 두께로 식각하도록 한다.Meanwhile, when the first contact hole is formed, the insulating film is etched to a thickness of 7000 to 9000 kPa.

그리고, 상기 제2콘택홀을 형성할 때, 습식식각으로 질화막플러그를 식각하고, 160 ∼ 180℃의 온도범위를 갖는 진한 인산용액으로 식각하도록 한다. 또한, 상기 제2콘택홀을 형성할 때 버퍼층을 블랭킷 건식식각으로 제거하여 금속배선을 노출시키도록 한다.When the second contact hole is formed, the nitride film plug is etched by wet etching, and the second contact hole is etched with a concentrated phosphoric acid solution having a temperature range of 160 to 180 ° C. In addition, when forming the second contact hole, the buffer layer is removed by blanket dry etching to expose the metal wiring.

이하, 첨부한 도면에 의거하여 본 발명의 바람직한 일실시예에 대하여 상세히 살펴보도록 한다.Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 4는 본 발명에 따른 금속배선 형성방법을 순차적으로 도시한 상태를 보인 도면이다.1 to 4 are views showing a state in which the metal wiring forming method according to the present invention sequentially shown.

도 1은 반도체기판(10)의 하부층에 금속배선(20)을 형성한 후 상기 결과물 상에 버퍼층(30)을 적층하도록 하고, 연속하여 상기 버퍼층(30) 상에 질화막(40)을 적층한 후 플러그가 형성될 부위에 감광막(45)을 형성하는 상태를 도시하고 있다.FIG. 1 shows that after forming the metal wiring 20 on the lower layer of the semiconductor substrate 10, the buffer layer 30 is stacked on the resultant, and the nitride film 40 is successively stacked on the buffer layer 30. The state which forms the photosensitive film 45 in the site | part which will form a plug is shown.

상기 버퍼층(30)은 실리콘산화막을 형성하고, 500 ∼ 1000Å의 두께로 형성하, 상기 질화막(40)은 15000 ∼ 20000Å의 두께로 형성하도록 한다.The buffer layer 30 forms a silicon oxide film, is formed to a thickness of 500 ~ 1000Å, and the nitride film 40 is formed to a thickness of 15000 ~ 20000Å.

도 2는 상기 단계 후에 질화막(40)을 식각하여 질화막플러그(40')을 형성한 후 이 질화막플러그(40')와 동일한 높이로 버퍼층(30) 상에 절연막(50)을 적층하는 상태를 도시하고 있다.FIG. 2 shows a state in which the nitride film 40 is etched after the above step to form the nitride film plug 40 'and the insulating film 50 is stacked on the buffer layer 30 at the same height as the nitride film plug 40'. Doing.

그리고, 상기 질화막(40)을 식각하여 질화막플러그(40')를 형성할 때 건식식각(Dry Etch)을 이용하여 300 ∼ 700Watt의 전력과, 100 ∼ 200mtorr의 압력으로 진행하도록 한다.In addition, when the nitride film 40 is etched to form the nitride film plug 40 ', dry etching is performed using a power of 300 to 700 Watts and a pressure of 100 to 200 mtorr.

또한, 상기 질화막(40)을 식각할 때, CHF3가스를 30 ∼ 60 sccm의 유량으로, CF4가스를 10 ∼ 30sccm의 유량으로, Ar가스를 50 ∼100 sccm의 유량으로 공급하여 진행하도록 한다.In addition, when the nitride film 40 is etched, CHF 3 gas is supplied at a flow rate of 30 to 60 sccm, CF 4 gas is supplied at a flow rate of 10 to 30 sccm, and Ar gas is supplied at a flow rate of 50 to 100 sccm. .

그리고, 도 3은 상기 단계 후에 질화막플러그(40')를 개방하는 상태로 감광막(60)을 적층한 후 식각으로 질화막플러그(40')의 일부가 노출되도록 제1콘택홀(70)을 형성하는 상태를 도시하고 있다.3 shows that the first contact hole 70 is formed such that a portion of the nitride film plug 40 'is exposed by etching after stacking the photoresist film 60 with the nitride film plug 40' open after the step. The state is shown.

이때, 상기 제1콘택홀(70)을 형성할 때 절연막(50)을 7000 ∼ 9000Å의 두께로 식각하여서 질화막플러그(40')를 노출하도록 한다.At this time, when the first contact hole 70 is formed, the insulating film 50 is etched to a thickness of 7000 to 9000 Å to expose the nitride film plug 40 '.

도 4는 상기 단계 후에 제1콘택홀(70)로 노출된 질화막플러그(40')를 식각하여 하부층의 금속배선(20)으로 연결되는 제2콘택홀(80)을 형성하는 상태를 도시한 것이다.FIG. 4 illustrates a state in which the nitride film plug 40 'exposed to the first contact hole 70 is etched to form a second contact hole 80 connected to the metal wiring 20 of the lower layer after the step. .

그리고, 상기 제2콘택홀 (80)을 형성할 때, 습식식각(Wet Etch)으로 질화막플러그(40')를 식각하고, 160 ∼ 180℃의 온도범위를 갖는 인산용액으로 식각하도록 한다.When the second contact hole 80 is formed, the nitride film plug 40 'is etched by wet etching and then etched with a phosphoric acid solution having a temperature range of 160 to 180 ° C.

또한, 상기 제2콘택홀(80)을 형성할 때 버퍼층(30)을 블랭킷 건식식각(Blancket Dry Etch)으로 형성하도록 한다.In addition, when the second contact hole 80 is formed, the buffer layer 30 may be formed by blanket dry etching.

이와 같이 구성된 제1,제2콘택홀(70)(80)에 도시되지는 않았지만 구리금속층을 몰입시켜 식각으로 금속배선이 상부금속배선과 연결되도록 하므로 새로운 이중상감법으로 구리를 금속배선으로 적용하는 데 큰 문제 없도록 한다.Although not shown in the first and second contact holes 70 and 80 configured as described above, the copper wiring is immersed so that the metal wiring is connected to the upper metal wiring by etching, thereby applying copper to the metal wiring by a new double damascene method. Do not have a big problem.

따라서, 상기한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법을 이용하게 되면, 반도체기판 하부에 형성된 금속배선을 상부로 연결하는 데 있어, 기판 상에 버퍼층 및 질화막을 순차로 적층하고 질화막을 식각하여 질화막플러그를 형성한 후 절연막을 적층하여 제1,콘택홀을 형성하고, 노출된 질화막플러그를 제거하므로 하부층의 금속배선으로 연결되는 이중콘택홀을 새로운 이중상감법으로 형성하고, 이 콘택홀내에 금속층을 적층하여 금속배선, 특히, 구리배선을 형성하므로 콘택시 에치스톱(Etch-Stop)을 없애고, 절연막의 유전율을 낮추어 금속배선을 안정적으로 형성하게 되어 소자의 전기적인 특성과 신뢰성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the metal wiring forming method of the semiconductor device according to the present invention is used as described above, in order to connect the metal wiring formed under the semiconductor substrate to the upper portion, the buffer layer and the nitride film are sequentially stacked on the substrate and the nitride film is formed. After etching to form a nitride film plug, an insulating film is stacked to form a first contact hole, and the exposed nitride film plug is removed to form a double contact hole connected to the metal wiring of the lower layer by a new double damascene method. Metal layers are stacked to form metal wirings, especially copper wires, thereby eliminating etch-stop during contact, and forming metal wires stably by lowering the dielectric constant of an insulating layer to improve electrical characteristics and reliability of the device. It is a very useful and effective invention.

Claims (8)

반도체소자의 다층 금속배선을 형성하는 방법에 있어서,In the method for forming a multilayer metal wiring of a semiconductor device, 반도체기판의 하부층에 금속배선을 형성한 후 상기 결과물 상에 버퍼층을 적층하는 단계와;Depositing a buffer layer on the resultant after forming a metal wiring on the lower layer of the semiconductor substrate; 상기 단계 후에 버퍼층 상에 질화막을 적층한 후 플러그가 형성될 부위에 감광막을 형성하는 단계와;Stacking a nitride film on the buffer layer after the step, and then forming a photosensitive film on a portion where a plug is to be formed; 상기 단계 후에 질화막을 식각하여 질화막플러그를 형성한 후 이 질화막플러그와 동일한 높이로 버퍼층 상에 절연막을 적층하도록 하는 단계와;Etching the nitride film after the step to form a nitride film plug, and then stacking an insulating film on the buffer layer at the same height as the nitride film plug; 상기 단계 후에 질화막플러그를 개방하는 상태로 감광막을 적층한 후 식각으로 질화막플러그의 일부가 노출되도록 제1콘택홀을 형성하는 단계와;Forming a first contact hole to expose a portion of the nitride film plug by etching after stacking the photoresist with the nitride film plug open; 상기 단계 후에 제1콘택홀로 노출된 질화막플러그를 식각하여 하부층의 금속배선으로 연결되는 제2콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.And etching the nitride film plug exposed through the first contact hole after the step to form a second contact hole connected to the metal wiring of the lower layer. 제 1 항에 있어서, 상기 버퍼층은 실리콘산화막을 이용하고, 500 ∼ 1000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.2. The method of claim 1, wherein the buffer layer is formed to a thickness of 500 to 1000 GPa using a silicon oxide film. 제 1 항에 있어서, 상기 질화막은 15000 ∼ 20000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.The method of claim 1, wherein the nitride film is formed to a thickness of 15000 to 20000 GPa. 제 1 항에 있어서, 상기 질화막을 식각하여 질화막플러그를 형성할 때 건식식각을 이용하여 300 ∼ 700Watt의 전력과, 100 ∼ 200mtorr의 압력으로 진행하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.2. The method of claim 1, wherein when the nitride film is etched to form the nitride film plug, the etching process is performed using a dry etching at a power of 300 to 700 Watts and a pressure of 100 to 200 mtorr. 제 1 항 또는 제 4 항에 있어서, 상기 질화막을 식각하여 질화막플러그를 형성할 때, CHF3가스를 30 ∼ 60 sccm의 유량으로, CF4가스를 10 ∼ 30sccm의 유량으로, Ar가스를 50 ∼100 sccm의 유량으로 공급하여 진행하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.The method of claim 1 or 4, wherein when the nitride film is etched to form a nitride film plug, the CHF 3 gas is flowed at 30 to 60 sccm, the CF 4 gas is flowed at 10 to 30 sccm, and the Ar gas is 50 to 50. A metal wiring forming method for a semiconductor device, characterized in that the supply proceeds at a flow rate of 100 sccm. 제 1 항에 있어서, 상기 제1콘택홀을 형성할 때 절연막을 7000 ∼ 9000Å의 두께로 식각하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.2. The method of claim 1, wherein the insulating film is etched to a thickness of 7000 to 9000 GPa when forming the first contact hole. 제 1 항에 있어서, 상기 제2콘택홀을 형성할 때, 습식식각으로 질화막플러그를 식각하고, 160 ∼ 180℃의 온도범위를 갖는 인산용액으로 식각하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.2. The method of claim 1, wherein when forming the second contact hole, the nitride film plug is etched by wet etching and etched with a phosphoric acid solution having a temperature range of 160 to 180 ° C. . 제 1 항에 있어서, 상기 제2콘택홀을 형성할 때 버퍼층을 블랭킷 건식식각으로 제거하는 것을 특징으로 하는 반도체소자의 금속배선형성방법.The method of claim 1, wherein the buffer layer is removed by blanket dry etching when forming the second contact hole.
KR10-1998-0059279A 1998-12-28 1998-12-28 Metal wiring formation method of semiconductor device_ KR100511092B1 (en)

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KR100821830B1 (en) * 2006-12-26 2008-04-14 동부일렉트로닉스 주식회사 Watermark on low-k layer preventing method for post-cmp cleaning process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100821830B1 (en) * 2006-12-26 2008-04-14 동부일렉트로닉스 주식회사 Watermark on low-k layer preventing method for post-cmp cleaning process

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