KR20000043902A - Method for forming multilayer metal wiring of semiconductor device - Google Patents
Method for forming multilayer metal wiring of semiconductor device Download PDFInfo
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- KR20000043902A KR20000043902A KR1019980060340A KR19980060340A KR20000043902A KR 20000043902 A KR20000043902 A KR 20000043902A KR 1019980060340 A KR1019980060340 A KR 1019980060340A KR 19980060340 A KR19980060340 A KR 19980060340A KR 20000043902 A KR20000043902 A KR 20000043902A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract
Description
본 발명은 반도체 소자의 다층 금속 배선 형성 방법에 관한 것으로, 특히 하부 금속 배선과 상부 금속 배선 사이를 절연시키는 절연층의 유전율을 낮추어 하부 금속 배선과 상부 금속 배선 사이의 인트린직 캐패시티(intrinsic capacity)를 작게하므로써, 소자 동작시 시정수 지연(RC delay)의 감소로 소자의 신뢰성 및 동작 속도를 향상시킬 수 있을 뿐만 아니라, 하부 금속 배선과 상부 금속 배선 사이의 간격을 좁힐 수 있어 소자의 고집적화 및 소형화를 실현할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer metal wiring of a semiconductor device. In particular, the intrinsic capacity between the lower metal wiring and the upper metal wiring is reduced by lowering the dielectric constant of the insulating layer that insulates the lower metal wiring from the upper metal wiring. In addition, by reducing the time delay (RC delay) during device operation, not only can the device improve reliability and operation speed, but also the gap between the lower metal wiring and the upper metal wiring can be narrowed, resulting in high integration and miniaturization of the device. The present invention relates to a metal wiring forming method of a semiconductor device capable of realizing.
일반적으로, 반도체 소자가 고집적화 및 소형화되어 감에 따라 하부 금속 배선과 상부 금속 배선 사이의 간격은 좁아지고 있다. 하부 금속 배선과 상부 금속 배선 사이의 간격이 좁아질 경우 시정수 지연이 증가되고, 이로 인하여 소자의 동작 속도가 느려지는 문제가 있어 반도체 소자의 신뢰성 저하는 물론 소자의 고집적화 및 소형화를 이룰 수 없게 된다.In general, as semiconductor devices become more integrated and miniaturized, the gap between the lower metal wiring and the upper metal wiring becomes smaller. If the distance between the lower metal wiring and the upper metal wiring becomes narrow, the time constant delay is increased, which causes a problem that the operation speed of the device is slowed, thereby lowering the reliability of the semiconductor device and not achieving high integration and miniaturization of the device. .
도 1a 내지 도 1c는 종래 반도체 소자의 다층 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of forming a multilayer metal wiring of a conventional semiconductor device.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 하부 금속 배선(12)을 형성한다. 하부 금속 배선(12)을 포함한 기판(11)상에 층간 절연막(13)을 형성한 후, 층간 절연막(13)의 일부분을 식각 하여 하부 금속 배선(12)의 일부분이 노출되는 다수의 비아 콘택홀(14)을 형성한다.Referring to FIG. 1A, a lower metal wiring 12 is formed on a substrate 11 having a structure in which various elements for forming a semiconductor device are formed. After the interlayer insulating layer 13 is formed on the substrate 11 including the lower metal lines 12, a plurality of via contact holes exposing portions of the lower metal lines 12 are exposed by etching portions of the interlayer insulating layer 13. (14) is formed.
상기에서, 층간 절연막(13)은 주로 산화물(oxide) 계통의 물질을 사용하며, 통상 산화물은 그 유전율이 약 3.9 정도이다.In the above, the interlayer insulating layer 13 mainly uses an oxide-based material, and usually, the oxide has a dielectric constant of about 3.9.
도 1b를 참조하면, 비아 콘택홀(14)을 포함한 층간 절연막(13)상에 장벽 금속층(15) 및 금속층(16)을 순차적으로 형성한다.Referring to FIG. 1B, the barrier metal layer 15 and the metal layer 16 are sequentially formed on the interlayer insulating layer 13 including the via contact hole 14.
도 1c를 참조하면, 금속층(16) 및 장벽 금속층(15)을 패터닝하여 비아 콘택홀(14)을 통해 하부 금속 배선(12)과 연결되는 상부 금속 배선(160)을 형성한다.Referring to FIG. 1C, the metal layer 16 and the barrier metal layer 15 are patterned to form an upper metal line 160 connected to the lower metal line 12 through the via contact hole 14.
상기한 종래의 방법으로 형성된 하부 금속 배선(12)과 상부 금속 배선(160)은 층간 절연막(13)에 의해 전기적으로 절연된다. 이러한 상태에서 소자를 동작하게 되면, 하부 금속 배선(12)과 상부 금속 배선(160) 사이에 인트린직 캐패시티(intrinsic capacity)가 생기게 되는데, 인트린직 캐패시티의 크기는 층간 절연막(13)의 유전율에 따라 달라지게 된다. 그런데, 기존에 사용되는 층간 절연막(13)의 유전율은 약 3.9 정도이기 때문에 반도체 소자가 고집적화 및 소형화되어 감에 따라 시정수 지연(RC delay)을 가져왔다. 이러한 시정수 지연은 반도체 소자에서 중요한 동작 속도 저하를 초래하게 되는 문제가 발생된다.The lower metal wiring 12 and the upper metal wiring 160 formed by the conventional method described above are electrically insulated by the interlayer insulating film 13. In this state, when the device is operated, an intrinsic capacity is generated between the lower metal wiring 12 and the upper metal wiring 160. Will depend on. However, the dielectric constant of the conventional interlayer insulating film 13 is about 3.9, resulting in a time constant delay (RC delay) as the semiconductor device becomes highly integrated and miniaturized. This time constant delay causes a problem that causes a significant decrease in operating speed in the semiconductor device.
따라서, 본 발명은 반도체 소자의 다층 금속 배선 형성 시에 하부 금속 배선과 상부 금속 배선 사이를 절연시키는 절연층의 유전율을 낮추어 하부 금속 배선과 상부 금속 배선 사이의 인트린직 캐패시티(intrinsic capacity)를 작게하므로써, 소자 동작시 시정수 지연(RC delay)의 감소로 소자의 신뢰성 및 동작 속도를 향상시킬 수 있을 뿐만 아니라, 하부 금속 배선과 상부 금속 배선 사이의 간격을 좁힐 수 있어 소자의 고집적화 및 소형화를 실현할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention lowers the dielectric constant of the insulating layer that insulates the lower metal wiring and the upper metal wiring from the formation of the multilayer metal wiring of the semiconductor device, thereby reducing the intrinsic capacity between the lower metal wiring and the upper metal wiring. Therefore, the reliability and operating speed of the device can be improved by reducing the time delay (RC delay) during device operation, and the gap between the lower metal wiring and the upper metal wiring can be narrowed to achieve high integration and miniaturization of the device. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 기판 상에 하부 금속 배선을 형성한 후, 상기 하부 금속 배선을 포함한 기판 상에 식각 정지막을 형성하는 단계; 상기 식각 정지막 상에 트렌치와 비아 콘택홀로 이루어진 다수의 듀얼 다마신 패턴이 형성된 제 1 층간 절연막을 형성하는 단계; 상기 듀얼 다마신 패턴을 포함한 제 1 층간 절연막 상에 장벽 금속층 및 금속층을 형성한 후, 화학 기계적 연마 공정으로 연마하여 상기 비아 콘택홀을 통해 상기 하부 금속 배선과 연결된 다수의 상부 금속 배선을 형성하는 단계; 상기 제 1 층간 절연막을 제거하는 단계; 상기 상부 금속 배선 사이에 에어 갭이 형성된 절연막을 형성하는 단계; 및 상기 절연막을 화학 기계적 연마 공정으로 연마하여 하부 금속 배선과 상부 금속 배선을 전기적으로 절연시키는 제 2 층간 절연막이 형성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal interconnection of a semiconductor device, the method including: forming a lower metal interconnection on a substrate and then forming an etch stop layer on the substrate including the lower metal interconnection; Forming a first interlayer insulating layer having a plurality of dual damascene patterns formed of trenches and via contact holes on the etch stop layer; Forming a barrier metal layer and a metal layer on the first interlayer insulating layer including the dual damascene pattern, and then polishing by a chemical mechanical polishing process to form a plurality of upper metal wires connected to the lower metal wires through the via contact holes. ; Removing the first interlayer insulating film; Forming an insulating film having an air gap formed between the upper metal wires; And polishing the insulating film by a chemical mechanical polishing process to form a second interlayer insulating film electrically insulating the lower metal wiring and the upper metal wiring.
도 1a 내지 도 1c는 종래 반도체 소자의 다층 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a multilayer metal wiring of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 다층 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2F are cross-sectional views of devices for explaining a method of forming a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 기판 12: 하부 금속 배선11: substrate 12: lower metal wiring
13: 층간 절연막 14: 비아 콘택홀13: interlayer insulating film 14: via contact hole
15: 장벽 금속층 16: 금속층15: barrier metal layer 16: metal layer
160: 상부 금속 배선 21: 기판160: upper metal wiring 21: substrate
22: 하부 금속 배선 23: 제 1 식각 정지막22: lower metal wiring 23: first etching stop film
24: 제 1 절연막 25: 제 2 식각 정지막24: first insulating film 25: second etch stop film
26: 제 2 절연막 100: 제 1 층간 절연막26: second insulating film 100: first interlayer insulating film
27: 듀얼 다마신 패턴 27A: 트렌치27: dual damascene pattern 27A: trench
27B: 비아 콘택홀 28: 장벽 금속층27B: Via contact hole 28: Barrier metal layer
29: 금속층 290: 상부 금속 배선29: metal layer 290: upper metal wiring
30: 절연막 31: 에어 갭30: insulating film 31: air gap
300: 제 2 층간 절연막300: second interlayer insulating film
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 다층 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2F are cross-sectional views of devices for describing a method of forming a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(21)상에 하부 금속 배선(22)을 형성한다. 하부 금속 배선(22)을 포함한 기판(21)상에 제 1 식각 정지막(23)을 형성한다. 제 1 식각 정지막(23)상에 제 1 절연막(24), 제 2 식각 정지막(25) 및 제 2 절연막(26)을 형성하여 금속 배선간 절연을 위한 제 1 층간 절연막(100)이 형성되는데, 듀얼 다마신(dual damascene) 공정으로 듀얼 다마신 패턴을 형성하기 위하여, 제 1 식각 정지막(23)상에 제 1 절연막(24) 및 제 2 식각 정지막(25)을 형성한 후, 제 2 식각 정지막(25)의 일부분을 식각하고, 제 2 절연막(26)을 제 2 식각 정지막(25)상에 형성하고, 제 2 절연막(26)의 일부분을 식각 하여 트렌치(27A)를 형성하고, 제 1 절연막(24)의 일부분을 식각 하여 하부 금속 배선(22)의 일부가 노출되는 비아 콘택홀(27B)을 형성하여, 트렌치(27A)와 비아 콘택홀(27B)을 갖는 다수의 듀얼 다마신 패턴(27)이 형성된다.Referring to FIG. 2A, a lower metal wiring 22 is formed on a substrate 21 having a structure in which various elements for forming a semiconductor device are formed. The first etch stop layer 23 is formed on the substrate 21 including the lower metal lines 22. The first insulating film 24, the second etching stop film 25, and the second insulating film 26 are formed on the first etch stop film 23 to form a first interlayer insulating film 100 for insulating between metal wires. In order to form a dual damascene pattern by a dual damascene process, after forming the first insulating film 24 and the second etching stop film 25 on the first etching stop film 23, A portion of the second etch stop layer 25 is etched, a second insulating layer 26 is formed on the second etch stop layer 25, and a portion of the second insulating layer 26 is etched to form the trench 27A. Forming a via contact hole 27B through which a portion of the first insulating film 24 is etched to expose a portion of the lower metal wiring 22 to form a plurality of trenches having a trench 27A and a via contact hole 27B. Dual damascene pattern 27 is formed.
상기에서, 제 1 식각 정지막(23)은 질화물을 증착하여 형성된다. 제 2 식각 정지막(25)은 듀얼 다마신 패턴(27)의 비아 콘택홀(27A) 및 트렌치(27A)를 정의(define)하는 역할을 한다.In the above, the first etch stop layer 23 is formed by depositing nitride. The second etch stop layer 25 defines the via contact hole 27A and the trench 27A of the dual damascene pattern 27.
도 2b를 참조하면, 듀얼 다마신 패턴(27)을 포함한 제 1 층간 절연막(100)상에 장벽 금속층(28) 및 금속층(29)을 순차적으로 형성한다.Referring to FIG. 2B, the barrier metal layer 28 and the metal layer 29 are sequentially formed on the first interlayer insulating layer 100 including the dual damascene pattern 27.
도 2c를 참조하면, 금속층(29) 및 장벽 금속층(28)을 제 1 층간 절연막(100)의 상부면이 노출되는 시점까지 화학 기계적 연마 공정으로 연마하여 듀얼 다마신 패턴(27) 내에 하부 금속 배선(22)과 비아 콘택홀(27B)을 통해 연결된 다수의 상부 금속 배선(290)을 형성한다.Referring to FIG. 2C, the metal layer 29 and the barrier metal layer 28 are polished by a chemical mechanical polishing process until the upper surface of the first interlayer insulating layer 100 is exposed, thereby lowering metal wirings in the dual damascene pattern 27. A plurality of upper metal wires 290 connected to the via 22 and the via contact hole 27B are formed.
도 2d를 참조하면, 제 1 식각 정지막(23)을 식각 장벽으로 하여 듀얼 다마신 공정에 사용된 제 1 층간 절연막(100)을 완전히 제거한다.Referring to FIG. 2D, the first interlayer insulating layer 100 used in the dual damascene process is completely removed using the first etch stop layer 23 as an etch barrier.
도 2e를 참조하면, 상부 금속 배선(290)을 포함한 전체 구조상에 스텝-커버리지(step-coverage) 특성이 나쁜 절연물을 증착하여 절연막(30)을 형성한다. 절연막(30)은 스텝-커버리지 특성이 나쁘기 때문에 상호 근접된 상부 금속 배선(290) 사이에 에어 갭(air gap; 31)이 형성된다.Referring to FIG. 2E, an insulating material having poor step-coverage characteristics is deposited on the entire structure including the upper metal wiring 290 to form an insulating film 30. Since the insulating film 30 has poor step-coverage characteristics, an air gap 31 is formed between the upper metal wires 290 adjacent to each other.
상기에서, 절연막(30)은 플라즈마 증가형 테오스계 산화막(PE-TEOS oxide film)과 고밀도 플라즈마 산화막(HDP oxide film) 등과 같은 스텝-커버리지 특성이 나쁜 산화물로 형성된다. 에어 갭(air gap; 31)은 에어(air)의 유전율이 "1"이기 때문에 층간 절연막으로 주로 사용되는 산화물(oxide) 계통의 물질보다 훨씬 유전율이 낮다. 에어 갭(air gap; 31)은 네거티브 슬롭(negative slop)을 이용하여 제조된다.In the above description, the insulating film 30 is formed of an oxide having poor step-coverage characteristics, such as a plasma-enhanced teos-based oxide film and a high-density plasma oxide film. The air gap 31 is much lower in dielectric constant than an oxide-based material mainly used as an interlayer insulating film because the air permittivity is "1". The air gap 31 is made using negative slops.
도 2f를 참조하면, 화학 기계적 연마 공정으로 상부 금속 배선(290)의 상부면이 노출되는 시점까지 절연막(30)을 연마하여 하부 금속 배선(22)과 상부 금속 배선(290) 사이에 유전율이 낮은 에어 갭(air gap; 31)을 갖는 새로운 제 2 층간 절연막(300)이 형성된다.Referring to FIG. 2F, a dielectric constant is lowered between the lower metal wiring 22 and the upper metal wiring 290 by polishing the insulating film 30 until the upper surface of the upper metal wiring 290 is exposed by a chemical mechanical polishing process. A new second interlayer insulating film 300 having an air gap 31 is formed.
상기한 본 발명의 실시예는 듀얼 다마신(dual damascene)공정으로 층간 절연막에 다수의 듀얼 다마신 패턴을 형성한 후 금속층 증착하고, 화학 기계적 연마 공정으로 금속층을 연마하여 듀얼 다마신 패턴 내에 하부 금속 배선과 비아 콘택홀을 통해 연결된 상부 금속 배선을 형성하고, 듀얼 다마신 공정에 사용된 층간 절연막을 완전히 제거하고, 상부 금속 배선을 포함한 전체 구조상에 스텝-커버리지(step-coverage) 특성이 나쁜 절연물을 증착한 후, 화학 기계적 연마 공정으로 상부 금속 배선의 상부면이 노출되는 시점까지 절연막을 연마하여 하부 금속 배선과 상부 금속 배선 사이에 유전율이 낮은 에어 갭(air gap)을 갖는 새로운 층간 절연막을 형성하여 반도체 소자의 다층 금속 배선을 형성하는 기술로서, 유전율이 낮은 에어 갭에 의해 하부 금속 배선과 상부 금속 배선 사이의 인트린직 캐패시티(intrinsic capacity)가 작아져 소자 동작시 시정수 지연(RC delay)을 감소시킬 수 있어 소자의 신뢰성 및 동작 속도를 향상시킬 수 있을 뿐만 아니라, 하부 금속 배선과 상부 금속 배선 사이의 간격을 좁힐 수 있어 소자의 고집적화 및 소형화를 실현할 수 있다.The embodiment of the present invention described above forms a plurality of dual damascene patterns on an interlayer insulating film by a dual damascene process, and deposits a metal layer, and polishes the metal layer by a chemical mechanical polishing process to form a lower metal in the dual damascene pattern. Form upper metal wires connected through the wiring and via contact holes, completely remove the interlayer insulating film used in the dual damascene process, and insulate poor step-coverage properties over the entire structure, including the upper metal wires. After deposition, the insulating film was polished until the upper surface of the upper metal wiring was exposed by a chemical mechanical polishing process to form a new interlayer insulating film having an air gap having a low dielectric constant between the lower metal wiring and the upper metal wiring. A technique for forming a multi-layered metal wiring of a semiconductor device, the upper metal wiring and the lower metal wiring and the lower metal wiring The intrinsic capacity between the metal wires is reduced to reduce the RC delay during device operation, improving the reliability and operating speed of the device, as well as lower metal wires and upper metal. Since the distance between wirings can be narrowed, high integration and miniaturization of the device can be realized.
상술한 바와 같이, 본 발명은 듀얼 다마신 공법을 이용하여 하부 금속 배선과 상부 금속 배선의 층간 절연 물질로 유전율이 낮은 에어(air; 유전율=1)를 사용하므로써, 기존의 공정에 비해 인트린직 캐패시티의 감소를 가져올 수 있어 시정수 지연의 감소 즉, 소자의 동작 속도 측면에서 우수한 반도체 소자를 얻을 수 있고, 또한 듀얼 다마신 공법을 사용하므로 식각하기 힘든 금속층을 식각할 필요가 없고 식각하기 용이한 절연막을 식각 하면 되기 때문에 공정을 진행하기 용이한 효과가 있다.As described above, the present invention uses a low dielectric constant air (dielectric constant = 1) as the interlayer insulating material of the lower metal wiring and the upper metal wiring using the dual damascene method, thereby reducing the intrinsic capacities compared to the conventional process. It is possible to reduce the city, resulting in the reduction of time constant delay, that is, excellent semiconductor device in terms of operating speed of the device, and the dual damascene method, which eliminates the need to etch and difficult to etch a difficult metal layer. Since the insulating film needs to be etched, the process can be easily performed.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030096484A (en) * | 2002-06-12 | 2003-12-31 | 동부전자 주식회사 | metal pattern structure by dual damascene process of semiconductor device and its manufacturing method |
| KR100574911B1 (en) * | 1999-01-18 | 2006-04-28 | 삼성전자주식회사 | Method for fabricating conductive wiring-layers of semiconductor device |
| KR100668810B1 (en) * | 2000-08-02 | 2007-01-16 | 주식회사 하이닉스반도체 | The method of fabricating metal-line improved rc delay in semiconductor device |
| KR100673238B1 (en) * | 2004-12-28 | 2007-01-22 | 주식회사 하이닉스반도체 | Method of forming a damascene pattern in a semiconductor device |
| KR100782487B1 (en) * | 2006-08-21 | 2007-12-05 | 삼성전자주식회사 | Void-restricting structure, semiconductor devices having the void-restricting structure and methods of forming the same |
| KR100852207B1 (en) | 2007-06-04 | 2008-08-13 | 삼성전자주식회사 | Method of removing an insulator layer and method of forming--metal wire |
| US9343409B2 (en) | 2014-04-07 | 2016-05-17 | Samsung Electronics Co., Ltd. | Semiconductor devices having staggered air gaps |
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| KR101087509B1 (en) * | 2004-06-25 | 2011-11-30 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
Family Cites Families (7)
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| JPH0755969B2 (en) * | 1986-01-31 | 1995-06-14 | 宇部興産株式会社 | Impact-resistant polystyrene resin composition |
| US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
| JP2773729B2 (en) * | 1996-02-29 | 1998-07-09 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2917940B2 (en) * | 1996-11-20 | 1999-07-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3102382B2 (en) * | 1997-05-30 | 2000-10-23 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| KR20000040530A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | Method of forming interlayer insulating film of semiconductor device provide with void between conductive layer patterns |
| KR20000041734A (en) * | 1998-12-23 | 2000-07-15 | 윤종용 | Semiconductor device having multi-layer structure with empty space between wiring and manufacturing method thereof |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100574911B1 (en) * | 1999-01-18 | 2006-04-28 | 삼성전자주식회사 | Method for fabricating conductive wiring-layers of semiconductor device |
| KR100668810B1 (en) * | 2000-08-02 | 2007-01-16 | 주식회사 하이닉스반도체 | The method of fabricating metal-line improved rc delay in semiconductor device |
| KR20030096484A (en) * | 2002-06-12 | 2003-12-31 | 동부전자 주식회사 | metal pattern structure by dual damascene process of semiconductor device and its manufacturing method |
| KR100673238B1 (en) * | 2004-12-28 | 2007-01-22 | 주식회사 하이닉스반도체 | Method of forming a damascene pattern in a semiconductor device |
| KR100782487B1 (en) * | 2006-08-21 | 2007-12-05 | 삼성전자주식회사 | Void-restricting structure, semiconductor devices having the void-restricting structure and methods of forming the same |
| US7956439B2 (en) | 2006-08-21 | 2011-06-07 | Samsung Electronics Co., Ltd. | Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same |
| US8420524B2 (en) | 2006-08-21 | 2013-04-16 | Samsung Electronics Co. Ltd. | Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same |
| KR100852207B1 (en) | 2007-06-04 | 2008-08-13 | 삼성전자주식회사 | Method of removing an insulator layer and method of forming--metal wire |
| US9343409B2 (en) | 2014-04-07 | 2016-05-17 | Samsung Electronics Co., Ltd. | Semiconductor devices having staggered air gaps |
| US9748170B2 (en) | 2014-04-07 | 2017-08-29 | Samsung Electronics Co., Ltd. | Semiconductor devices having staggered air gaps |
| US10141258B2 (en) | 2014-04-07 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having staggered air gaps |
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