JP2012222197A - Semiconductor integrated circuit device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of difficulty in formation of micro wiring due to restriction of processing limitation with reduction of a wiring width or a wiring interval.SOLUTION: A manufacturing method comprises the steps of forming a groove 15 in an insulation layer (first insulation layer 12 and second insulation layer 13), forming a conductive film (barrier film 16 and metal film 17) with a film thickness not to bury the groove 15, and subsequently forming side wall-shape wiring 18 on side walls of the groove 15 by etch back of the conductor film. Accordingly, wiring formation is not subjected to restriction of processing limitation because a wiring width can be controlled based on a film thickness of the conductor film, and predetermined wiring resistance can be maintained by increasing a wiring height.

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a wiring in a semiconductor integrated circuit device and a manufacturing method thereof.

  In a semiconductor integrated circuit device, various wirings are formed in an insulating layer to constitute an integrated circuit, and wiring layers are formed in multiple layers from various semiconductor elements on a semiconductor substrate toward an upper layer.

  A wiring used in a semiconductor integrated circuit is usually formed by forming a conductor film on an insulating layer and processing it into a desired pattern by a photolithography technique and an etching technique. For example, in Patent Document 1, in order to form the wirings 54 to 56 on the silicon oxide film 50 in FIG. 23, first, for example, a thin TiN film by sputtering on the silicon oxide film 50, Al (about 500 nm thick Al ( An aluminum) alloy film and a thin Ti film are deposited, and then a laminated film of the TiN film, the Al alloy film, and the Ti film is dry-etched using the photoresist film as a mask to form wirings 54 to 56.

  As a method for forming wiring, a damascene method is known in which a groove is formed in an insulating layer and a conductor is filled in the groove to form a wiring.

JP 2003-224203 A

  Here, with the miniaturization and high integration of the semiconductor integrated circuit, the wiring width and the wiring interval are also miniaturized, and there is a concern about an increase in resistance. In order to avoid an increase in resistance without increasing the wiring width, it is effective to increase the height of the wiring (thickness) and increase the cross-sectional area. However, in the etching method described in Patent Document 1, it is difficult to process a wiring having a large aspect ratio, and the processing limit is limited.

  In addition, the damascene method of wiring formation is suitable for upper layer wiring with a certain amount of wiring width. However, if the wiring width is made finer and the aspect ratio of the groove to be formed becomes larger, an embedding defect, etc. Cause problems.

According to one embodiment of the present invention,
Forming a groove in the insulating layer;
Forming a conductor film in a film thickness that does not bury the groove;
Etching back the conductor film over the entire surface, forming sidewall-like wiring on both side walls of the groove,
And a method of manufacturing a semiconductor integrated circuit device including a wiring forming process.

Also, according to another embodiment of the present invention,
Processing the insulating layer into a fin-like insulating layer;
Forming a conductor film with a predetermined film thickness covering the fin-like insulating layer;
Etching back the conductor film over the entire surface, forming a wiring in a sidewall shape on both side walls of the fin-like insulating layer,
And a method of manufacturing a semiconductor integrated circuit device including a wiring forming process.

Furthermore, according to another embodiment of the present invention,
A semiconductor integrated circuit device having a wiring formed in an insulating layer,
The wiring consists of a laminate of a barrier film and a metal film,
A semiconductor integrated circuit device is provided in which the barrier film is formed only on the lower surface of the metal film and one side surface in contact with the insulating layer.

  According to an embodiment of the present invention, by leaving a conductor film in a sidewall shape on both side walls of a groove or fin-shaped insulating layer formed in the insulating layer, the wiring height is set to the groove depth or the height of the fin-shaped insulating layer. Since the wiring width can be controlled by the amount of deposited conductor film, a high-aspect wiring can be formed in a self-aligned manner without being restricted by the processing limit.

It is a schematic process sectional drawing explaining the wiring formation process which concerns on one Embodiment of this invention. It is a schematic process sectional drawing explaining the wiring formation process which concerns on another embodiment of this invention. (A) is a top view showing a state after a conductor film is formed in an end groove and etched back, and (b) is a state after a conductor film is formed and etched back covering a plurality of insulating layer fins. FIG. It is a top view which shows the process of removing the conductor film of the both ends of an insulating layer fin from the state of FIG.3 (b). It is process sectional drawing explaining the wiring formation process which concerns on the 1st Example of this invention. It is process sectional drawing which shows the example of formation of the air gap structure which concerns on the 2nd Example of this invention. It is the top view (a) and sectional drawing (b) which show the usage example as a power wire which concerns on the 3rd Example of this invention. It is a conceptual diagram which illustrates a wiring layout.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

  In the present invention, the wiring is basically formed in a sidewall shape on the side wall of the insulating layer to be the support column. The insulating layer to be a support is roughly classified into a case where a groove is formed by the processing method and a method of processing into a convex shape (fin shape).

  FIG. 1 is a schematic process cross-sectional view illustrating a wiring formation process according to an embodiment of the present invention. First, as shown in FIG. 1A, a groove 1 </ b> T is formed in the insulating layer 1. Next, as shown in FIG. 1B, the conductor film 2 is formed to a thickness that does not bury the groove 1T. Finally, the conductor film 2 is etched back. By etching back, the conductor film 2 on the insulating layer 1 and on the bottom surface of the trench 1T is removed, and a sidewall-like wiring 3 is formed on both side walls of the trench 1T.

  FIG. 2 is a schematic process cross-sectional view illustrating a wiring formation process according to another embodiment of the present invention. First, as shown in FIG. 2A, the insulating layer 1 is processed to form insulating layer fins 1F. Next, as shown in FIG. 2B, a conductor film 2 is formed on the entire surface with a predetermined film thickness so as to cover the insulating layer fins 1F. Finally, the conductor film 2 is etched back. By etching back, the conductor film 2 on the insulating layer fins 1F and the insulating layer 1 are removed, and sidewall-like wirings 3 are formed on both side walls of the insulating layer fins 1F.

  By disposing a plurality of insulating layer fins 1F, grooves 1T are formed between the insulating layer fins 1F. In order to reduce the wiring interval, a plurality of insulating layer fins 1F and / or grooves 1T are formed at a narrow pitch, and a sidewall-like wiring is formed by the above method. The wiring width in the present invention depends on the deposition amount (deposited film thickness) of the conductor film. From the wiring width formed by the conventional method, it is below the processing limit by the photolithography technique that is difficult to form by the conventional method. A wide wiring width can be applied. With the reduction of the wiring width, the wiring resistance becomes a problem. In the method according to the present invention, the wiring width can be reduced by controlling the depth of the groove formed in the insulating layer or the height of the insulating layer fin. This can cope with the accompanying increase in wiring resistance. That is, the wiring height is a height that provides a cross-sectional area that satisfies a predetermined wiring resistance with respect to the wiring width.

  As a processing pattern of the insulating layer 1, when a groove 1Ta having an end where the insulating layer 1 remains at the terminal end (longitudinal end portion) of the groove is formed (FIG. 3A), the insulating layer 1 is divided into a plurality of insulating layers 1. In the case of the endless groove 1Tb which is processed into the insulating layer fin 1F, the groove terminates at the end of the insulating layer fin, and becomes open (FIG. 3B). Further, a form in which these end groove 1Ta and endless groove 1Tb are combined is also possible (FIG. 3C). Further, FIG. 3 (c) also shows the case of the groove 1Tc at the end where the insulating layer 1 remains at one end of the groove and the other is open. In either case, the conductor film 2 is connected to form a ring shape in the groove or at both end portions of the insulating layer fin even after the etch back. In order to separate the conductor film formed on both side walls of the groove or the insulating layer fin and divide it into two wirings, it is necessary to further remove the conductor film at both end portions of the groove (both end portions of the insulating layer fin). is there.

  For example, in order to remove the conductor film 2 connected at both end portions of the insulating layer fin 1F as shown in FIG. 3B, both end portions of the insulating layer fin 1F are removed as shown in FIG. A method of removing the exposed conductor film 2 by wet etching, dry etching, or the like (FIG. 4B) may be used. In addition, when two wires are used as a set for a power supply line or the like as in the third embodiment described later, it may be possible to use at least one of both terminal portions connected.

  Note that the side wall of the groove 1T or the insulating layer fin 1F is not limited to the vertical shape as shown in the figure, and the groove 1T or the adjacent insulating layer fin 1F may have a taper shape in which the space between the bottom portion and the upper portion becomes wider. The invention can be applied. In that case, the elevation angle of the side surface in contact with the insulating layer of the formed wiring and the side surface separated by the etch back may be different, and both are included in the category of the present invention.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated concretely, this invention is not limited only to these Examples.

[First Embodiment]
FIG. 5 is a process cross-sectional view illustrating the wiring forming method according to the first embodiment of the present invention. A semiconductor element formed on the semiconductor substrate, an interlayer insulating film covering the semiconductor element, a contact plug for connecting the wiring and the semiconductor element, and the like are formed below the first interlayer insulating film where the wiring is formed. Here, details of the lower layer of the first interlayer insulating film in which the wiring is formed are not shown. Here, the lower layer of the first interlayer insulating film is referred to as a substrate 11.

  First, a silicon oxide film is formed on the substrate 11 as a first insulating film 12 by a known method such as a plasma CVD method. A silicon nitride film is formed on the first insulating film 12 as a second insulating film 13 having etching characteristics different from those of the first insulating film 12 serving as a hard mask by a known method such as a plasma CVD method. Further, a photoresist film 14 is formed on the second insulating film 13 and patterned so as to form a desired groove pattern (FIG. 5A).

  Subsequently, as shown in FIG. 5B, the second insulating film 13 is etched using the photoresist film 14 as a mask to form a first mask pattern 13P having a first pattern. After the remaining photoresist film 14 is removed, the mask pattern 13P is reduced (shrinked) by wet etching using phosphoric acid (FIG. 5C). By shrinking in this way, the mask pattern 13P can be reduced to a width less than the resolution limit. The second insulating film 13 formed in the shrinked second pattern is referred to as a second mask pattern 13P '.

  Next, using the second mask pattern 13P 'as a mask, the first insulating film 12 is etched to form a groove 15 (FIG. 5D). Note that a silicon nitride film serving as an etching stopper is preferably formed on the entire surface of the substrate 11.

  Subsequently, a Ti film, a TiN film, or a laminated film thereof is formed as a barrier film 16 on the entire surface including the inside of the groove 15 by a sputtering method or a CVD method, and a metal film having a film thickness that does not bury the remaining groove 15. Tungsten (W) or aluminum (Al) is deposited as 17 (FIG. 5E).

  Next, as shown in FIG. 5F, the barrier film 16 and the metal film 17 are etched back to expose the second insulating film 13 (second mask pattern 13P '). At the bottom of the trench 15, the barrier film 16 and the metal film 17 on the substrate 11 are similarly removed, and sidewall-like wirings 18 are formed on both side walls of the trench 15. The wiring 18 thus formed is in a state where the barrier film 16 is formed only on one side surface in contact with the lower surface of the metal film 17 and the first interlayer insulating film 12. For example, when wiring of the same width is formed by a conventional damascene method, a barrier film is formed on both sides of the groove, and the ratio of the metal film is reduced. By having it, the proportion of the metal film increases correspondingly, and the resistance becomes lower. In addition, it has been difficult for conventional wiring formation methods to form conductor wiring with a large aspect ratio due to restrictions on processing limits, but in the present invention, conductor wiring with a large aspect ratio is formed without being restricted by processing limits. can do. That is, the height of the conductor film is determined by the height of the first insulating film 2 serving as a support, while the wiring width is determined by the deposited film thickness of the conductor film. Wiring can be formed. Further, the second insulating film 13 serving as a mask as shown in this embodiment can be shrunk by applying a double patterning technique so that the wiring interval can be formed at an interval equal to or less than the processing limit.

  After the etch back, as shown in FIG. 4, the wiring 18 (metal film 17 and barrier film 16) connected at the terminal end of the groove (or insulating layer fin) is selectively removed, so that each groove (insulating layer) The wiring can be separated on both side walls of the fin). By forming an insulating film (third insulating film) between the wirings thus formed and on the wirings, a further upper layer structure can be formed.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  When the wiring height is high and the wiring interval is narrowed, the coupling capacitance between the wirings may become a problem. In order to reduce the coupling capacitance, it is effective to reduce the dielectric constant between the wirings, and it is conceivable to use a low dielectric constant material or the like as the insulating material between the wirings. However, there are problems such as having to clear various factors such as etching characteristics. Therefore, there is a method of providing an air gap instead of using a low dielectric constant material. Literally, the air gap is a technology that realizes the ultimate low dielectric constant by providing a gap (vacuum or predetermined gas (air)) between the wirings.

  In the first embodiment, after the step of FIG. 5 (f), as shown in FIG. 4 (b), the conductive film at the end of the insulating layer fin 1F is removed, and then hydrofluoric acid is used. The silicon oxide film which is the first insulating film 12 is removed by wet etching. Thereby, as shown in FIG. 6A, every other air gap 21 can be formed between the wirings. In addition, as described above, when the silicon nitride film serving as an etching stopper is formed on the surface of the substrate 11 when the groove 15 is formed, the silicon oxide film can be prevented from entering the lower layer of the wet etching solution. Further, since the second insulating film 13 (second mask pattern 13P ′) remains even after the first insulating film 12 is removed, the collapse of the wiring 18 can be suppressed. Subsequently, when the third insulating film 22 is formed between the separated wirings between the grooves, if the film is formed by a high coverage HDP (High-Density Plasma) CVD method, the separated wirings between the grooves are formed. A void serving as the second air gap 23 is also formed therebetween (FIG. 6B).

  As described above, it is possible to reduce the coupling capacity by providing the air gap between the wirings. Note that the air gap may be formed in a region with a narrow wiring interval (wiring dense region) where the coupling capacity is a problem, and does not have to be formed in the entire wiring formation region. When the air gap is partially provided, an opening is formed in the second insulating film 13, and the first insulating film 12 can be removed through the opening.

[Third Embodiment]
Next, a third embodiment will be described.

  The wiring includes a signal line for transmitting a signal and a power supply line for supplying power necessary for the semiconductor device. In the power supply line, more electricity flows than in the signal line, so that a wiring having a lower resistance than the signal line is required. Usually, the cross-sectional area in the current direction is increased, that is, a thick wiring is used. However, since the method of the present invention is a method of forming a fine wiring, there is a case where one wiring is not suitable as a power supply line. Therefore, in the present embodiment example, by using two adjacent wirings as a set, it can be applied as a power supply line. FIG. 7 shows a state in which the two wirings 18A and 18B facing each other in the groove are used as the power supply line 31, and the contact plug 32 is formed on the power supply line 31. The figure (a) is a top view, The figure (b) shows the AA cross section of (a). When the contact is connected on the upper surface of the wiring by shrinking the wiring width, there is a problem that the contact resistance increases. However, in this embodiment, a contact hole is formed between the wirings 18A and 18B, and the two wirings 18A and 18B are connected. Contact resistance can be reduced by making the contact plugs 32 come into contact with the opposing side surfaces. In this way, it is possible to reduce the contact resistance at the same time as reducing the wiring resistance by combining two adjacent wirings.

  In addition to the case where the contact formation part is formed between the wirings facing each other between the grooves as shown in FIG. 7, a contact penetrating the insulating layer fin is provided and formed between the wirings facing each other on both side walls of the insulating layer fin. May be. Further, when the wiring connected at the terminal end of the wiring described in the first embodiment is used as it is as a power supply line without being separated, a contact may be formed at the terminal end. If the contact is formed inside the wiring terminal portion, the contact plug and the wiring come into contact with each other on three surfaces, and the contact resistance can be further reduced. Further, the contact resistance can also be reduced by forming the wiring end portion over the inside and outside. Even when a contact plug is formed on a single wiring, the contact resistance can be similarly reduced by connecting the contact plug across one or both of the side walls.

  Furthermore, as shown on the right side of FIG. 3C, it is possible to use a wiring surrounding a plurality of wirings in a ring shape and use it as a power supply line.

  In the above description, an example in which the wiring is formed in a straight line is shown. However, the wiring is not limited to a straight line, and a curved or bent wiring can be formed. For example, a bit wiring of a DRAM may form a bent wiring avoiding a capacitor contact, but the wiring according to the present invention can also be applied to such a bent wiring. Further, the interval between the wirings depending on the groove width or the insulating layer fin width does not need to be constant, and as shown in FIG. 8, the groove width, The insulating layer fin width or both widths may be increased. FIG. 8 shows an example in which two opposing wires are used as the power supply line 41 and the signal line 42 is arranged around the two wires. A black circle indicates a contact portion.

1 Insulating Layer 1T Groove 1Ta Ended Groove 1Tb Endless Groove 1Tc End End Groove 1F Insulating Layer Fin 2 Conductor Film 3 Wiring 4 Resist 11 Substrate 12 First Insulating Film 13 Second Insulating Film 13P First Mask Pattern 13P 'Second mask pattern 14 Photoresist 15 Groove 16 Barrier film 17 Metal film 18 Wiring 21 First air gap 22 Third insulating film 23 Second air gap 31 Power line 32 Contact plug 41 Power line 42 Signal line

Claims (20)

Forming a groove in the insulating layer;
Forming a conductor film in a film thickness that does not bury the groove;
Etching back the conductor film over the entire surface, forming sidewall-like wiring on both side walls of the groove,
A method for manufacturing a semiconductor integrated circuit device, comprising a wiring formation step comprising:   The insulating layer is a stack of a second insulating film having a different etching characteristic from the first insulating film on the first insulating film, and the step of forming the groove includes forming a groove pattern on the second insulating film. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: a step of transferring the first insulating film, and a step of etching the first insulating film using the patterned second insulating film as a mask.   In the step of transferring the groove pattern to the second insulating film, the second insulating film is processed into a first pattern by using a photolithography technique, and then the first pattern is reduced to reduce the second pattern. The method of manufacturing a semiconductor integrated circuit device according to claim 2, comprising a step of processing the semiconductor integrated circuit device.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of removing a conductive film at least one end portion of the groove after the conductive film is etched back. 5.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the conductor film is a step of forming a metal film after forming a barrier film on the entire surface.   6. The semiconductor integrated circuit according to claim 1, further comprising a step of forming a first air gap by removing at least a part of an insulating layer remaining between the trenches after forming the wiring. A method of manufacturing a circuit device. Processing the insulating layer into a fin-like insulating layer;
Forming a conductor film with a predetermined film thickness covering the fin-like insulating layer;
Etching back the conductor film over the entire surface, forming a sidewall-like wiring on both side walls of the fin-like insulating layer,
A method for manufacturing a semiconductor integrated circuit device, comprising a wiring formation step comprising:   8. The semiconductor integrated circuit device according to claim 7, wherein a plurality of the fin-like insulating layers are formed, and the step of forming the conductor film is a step of forming a film thickness that does not bury a gap between the adjacent fin-like insulating layers. Manufacturing method.   The insulating layer is a stack of a second insulating film having etching characteristics different from that of the first insulating film on the first insulating film, and the step of forming the fin-shaped insulating layer includes the step of forming the second insulating film. 9. The semiconductor integrated circuit device according to claim 7, further comprising: transferring a fin-like insulating layer pattern to the substrate; and etching the first insulating film using the patterned second insulating film as a mask. Production method.   The step of transferring the fin-like insulating layer pattern to the second insulating film is performed by processing the second insulating film into a first pattern by using a photolithography technique, and then reducing the first pattern to reduce the first pattern. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising a step of processing into two patterns.   11. The method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising a step of removing a conductor film at at least one end portion of the fin-like insulating layer after the conductor film is etched back.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the step of forming the conductor film is a step of forming a metal film after forming a barrier film on the entire surface.   13. The method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising a step of forming an air gap by removing at least a part of the fin-like insulating layer after the wiring forming step. .   After the step of forming the wiring, the method further includes a step of forming a third insulating layer that covers the wiring, and when forming the third insulating layer, the second insulating layer is inserted between the wirings in which the third insulating layer is embedded. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed so as to have a void serving as an air gap.   After the wiring formation step, a step of forming a third insulating layer that covers the wiring, and a contact that exposes at least a part of at least opposing side surfaces of two adjacent wirings in the third insulating layer 15. The method according to claim 1, further comprising a step of forming a hole and a step of filling the contact hole with a conductor to form a contact plug, wherein two wirings connected to one contact plug are used as power supply lines. A method for manufacturing a semiconductor integrated circuit device according to any one of the preceding claims. A semiconductor integrated circuit device having a wiring formed in an insulating layer,
The wiring consists of a laminate of a barrier film and a metal film,
The semiconductor integrated circuit device, wherein the barrier film is formed only on a lower surface of the metal film and one side surface in contact with the insulating layer.   17. The wiring according to claim 16, wherein the wiring has a width that is equal to or less than a processing limit by a photolithography technique, and the wiring height has a cross-sectional area that satisfies a predetermined wiring resistance with respect to the wiring width. Semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 16, wherein the wiring includes a ring-shaped wiring connected at both terminal ends of two wirings.   19. The device according to claim 16, wherein a plurality of the wirings are provided, a power supply line is configured by combining two adjacent wirings, and a contact plug connected to opposite side surfaces of the two wirings constituting the power supply line is provided. The semiconductor integrated circuit device according to any one of the above.   The semiconductor integrated circuit device according to claim 16, wherein a plurality of the wirings are provided and an air gap is provided between the wirings.