JP2015061032A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high speed of a semiconductor device by reducing parasitic capacitance between neighboring interconnections and between neighboring via plugs.SOLUTION: A semiconductor device comprises: a first interconnection (3) arranged on a semiconductor substrate (1); a via plug (20B) in which a via hole (9) connected to a top face of the first interconnection (3) is buried; and a second interconnection (20A) in which a trench (7) which is connected to a top face of the via plug (20B) and extends in a first direction (X) is buried. The semiconductor device comprises trench air gaps (11a, 11b) which are arranged on two lateral faces (5a, 5b), respectively, which compose the trench (7), and via air gaps (11a, 11b, 11c, 11d) which are arranged on lateral faces (4a, 4b, 4c, 4d), respectively, which compose the via hole (9).

Description

  The present invention relates to a semiconductor device having a wiring structure and a manufacturing method thereof, and more particularly to a semiconductor device having a damascene wiring structure and a manufacturing method thereof.

  2. Description of the Related Art In recent years, a multilayer wiring structure as disclosed in Patent Document 1 is used in a semiconductor device with high integration. In addition, the trend toward miniaturization and miniaturization is being accelerated. However, this miniaturization and miniaturization leads to narrowing of the wiring interval, and causes a problem of increasing the existing capacity between the wirings and increasing the signal delay.

  In order to cope with this problem of signal delay, Patent Document 2 discloses a method of forming a cavity between electrodes or wiring layers for the purpose of reducing parasitic capacitance between wirings. Since the cavity has a lower relative dielectric constant than the insulating film that is a solid material, it can contribute to the reduction of the parasitic capacitance of the wiring.

  Further, in order to cope with a demand for high-speed operation of a semiconductor device, a copper dual damascene method in which low resistance copper (Cu) is used for wiring and a via plug connected to a lower layer wiring and a wiring arranged on the via plug are simultaneously formed. Is used. The Cu dual damascene method includes a via first method in which a via hole in which a via plug is embedded is formed first, and a trench first method in which a wiring groove (trench) in which a wiring is embedded is formed first. Patent Document 3 discloses an example of the via first method, and Patent Document 4 discloses an example of the trench first method.

JP 2006-210648 A JP 2006-135069 A JP 2006-41519 A JP 2009-283812 A

  In the method described in Patent Document 2, when an insulating film having poor step coverage is formed on a wiring after forming the adjacent wiring extending in the same direction, the upper space between the adjacent wirings is blocked by the insulating film. As a result, a phenomenon in which a cavity is generated inside the wiring is used. In the method of Patent Document 2, a cavity can be formed between wirings with a small interval, but there is a wiring pattern dependency that a cavity cannot be formed between wirings with a large interval. There was a problem that could not be formed. Further, the method of Patent Document 2 has a problem that it cannot be applied to the Cu dual damascene structure described in Patent Document 3.

  A semiconductor device according to a first aspect includes a first wiring disposed on a semiconductor substrate, a via plug burying a via hole connected to the upper surface of the first wiring, and an upper surface of the via plug connected in the first direction. A second wiring for burying an existing trench, and a trench air gap disposed on each of two side surfaces constituting the trench, and a via air gap disposed on a side surface constituting the via hole. It has a configuration.

  In another aspect, a semiconductor device includes: a first wiring disposed on a semiconductor substrate; a via plug embedded in a via hole connected to an upper surface of the first wiring; and a first plug connected to the upper surface of the via plug and extending in a first direction. A second wiring for burying the trench, a trench air gap disposed on each of two side surfaces constituting the trench, and a via air gap disposed on the side surface constituting the via hole, At least a part of the trench air gap arranged at the side and at least a part of the via air gap arranged at the side surface of the via hole have a configuration that is flush with the vertical direction.

  The method for manufacturing a semiconductor device includes a step of forming a first wiring and a first interlayer insulating film on a semiconductor substrate, and a step of sequentially forming a second interlayer insulating film and a third interlayer insulating film on the first wiring. And forming a trench in the third interlayer insulating film and forming a via hole in the second interlayer insulating film, and forming a trench in the third interlayer insulating film and forming a via hole in the second interlayer insulating film. The step of forming includes a step of forming such that at least a part of the side surface of the trench and at least a part of the side surface of the via hole are flush with each other.

  According to the present invention, in the damascene structure wiring, the air gap is arranged on both the side surface of the wiring in which the trench is embedded and the side surface of the via plug in which the via hole located under the trench is embedded. it can. Thereby, the parasitic capacitance between adjacent wirings and between adjacent via plugs can be reduced, and the semiconductor device can be operated at high speed. In addition, since the air gap associated therewith can be arranged in contact with the wiring and the via plug itself, the air gap can be formed for any wiring pattern without depending on the layout of the wiring pattern.

1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention. (A), (b), and (c) are A-A 'sectional drawing, B-B' sectional drawing, and C-C 'sectional drawing in FIG. 1, respectively. (A), (b), (d) respectively show the 1st wiring formation process, the interlayer insulation film formation process, and the trench formation process of the manufacturing method of the semiconductor device in 1st Embodiment of this invention, FIG. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1, a cross-sectional view taken along line BB ′ of FIG. (A), (b), (c), and (d) are respectively AA of FIG. 1 showing the first step of the via hole forming step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view, a cross-sectional view taken along the line BB ′ of FIG. 1, a cross-sectional view taken along the line CC ′ of FIG. (A), (b), (c), and (d) each show a second step of the via hole forming step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view, a cross-sectional view taken along the line BB ′ of FIG. 1, a cross-sectional view taken along the line CC ′ of FIG. (A), (b), (c), and (d) each show a third step of the via hole forming step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view, a cross-sectional view taken along the line BB ′ of FIG. 1, a cross-sectional view taken along the line CC ′ of FIG. (A), (b), (c), and (d) are each AA in FIG. 1 showing a fourth step of the via hole forming step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view, a cross-sectional view taken along the line BB ′ of FIG. 1, a cross-sectional view taken along the line CC ′ of FIG. (A), (b), (c), and (d) each show a fifth step of the via hole forming step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view, a cross-sectional view taken along the line BB ′ of FIG. 1, a cross-sectional view taken along the line CC ′ of FIG. FIGS. 1A and 1B are cross-sectional views taken along the line AA ′ of FIG. 1, showing a first step of the sidewall film forming step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, respectively. It is BB 'sectional drawing of. FIGS. 1A and 1B are cross-sectional views taken along the line AA ′ of FIG. 1, showing a second step of the sidewall film forming process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. It is BB 'sectional drawing of. FIGS. 1A and 1B are cross-sectional views taken along line AA ′ of FIG. 1, respectively, illustrating a first step of a first via plug and a second wiring forming process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a sectional view taken along the line BB ′ in FIG. FIGS. 1A and 1B are cross-sectional views taken along line AA ′ of FIG. 1, respectively, showing a second step of a first via plug and a second wiring forming process of the semiconductor device manufacturing method according to the first embodiment of the present invention. FIG. 2 is a sectional view taken along the line BB ′ in FIG. (A), (b) is the AA 'cross section figure of FIG. 1, and the BB' cross section of FIG. 1 which shows the air gap formation process of the manufacturing method of the semiconductor device in 1st Embodiment of this invention, respectively. FIG. FIGS. 1A and 1B are cross-sectional views taken along line AA ′ of FIG. 1 and BB ′ of FIG. 1, respectively, illustrating a cap insulating film forming step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. It is sectional drawing. FIGS. 1C and 1D show the first step of the second via plug and third wiring formation step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, respectively, respectively. It is C 'sectional drawing and a top view. FIGS. 1C and 1D show the second step of the second via plug and the third wiring forming step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, respectively. It is C 'sectional drawing and a top view. As a comparative example of the first embodiment of the present invention, the dual damascene structure disclosed in Patent Document 3 is used, and is a bird's eye view at a stage where a sidewall film is formed. It is a bird's-eye view of the stage in which the sidewall sacrificial film was formed of the semiconductor device concerning a 2nd embodiment of the present invention. (A), (b) is a figure which shows typically the example of a trench first method and the via first method in the case of using a separate hole pattern for the formation mask of a 1st via hole, respectively. It is a top view which shows the structure of the semiconductor device which concerns on 3rd Embodiment of this invention.

  In the following drawings, the scale and number of each structure are different from each other in order to make each configuration easy to understand. In addition, an XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the semiconductor substrate, the X direction is a direction perpendicular to the Z direction in a plane parallel to the surface of the semiconductor substrate, and the Y direction is horizontal to the surface of the semiconductor substrate. This is a direction orthogonal to the X direction on a smooth surface. Thus, the Y direction and the X direction are orthogonal to each other. The X direction is also called the first direction, the Y direction is also called the second direction, and the Z direction is also called the third direction.

[First Embodiment]
A first embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment, based on the Cu dual damascene method using the trench first method, an air gap (air gap) is formed on both the side surface of the wiring buried in the trench and the side surface of the via plug buried in the via hole. Hereinafter, a semiconductor device having a wiring structure having AG and a manufacturing method thereof will be described.

  First, the semiconductor device of the first embodiment will be described with reference to the plan view of FIG. 1 and the cross-sectional view of FIG.

  2A, 2B, and 2C correspond to the A-A 'cross-sectional view, B-B' cross-sectional view, and C-C 'cross-sectional view in FIG. 1, respectively.

  A first interlayer insulating film 2 made of a silicon oxide film and a second interlayer insulating film 4 are embedded on a semiconductor substrate 1 on which a semiconductor element such as a transistor is formed and extend in the Y direction (second direction). 1 wiring 3 is provided. The first wiring 3 is a lower layer wiring and is made of tungsten (W), Cu, aluminum (Al), or the like. The first wiring 3 may be a contact plug with a lower layer conductor. On the first wiring 3, for example, a second interlayer insulating film 4 having a thickness of 50 nm is disposed. Further, a third interlayer insulating film 5 made of, for example, a silicon oxide film having a thickness of 100 nm is disposed on the second interlayer insulating film 4. As the second interlayer insulating film 4, a silicon oxynitride film (SiON film) or a silicon carbonitride film (SiCN film) that can ensure etching selectivity with respect to the silicon oxide film constituting the third interlayer insulating film 5 is used. . Further, an impurity-containing silicon oxide film such as a BPSG film that enables detection of the etching end point of the third interlayer insulating film 5 may be used.

  The third interlayer insulating film 5 is provided with a wiring groove (hereinafter referred to as a trench) 7 extending in the X direction (first direction) perpendicular to the Y direction. 20A is buried. A via hole 9 extending in the Z direction (third direction) in contact with the bottom surface of the trench 7 and connected to the upper surface of the first wiring 3 is disposed, and a first via plug 20B is embedded in the via hole 9. By the first via plug 20B, the second wiring 20A and the first wiring 3 located in the lower layer are connected. The second wiring 20A and the first via plug 20B are arranged in an integrated configuration, and both are configured by laminating a Cu film 20b on the Cu diffusion barrier film 20a. The second wiring 20A and the first via plug 20B may be made of aluminum.

  A cap insulating film 12 is disposed on the upper surfaces of the second wiring 20 </ b> A and the third interlayer insulating film 5. A second via plug 13 connected to the upper surface of the second wiring 20A is disposed in the cap insulating film 12 located on the second wiring 20A. Further, a third wiring 14 connected to the upper surface of the second via plug 13 is disposed. The second via plug 13 and the third wiring 14 can be configured by an integrated aluminum wiring. Further, similarly to the second wiring 20A, a combination of a Cu diffusion barrier and a Cu wiring may be used. Thus, a multilayer wiring structure including the first wiring 3, the second wiring 20A, and the third wiring 14 is configured.

  In the above configuration, as shown in FIG. 1 and FIGS. 2A and 2C, the trench 7 in which the second wiring 20 </ b> A is embedded and extends in the X direction has the first side surface 5 a and the second side facing each other in the Y direction. It has a side surface 5b. The width W2 of the trench 7 in the Y direction, that is, the distance between the first side surface 5a and the second side surface 5b is 60 nm. A first air gap (AG) 11a is disposed between the first side surface 5a and the second wiring 20A. Further, a second air gap (AG) 11b is disposed between the second side surface 5b and the second wiring 20A.

  The combination of the first AG 11a and the second AG 11b, which are respectively disposed on the two side surfaces 5a and 5b constituting the trench 7, is also called a trench air gap.

  On the other hand, as shown in FIG. 1 and FIGS. 2A and 2B, the via hole 9 in contact with the bottom surface of the trench 7 is formed in the X direction with the via first side surface 4a and the via second side surface 4b opposed to the Y direction. Opposing via third side surface 4c and via fourth side surface 4d are provided. The first side surface 5a and the first via side surface 4a are flush with each other. Further, the second side surface 5b and the via second side surface 4b also constitute a continuous side surface. As described above, the semiconductor device according to the first embodiment has the trench 7 and the via hole 9 extending in contact with the bottom surface of the trench 7, and at least a part of the side surface constituting the trench 7 has the via hole 9. One of the features is that a side surface that is continuous with at least a part of the side surface is configured. As a result, the air gap (AG) disposed between the via first side surface 4a and the first via plug 20B is included in the first AG 11a, and the air gap disposed between the via second side surface 4b and the first via plug 20B ( AG) is included in the second AG 11b.

  Corresponding third air gap (AG) 11c and fourth air gap (AG) 11d are arranged in via third side surface 4c and via fourth side surface 4d, respectively. The first AG 11a, the third AG 11c, the second AG 11b, and the fourth AG 11d located around the via hole 9 are connected to each other at a corner portion in plan view of the via hole 9 to form one ring-shaped air gap (AG). The width in the Y direction of each of the first AG 11a and the second AG 11b and the width in the X direction of each of the third AG 11c and the fourth AG 11d are all configured to have the same width. Here, the width is, for example, 10 nm.

  A combination of the first to fourth AGs 11a, 11b, 11c, and 11d disposed on the side surfaces 4a, 4b, 4c, and 4d constituting the via hole 9 is also referred to as a via air gap.

  As described above, the first side surface 5a of the trench 7 and the via first side surface 4a of the via hole 9 are disposed so as to overlap in plan view, and the second side surface 5b of the trench 7 and the via second side surface 4b of the via hole 9 are also viewed in plan view. It is arranged at the overlapping position. Therefore, the width W2 of the via hole 9 in the Y direction is equal to the width W2 of the trench 7 in the Y direction and is 60 nm. The position of the via hole 9 in the Y direction is aligned with the position of the trench 7 in the Y direction. The width W3 in the X direction of the via hole 9, that is, the interval between the via third side surface 4c and the via fourth side surface 4d is 60 nm.

  As shown in FIG. 1, the width W1 of the first wiring 3 in the X direction is configured to be larger than the width W3 of the via hole 9 in the X direction. Here, it is 80 nm. As a result, the via hole 9 can be arranged in the first wiring 3 without protruding from the end portion in the X direction on the upper surface of the first wiring 3 in a plan view even in consideration of a margin of lithography pattern overlay accuracy. .

  Thus, in the semiconductor device of the first embodiment, the first wiring (3) disposed on the semiconductor substrate (1) and the via plug (9) connected to the upper surface of the first wiring (3) are embedded. (20B) and a second wiring (20A) for burying a trench (7) that is connected to the upper surface of the via plug (20B) and extends in one direction, and two side surfaces that constitute the trench (7) ( 5a, 5b) and the via air gaps (11a, 11b, 11c) disposed on the side surfaces (4a, 4b, 4c, 4d) constituting the via holes (9). 11d).

  In other words, the semiconductor device of the first embodiment includes a first wiring (3) disposed on the semiconductor substrate (1) and a via hole (9) connected to the upper surface of the first wiring (3). A via plug (20B) to be buried, a second wiring (20A) to bury a trench (7) connected to the upper surface of the via plug (20B) and extending in one direction, and two side surfaces (5a) constituting the trench (7) , 5b) and via air gaps (11a, 11b, 11c, 11d) arranged on the side surfaces (4a, 4b, 4c, 4d) constituting the via holes (9). ), And at least part of the trench air gap (11a, 11b) disposed on the side surface (5a, 5b) of the trench (7), and the side surface (4a, 4b, 4c, 4d) of the via hole (9) In Via an air gap which is location (11a, 11b, 11c, 11d) and at least a portion of, it is composed of flush in the vertical direction.

  As described above, the semiconductor device according to the first embodiment includes the second wiring 20A and the first via plug 20B continuous below the second wiring, and the two side surfaces 5a and 5b of the second wiring 20A. Since the AG is disposed on any of the four side surfaces 4a, 4b, 4c, and 4d of the first via plug 20B, the parasitic capacitance of the wiring caused between the adjacent wirings and between the adjacent via plugs can be reduced. This can contribute to high speed operation. In the first embodiment, since the AG is arranged along with the side surface of the wiring itself, the AG can be arranged in any wiring without being restricted by the wiring layout pattern.

  In the first embodiment, the via hole 9 is shown as a rectangular pattern in plan view. However, the present invention is not limited to this, and the via hole 9 can be similarly configured even in a circular pattern in plan view.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. In each figure, (a) is a cross-sectional view taken along line AA ′ of FIG. 1, (b) is a cross-sectional view taken along line BB ′ of FIG. 1, and (c) is a cross-sectional view taken along line CC ′ of FIG. ing. FIG. 4D shows a plan view of the corresponding process.

(First wiring formation process)
First, a first wiring forming process is performed to be a lower layer wiring to which a via plug is connected.

  As shown in FIGS. 3A and 3B, a first interlayer insulating film 2 is formed on a semiconductor substrate 1 on which a semiconductor element such as a transistor is formed. For example, a silicon oxide film (SiO film) is used for the first interlayer insulating film 2. The semiconductor substrate 1 is a silicon single crystal substrate, but is not limited to this. A first wiring 3 extending in the Y direction (second direction) and having a width in the X direction (first direction) perpendicular to the Y direction is formed in the first interlayer insulating film 2. W1 is, for example, 80 nm. The first wiring 3 is not limited to an aluminum wiring or a Cu wiring, but may be a contact plug made of a tungsten (W) film or a silicon film. Further, the first wiring 3 may be the semiconductor substrate 1 itself. The first wiring 3 is not particularly limited in thickness, planar shape, or the like.

(Interlayer insulation film formation process)
Next, an interlayer insulating film forming step is performed.

  As shown in FIG. 3A, a second interlayer insulating film 4 having a thickness of, for example, 50 nm and a third interlayer having a thickness of, for example, 150 nm are formed on the upper surface of the first wiring 3 and the upper surface of the first interlayer insulating film 2. The insulating film 5 is sequentially stacked.

  For example, a silicon oxynitride film (SiON film) is used as the second interlayer insulating film 4. As the second interlayer insulating film 4, a silicon carbonitride film (SiCN film) or the like can be used in addition to the SiON film. The second interlayer insulating film 4 can be made of an impurity-containing silicon oxide film (BPSG) such as boron or phosphorus. The second interlayer insulating film 4 is preferably made of a material that can be left when the third interlayer insulating film 5 is etched in a wiring trench (trench) forming process described later. That is, the second interlayer insulating film 4 is preferably a material that can ensure an etching selectivity relative to the third interlayer insulating film 5 or can detect the etching end point of the third interlayer insulating film 5.

  For example, a silicon oxide film (SiO) is used for the third interlayer insulating film 5. The third interlayer insulating film 5 may be made of a low dielectric constant material having a dielectric constant lower than that of the silicon oxide film. When the third interlayer insulating film 5 is composed of an SiO film, the SiON film, SiCN film, BPSG film, etc. used as the second interlayer insulating film 4 contain elements not contained in the third interlayer insulating film 5. Yes. Therefore, the etching end point of the third interlayer insulating film 5 can be detected by monitoring the plasma emission caused by these elements, and the second interlayer insulating film 4 can be left. In addition, the SiON film, the SiCN film, and the like can ensure etching selectivity with respect to the SiO film.

(Trench formation process)
Next, a trench forming step for forming a trench in the third interlayer insulating film 5 is performed.

  First, as shown in FIGS. 3A and 3D, a first mask film 6 is formed on the upper surface of the third interlayer insulating film 5. The first mask film 6 is composed of a first photosensitive organic film (first photoresist film) formed in the uppermost layer in addition to the first antireflection film (first BARC film), the first Si-containing organic film, and the like. In addition, the first mask film 6 may include an inorganic hard mask film made of Si or the like.

  Next, as shown in FIGS. 3A and 3D, the first mask film 6 extends in the X direction and the width W2 in the Y direction becomes 60 nm, for example, by lithography and anisotropic dry etching. A trench pattern 6a is formed. The trench pattern 6a is formed such that the entire width W2 overlaps the upper surface of the first wiring 3 extending in the X direction.

  Next, as shown in FIGS. 3A, 3B, and 3D, the third interlayer insulating film 5 is etched by anisotropic dry etching using fluorine-containing plasma using the trench pattern 6a as a mask. . As a result, a trench 7 is formed which has a first side surface 5a and a second side surface 5b made of the third interlayer insulating film 5 facing each other in the Y direction and extending in the X direction. The trench 7 becomes a wiring groove in which wiring is embedded in a process described later. The upper surface of the second interlayer insulating film 4 is exposed at the bottom surface of the trench 7.

  Next, the first mask film 6 is removed.

(Via hole formation process)
Next, a via hole forming step is performed which continues below the trench 7 and connects to the upper surface of the first wiring 3.

  First, as shown in FIGS. 4A, 4 </ b> B, and 4 </ b> C, the inside of the trench 7 is buried, and the second BARC film 8 (trench buried film 8) that covers the upper surface 51 of the third interlayer insulating film 5 is rotated. It is formed by a coating method. The upper surface 81 of the second BARC film 8 is formed so as to be 0 to 50 nm higher than the upper surface 51 of the third interlayer insulating film 5.

  Next, as shown in FIGS. 4B and 4C, a second Si-containing organic film 8a and a second photoresist film 8b to be the second mask film 8c are sequentially stacked on the upper surface of the second BARC film 8. A first via hole pattern 8A is formed in the second photoresist film 8b by lithography.

  As shown in FIG. 4D, the first via hole pattern 8A of the first embodiment is formed across at least the first side surface 5a and the second side surface 5b of the trench 7 extending in the X direction. is necessary. For this reason, here, the first via hole pattern 8A is formed in a line pattern extending across the plurality of trenches 7 arranged in the Y direction. By forming the first via hole pattern 8A as a line pattern in the Y direction perpendicular to the extending direction of the trench 7, both the first side surface 5a and the second side surface 5b are surely positioned in the first via hole pattern 8A. It becomes.

  The first via hole pattern 8A is not limited to the line pattern, and may be formed as an individual rectangular pattern including the trench 7 at the center in the Y direction and straddling the first side surface 5a and the second side surface 5b.

  The first via hole pattern 8A is formed so that the width W3 in the X direction is smaller than the width W1 in the X direction of the first wiring 3 in the lower layer, and overlaps at a position that does not protrude from the width W1 in the X direction of the first wiring. Formed. Thereby, a via hole to be described later is connected to the upper surface of the first wiring 3 and can be prevented from being formed protruding from the upper surface of the first wiring 3. Here, the width W3 of the first via hole pattern 8A is set to 60 nm.

  Next, using the second photoresist film 8b as a mask, the second Si-containing organic film 8a is anisotropically dry-etched to transfer the first via hole pattern 8A to the second Si-containing organic film 8a. Thereby, as shown in FIGS. 4A, 4B, 4C, and 4D, a second mask film pattern 8A that is the first via hole pattern 8A is formed, and the second BARC film is included in the pattern. The upper surface of 8 is exposed.

  Next, as shown in FIGS. 5A, 5B, 5C, and 5D, the second BARC film 8 exposed in the first via hole pattern 8A is anisotropically dried using oxygen-containing plasma. Etching is performed by an etching method to form the second via hole pattern 8B. In the oxygen-containing plasma, organic films such as the second photoresist film 8b and the second BARC film 8 are etched, but inorganic films such as a silicon oxide film constituting the third interlayer insulating film 5 and the second interlayer insulating film 4 are etched. Not. Also, the second Si-containing organic film 8a is not etched.

  Therefore, when the anisotropic dry etching method using the oxygen-containing plasma is performed, only the second BARC film 8 in the first via hole pattern that is not covered with the second Si-containing organic film 8a is selectively removed. The As a result, the second BARC film 8 that has buried the trench 7 is removed, and the upper surface of the second interlayer insulating film 4 is exposed in the trench 7. Further, the upper surface of the third interlayer insulating film 5 is exposed between the trenches 7 adjacent in the Y direction.

  Therefore, as shown in FIG. 5D, the second via hole pattern 8B is opposed to the first side surface 5a and the second side surface 5b made of the third interlayer insulating film 5 in the Y direction, and is opposed to the second BARC in the X direction. A hole pattern having a rectangular shape in plan view partitioned by the third side surface 8d and the fourth side surface 8e made of the film 8 is obtained.

  Next, as shown in FIGS. 6A, 6B, 6C, and 6D, the second Si-containing organic film 8a is removed. Further, the upper surface of the second BARC film 8 is etched back. As a result, as shown in FIGS. 6C and 6D, the upper surface 51 of the third interlayer insulating film 5 located in a region other than the first via hole pattern 8A is exposed. The trench 7 located in a region other than the second via hole pattern 8B is buried with the second BARC film 8.

  Next, as shown in FIGS. 7A, 7B, 7C and 7D, the third interlayer insulating film 5 and the second BARC film 8 are used as a mask to be exposed in the second via hole pattern 8b. The second interlayer insulating film 4 is etched. This etching is performed by anisotropic dry etching using fluorine-containing plasma. At this time, the third interlayer insulating film 5 made of a silicon oxide film is also etched at the same time.

  If the upper surface 51 of the third interlayer insulating film 5 located in a region other than the first via hole pattern 8A is not exposed at the stage of FIG. 6, the third inner hole located inside and outside the first via hole pattern 8A is consequently obtained. An etching step occurs in the interlayer insulating film 5, which hinders subsequent process execution. However, in the first embodiment, since the upper surface of the third interlayer insulating film 5 is exposed over the entire surface in the stage of FIG. 6, the entire surface is etched at the same time, and no etching step is generated.

  Thereby, the second interlayer insulating film 4 located in the second via hole pattern 8B is etched to form the via hole 9. The via hole 9 is formed in the second interlayer insulating film 4, and includes a via first side surface 4a and a via second side surface 4b facing in the Y direction, a via third side surface 4c and a via fourth side surface 4d facing in the X direction, It is a rectangular hole in plan view partitioned by The via first side surface 4 a coincides with the first side surface 5 a of the trench 7, and the via second side surface 4 b coincides with the second side surface 5 b of the trench 7.

  As described above, both end portions in the Y direction of the via hole 9 according to the first embodiment are configured to coincide with end portions in the Y direction of the trench 7. That is, the via hole 9 has a width in the Y direction equal to the width in the Y direction of the trench 7 and is completely overlapped without protruding from the position in the Y direction of the trench 7. The via hole 9 of the first embodiment is formed in the trench 7 in a self-aligned manner by forming the first via hole pattern 8 </ b> A as a line in a direction orthogonal to the extending direction of the trench 7. The upper surface of the first wiring 3 is exposed on the bottom surface of the via hole 9.

  Next, as shown in FIGS. 8A, 8B, 8C, and 8D, the second BARC film 8 remaining in the trench 7 is removed by oxygen-containing plasma. As a result, a via hole 9 extending in the X direction and continuing below the trench 7 in which the wiring is buried and connected to the lower first wiring 3 is formed. In the trench 7, the bottom surface of the region other than the via hole 9 is constituted by the upper surface of the second interlayer insulating film 4. As shown in FIG. 8A, the first side surface 5a constituting the trench 7 is flush with the via first side surface 4a, and the second side surface 5b is flush with the via second side surface 4b.

  Thus, the method of manufacturing the semiconductor device according to the first embodiment includes the steps of forming the first wiring (3) and the first interlayer insulating film (2) on the semiconductor substrate (1), and the first wiring (3). Sequentially forming a second interlayer insulating film (4) and a third interlayer insulating film (5), a trench (7) in the third interlayer insulating film (5), and a via hole in the second interlayer insulating film (4). Forming the trench (7) in the third interlayer insulating film (5) and forming the via hole (9) in the second interlayer insulating film (4). ) At least a part of the side surfaces (5a, 5b) and at least a part of the side surfaces (4a, 4b, 4c, 4d) of the via hole (9).

  That is, the manufacturing method of the semiconductor device according to the first embodiment includes a step of forming the trench 7 in which the wiring is embedded and a step of forming the via hole 9 continuous on the bottom surface of the trench 7. One of the characteristics is that at least a part of the side surfaces 4a, 4b, 4c, and 4d is formed to be flush with at least a part of the side surfaces 5a and 5b of the trench 7.

(Sidewall film forming process)
Next, a sidewall film forming step for forming sidewall films on the two side surfaces 5a and 5b of the trench 7 and the four side surfaces 4a, 4b, 4c and 4d of the via hole 9 is performed.

  As shown in FIGS. 9A and 9B, a 10 nm thick sacrificial film 10 made of a silicon nitride film is formed on the entire surface including the inner surface of the trench 7 and the inner surface of the via hole 9. A silicon nitride film formed by a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method is excellent in step coverage, so that it is formed at the same thickness in any part.

  Thus, the first side surface 5 a and the second side surface 5 b of the trench 7, the via first side surface 4 a, the via second side surface 4 b, the via third side surface 4 c and the via fourth side surface 4 d of the via hole 9 are positioned in the trench 7. The upper surface of the second interlayer insulating film 4 and the upper surface of the third interlayer insulating film 5 are covered with the sacrificial film 10.

  Next, as shown in FIGS. 10A and 10B, the sacrificial film 10 is etched back by anisotropic dry etching using fluorine-containing plasma. Thereby, the sacrificial film 10 formed on the horizontal plane is removed. That is, the sacrificial film 10 formed on the upper surface of the second interlayer insulating film 4 and the upper surface of the third interlayer insulating film 5 located in the trench 7 is removed.

  As a result, the first sidewall film 10a made of the sacrificial film 10 is formed on the first side surface 5a of the trench 7, and the second sidewall film 10b is formed on the second side surface 5b. Also, the via first sidewall film 10c is formed on the via first side face 4a, the via second sidewall film 10d is formed on the via second side face 4b, and the third via sidewall film 10e is formed on the third via side face 4c. Via fourth sidewall films 10f are respectively formed on the side surfaces 4d. The first sidewall film 10a and the via first sidewall film 10c are formed to be flush with each other. The second sidewall film 10b and the via second sidewall film 10d are also formed to be flush with each other. Further, the four sidewall films 10c, 10e, 10d, and 10f formed on the side surface of the via hole 9 are configured to be continuous in the horizontal direction.

  Therefore, when solution etching of the sacrificial film is performed in the air gap formation step described later, etching proceeds downward from the upper surfaces of the first sidewall film 10a and the second sidewall film 10b, and the via first sidewall film 10c. In addition, the via third sidewall film 10e and the via fourth sidewall film 10f that are continuous in the horizontal direction when reaching the via second sidewall film 10d can be removed by etching.

  If the width of the via hole 9 in the Y direction is narrower than the width of the trench 7 in the Y direction, as will be described in detail in a comparative example described later (FIG. 17), the end of the via hole 9 and the trench 7 A horizontal plane portion made of the second interlayer insulating film 4 is generated between the end portions. The sacrificial film formed on the horizontal surface portion is removed by the above-described etch back process. Therefore, the first sidewall film 10a and the via first sidewall film 10c are not flush with each other and become discontinuous, which hinders the progress of the etching solution, so that there is a problem that an air gap cannot be formed in the via hole 9. To do.

(First via plug and second wiring formation step)
Next, a first via plug and second wiring formation process is performed so as to fill the trench 7 and the via hole 9 in which the sidewall film is formed.

  As shown in FIGS. 11A and 11B, a Cu diffusion barrier film 20a and a Cu film 20b are formed by a known method.

  Next, as shown in FIGS. 12A and 12B, the Cu diffusion barrier film 20a and the Cu film 20b formed on the upper surface of the third interlayer insulating film 5 are removed by a chemical mechanical polishing (CMP) method. . As a result, the second wiring 20 </ b> A is formed in the trench 7, and the first via plug 20 </ b> B is formed in the via hole 9 continuous below the trench 7. Further, the upper surface of the first sidewall film 10a and the upper surface of the second sidewall film 10b that are flush with the upper surface 51 of the third interlayer insulating film 5 are exposed.

(Air gap formation process)
Next, an air gap forming step for removing the sidewall film to form an air gap is performed.

  As shown in FIGS. 13A and 13B, the semiconductor substrate with the upper surface of the first sidewall film 10a and the upper surface of the second sidewall film 10b exposed to a phosphoric acid solution heated to 155 to 165 ° C. Immersion is performed, and the sidewall film made of the silicon nitride film is selectively removed by a solution etching method. Solution etching proceeds isotropically.

  In the first stage of solution etching, etching proceeds downward from the upper surface of each of the first and second sidewall films 10a and 10b formed on the two side surfaces 5a and 5b constituting the trench 7. . In the second stage after the etching reaches the via first sidewall film 10c and the via second sidewall film 10d, the lateral direction is performed simultaneously with the etching of the via first sidewall film 10c and the via second sidewall film 10d. Etching of the via third sidewall film 10e and the fourth via sidewall film 10f that are continuously formed also proceeds.

  As a result, the first AG 11a is formed between the first side surface 5a constituting the trench 7 and the Cu diffusion barrier film 20a, and the second AG 11b is formed between the second side surface 5b and the Cu diffusion barrier film 20a. Is done. A first via AG positioned between the first via side surface 4a and the Cu diffusion barrier film 20a is formed as a first AG 11a, and a second via AG positioned between the second via side surface 4b and the Cu diffusion barrier film 20a is a second AG 11b. Formed as. Further, a via third AG 11c located between the via third side surface 4c and the Cu diffusion barrier film 20a, and a via fourth AG 11d located between the via fourth side surface 4d and the Cu diffusion barrier film 20a are formed.

  As described above, at least part of the sidewall film formed on the side surface of the trench 7 and at least part of the sidewall film formed on the side surface of the via hole 9 continuous below the trench 7 are flush with each other. By forming continuously, it is possible to secure a passage from the trench 7 to the via hole 9 of the solution in which etching proceeds, and AG can be formed on the other side surface of the via hole.

  On the other hand, when the side wall film formed on the side surface of the trench 7 and the side wall film formed on the side surface of the via hole 9 are discontinuous, no solution passage is formed, and AG is formed on the side surface of the via hole 9. Can not form.

(Cap insulation film formation process)
Next, a cap insulating film forming step for closing the upper portion of the AG opened on the upper surface of the third interlayer insulating film 5 is performed.

  As shown in FIGS. 14A and 14B, a cap insulating film 12 made of a silicon oxide film having a thickness of 50 nm is formed using a plasma CVD method with poor step coverage. Since the width of the first and second AGs 11a and 11b in the Y direction is 10 nm, when the cap insulating film 12 having poor step coverage is formed to 50 nm, the openings of the first and second AGs 11a and 11b are formed by the cap insulating film 12. It is closed and a cavity (AG) remains inside.

(Second via plug and third wiring formation step)
Next, a second via plug and third wiring forming step for forming a third wiring to be an upper layer wiring of the second wiring 20A is performed.

  As shown in the plan view of FIG. 1 and FIGS. 15C and 15B, the opening 13a of the cap insulating film 12 is formed at an arbitrary position on the second wiring 20A extending in the X direction by lithography and anisotropic drying. It is formed by an etching method. Thereby, the upper surface of the second wiring 20A is exposed.

  Next, as shown in FIGS. 16C and 16B, after forming a metal conductor on the entire surface, the metal conductor formed on the upper surface of the cap insulating film 12 is removed by CMP. Thereby, the second via plug 13 is formed.

  Next, as shown in FIG. 1 and FIGS. 2B and 2C, an aluminum film is formed on the entire surface, and patterned by lithography and dry etching to form a third wiring 14 connected to the second via plug 13. To do. Note that the second via plug 13 and the third wiring 14 can be formed by the Cu dual damascene method similarly to the first via plug 20B and the second wiring 20B.

  As described above, according to the method of manufacturing the semiconductor device of the first embodiment, the first side surface 5a of the trench 7 and the via first side surface 4a of the via hole 9 disposed continuously below the trench 7 are provided. The second side surface 5b of the trench 7 and the via second side surface 4b of the via hole 9 are formed to be flush with each other. Thereby, the first sidewall film 10a covering the first side surface 5a and the third sidewall film 10a covering the via first side surface 4a can be formed flush with each other. Further, the second sidewall film 10b covering the second side surface 5b and the fourth sidewall film 10d covering the via second side surface 4b can be formed flush with each other. Therefore, by removing the sidewall film, the continuous first AG 11a and second AG 11b from the trench 7 to the via hole 9 can be formed, and the third AG 11c and the fourth AG 11d can be simultaneously formed on the other side surfaces of the via hole 9. . Since AG has a very low dielectric constant, it can contribute to high-speed operation of a semiconductor device by reducing parasitic capacitance between wirings.

(Comparative example)
FIG. 17 shows a bird's eye view at a stage where the sidewall films 10a, 10b, 10c, 10d, and 10f are formed using the dual damascene structure disclosed in Patent Document 3 as a comparative example of the first embodiment. In this comparative example, a via hole 9 that is continuous with the bottom surface of the trench 7 is disposed at the center of the trench 7 in the Y direction. Therefore, the first side surface 5a and the second side surface 5b that constitute the trench 7 and face in the Y direction, and the via first side surface 4a and the via second side surface 4b that constitute the via hole 9 and face in the Y direction are viewed in plan view. There are no overlapping parts.

  As a result, when the sidewall film is formed as in FIGS. 9 and 10, the first sidewall film 10a is formed on the first side surface 5a, and the second sidewall film 10b is formed on the second side surface 5b. In the via hole 9, a via first sidewall film 10c is formed on the first via side surface 4a, and a via second sidewall film 10d is formed on the second via side surface 4b. Further, a via fourth sidewall film 10f is formed on the fourth via side surface 4d.

  However, the first side surface 5a and the via first side surface 4a are separated by a width W4, and the upper surface 4u of the second interlayer insulating film 4 is exposed between them. Therefore, the first sidewall film 10a and the via first sidewall film 10c are not continuous. Therefore, after forming the second wiring 20A and the first via plug 20B, if the AG is formed according to the method of FIG. 13, the first AG and the second AG are formed on the first side surface 5a and the second side surface 5b of the trench 7, respectively. However, AG is not formed on the side surface of the first via plug 20B.

  In other words, the present comparative example has the trench 7 and the via hole 9 extending in contact with the bottom surface of the trench 7, but at least a part of the side surface constituting the trench 7 and the side surface constituting the via hole 9. It does not have a configuration in which at least a part is a flush side surface.

[Second Embodiment]
In the first embodiment, the configuration and the manufacturing method have been described in which the two side surfaces constituting the first via hole 9 are both flush with the two side surfaces constituting the trench 7. In the second embodiment, an example will be described in which one side surface constituting the trench 7 and one side surface constituting the first via hole 9 constitute a flush side surface.

  The first embodiment can be applied only to the trench first method, but the second embodiment can be applied to either the trench first method or the via first method.

  FIG. 18 is a bird's-eye view showing a configuration example of the second embodiment at the stage where the sidewall sacrificial film is formed as in FIG.

  A first via hole 9 exposing the upper surface of the first wiring 3 is disposed, and a trench 7 connected to the upper end of the first via hole 9 and extending in the X direction is disposed. The trench 7 has a first side surface 5a and a second side surface 5b that face each other in the Y direction. The via hole 9 has a via first side surface 4a, a via second side surface 4b, and a via fourth side surface 4d. A first sidewall film 10a is formed on the first side surface 5a, and a second sidewall film 10b is formed on the second side surface 5b. A via first sidewall film 10c is formed on the via first side face 4a, a via second sidewall film 10d is formed on the via second side face 4b, and a via fourth sidewall film 10f is formed on the fourth via side face 4d. . The first side surface 5a and the via first side surface 4a are formed as the same continuous side surface.

  Therefore, the first sidewall film 10a and the via first sidewall film 10c can be formed as flush sidewalls. In the via first sidewall film 10c, a via fourth sidewall film 10f and a via third sidewall film 10e (not shown) are continuously formed in the Y direction, and a via second sidewall film 10d is continuously formed. Is done. Since the via second side surface 4b is not flush with the second side surface 5b, the via second sidewall film 10d and the second sidewall film 10b are formed apart from each other in the Y direction.

  In the above configuration, after the second wiring 20A and the first via plug 20B are formed, when the sidewall film removing step is performed, etching proceeds from the upper surface of the first sidewall film 10a, and the via first sidewall film 10c is formed. At this stage, the etching also proceeds to the via third sidewall film 10e and the via fourth sidewall film 10f that are continuous in the lateral direction, and the via second sidewall film 10d is also etched. Therefore, even if one side surface 5a of the trench 7 and one side surface 4a of the first via hole are flush with each other, the two side surfaces of the trench 7 and the four side surfaces of the first via hole 9 are simultaneously AG. Can be formed.

  In the first embodiment, there is a restriction that the width of the trench 7 in the Y direction and the width of the first via hole 9 in the Y direction are the same size, but in the second embodiment, each width is arbitrarily set. You can change the layout.

  The configuration as shown in FIG. 18 can be achieved by using an individual hole pattern as a formation mask for the first via hole 9 instead of a line pattern extending in the Y direction across the plurality of wirings 20A.

  FIGS. 19A and 19B schematically show an example in which an individual hole pattern is used for the formation mask of the first via hole 9. FIG. 19A shows an example of the trench first method, and FIG. 19B shows an example of the via first method.

  First, an example of the trench first method will be described with reference to FIG.

  As in the first embodiment, a trench 7 extending in the X direction is formed in the third interlayer insulating film 5. The trench 7 has a first side surface 5a and a second side surface 5b that face each other in the Y direction. Thereafter, the trench 7 is buried with a trench filling material 25 such as a BARC film, and the surface is flattened. Next, a mask film 30 including a hard mask film on the entire surface and having a photoresist film on the uppermost surface is formed.

  Next, a rectangular via hole pattern 9a is formed in the mask film 30 by lithography and anisotropic dry etching. The via hole pattern 9a has a via pattern first side face 30a and a via pattern second side face 30b that face in the Y direction, and a via pattern third side face 30c and a via pattern fourth side face 30d that face in the X direction. . Via holes 9 that penetrate the third interlayer insulating film 5 and the trench burying material 25 and the second interlayer insulating film 4 and reach the first wiring 3 are formed by anisotropic dry etching using the mask film 30 as a mask. The

  The positions of the via pattern first side surface 30a and the via pattern second side surface 30b correspond to the positions of the via first side surface 4a and the via second side surface 4b of the via hole 9, respectively. The positions of the via pattern third side surface 30c and the via pattern fourth side surface 30d correspond to the positions of the via third side surface 4c and the via fourth side surface 4d of the via hole 9, respectively.

  In FIG. 19A, the first side surface 5a of the trench 7 and the via pattern first side surface 30a extend in parallel to the X direction. Further, the mask film 30 is formed so that the first side surface 5a is located between the via pattern first side surface 30a and the via pattern second side surface 30b. The first side surface 5a and the via pattern first side surface 30a may overlap in plan view. Thus, by arranging the via hole pattern 9a, at least a part of the side surface constituting the trench 7 and at least a part of the side surface constituting the via hole 9 can be formed in a flush configuration.

  After the via hole 9 is formed, the mask film 30 and the trench burying material 25 are removed. Next, as in the first embodiment, when the sidewall film is formed, the configuration of FIG. 18 is formed.

  Therefore, the sidewall film can be formed flush and the AG can be formed flush.

  In the case of FIG. 19A, the via pattern second side surface 30b does not have a plan view overlap with the second side surface 5b. Therefore, the side surface which is flush with the via hole 9 is not formed on the second side surface 5b side, but AG is formed on all side surfaces of the via hole 9 through the flush side surface formed on the first side surface 5a side. Can do.

  FIG. 19A shows an example of the mask pattern 30 that forms the flush side surface with the via hole 9 on the first side surface 5a side, but the present invention is not limited thereto, and the flush side surface is formed on the second side surface 5b side. You may do it.

  Next, an example of the via first method will be described with reference to FIG.

  In FIG. 19B, a via hole 9 that penetrates the third interlayer insulating film 5 and the second interlayer insulating film 4 and reaches the first wiring 3 is formed first. The via hole 9 has a via first side surface 4a and a via second side surface 4b facing each other in the Y direction, and a via third side surface 4c and a via fourth side surface 4d facing each other in the X direction.

  After the via hole 9 is formed, the inside of the via hole 9 is buried with a via hole burying material 25b such as a BARC film, and the surface is flattened. Next, a mask film 40 including a hard mask film on the entire surface and a photoresist film on the uppermost surface is formed. Next, a trench pattern 7a having a line extending in the X direction is formed in the mask film 40 by lithography and anisotropic dry etching.

  The trench pattern 7a has a trench pattern first side surface 40a and a trench pattern second side surface 40b that face each other in the Y direction. The trench 7 reaching the second interlayer insulating film 4 is formed by etching the third interlayer insulating film 5 and the via hole burying material 25b by anisotropic dry etching using the mask film 40 as a mask.

  The positions of the trench pattern first side surface 40a and the trench pattern second side surface 40b correspond to the positions of the first side surface 5a and the second side surface 5b of the trench 7, respectively.

  In FIG. 19B, the via first side surface 4a of the via hole 9 and the trench pattern first side surface 40a extend in parallel to the X direction. Further, the mask film 40 is formed so that the trench pattern first side surface 40a is located between the via first side surface 4a and the via second side surface 4b. The via first side surface 4a and the trench pattern first side surface 40a may overlap in plan view.

  Thus, even if the trench pattern 7a is arranged, the via first side surface 4a that penetrates the third interlayer insulating film 5 and the second interlayer insulating film 4 and is flush with the first side surface 4a is already formed. At least a part of the side surface and at least a part of the side surface constituting the via hole 9 can be formed to be flush with each other. The via first side surface 4a itself forms a flush side surface.

  After the trench 7 is formed, the mask film 40 and the via hole burying material 25b are removed. Next, as in the first embodiment, when the sidewall film is formed, the configuration of FIG. 18 is formed. Therefore, the sidewall film can be formed flush and the AG can be formed flush.

  In the case of FIG. 19B, the trench pattern second side surface 40b does not overlap with the via second side surface 4b in plan view. Accordingly, no side surface that is flush with the trench 7 is formed on the via second side surface 4b side, but AG is formed on all side surfaces of the via hole 9 through the flush side surface formed on the via first side surface 4a side. can do.

  FIG. 19B shows an example of the mask pattern 40 that forms a flush side surface with the trench 7 on the via first side surface 4a side, but the present invention is not limited to this. May be formed.

[Third Embodiment]
According to the manufacturing method of the second embodiment, since the position of the via hole 9 continuously formed under the trench 7 can be arbitrarily arranged, the wiring is different from the wiring layout of the first embodiment shown in FIG. Layout can be configured.

  A semiconductor device according to the third embodiment of the present invention will be described with reference to the plan view of FIG.

  For example, a plurality of first wirings (lower layer wirings) 3A extending in one direction in the Y direction and a plurality of first wirings (lower layer wirings) 3B extending in the other direction in the Y direction are arranged. The individual wires of the plurality of first wires 3A and the individual wires of the first wires 3B each extend in the Y direction in parallel. Each of the plurality of first wirings 3A is connected to an upper-layer first collective wiring 20A1 embedded in a first trench 7A having a damascene structure and extending in the X direction. Similarly, each of the plurality of first wirings 3B is connected to the upper second aggregate wiring 20A2 embedded in the second trench 7B having a damascene structure and extending in the X direction.

  The first collective wiring 20A1 and the plurality of first wirings 3A are connected via a first via plug 20B1 in which a first via hole 9A corresponding to each first wiring 3A is embedded. Each of the first trench 7A and the second trench 7B has a first side surface 5a and a second side surface 5b that face each other in the Y direction. The first AG 11a is disposed on the first side surface 5a, and the second AG 11b is disposed on the second side surface 5b. Each of the plurality of first via plugs 20B1 connected to the first collective wiring 20A1 includes a first via AG11e and a second via AG11f that face each other in the Y direction, and a third via AG11c and a fourth via AG11d that face each other in the X direction. The via second AG11f is flush with the second AG11b. The via first AG 11e is spaced apart from the first AG 11a and does not have a flush configuration. That is, each of the plurality of first via plugs 20B1 connected to the first collective wiring 20A1 has an AG that is flush with the second AG 11b disposed on one side surface 5b of the first trench 7A.

  On the other hand, the via plug 20B connected to the second collective wiring 20A2 includes the first via plug 20B1 and the second via plug 20B2 having a configuration in which the via first AG11e is flush with the first AG11a. In the second collective wiring 20A2, the first via plugs 20B1 and the second via plugs 20B2 are alternately arranged in the X direction. By arranging the via plugs 20B in a zigzag shape in plan view, it is possible to reduce the facing area between the adjacent via plugs and to further reduce the parasitic capacitance.

  According to the third embodiment based on the configuration of the second embodiment, it is not necessary to match the width in the Y direction of the via plug and the width in the Y direction of the wiring connected to the upper surface of the via plug. The degree of freedom in layout can be further improved.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st interlayer insulation film 3 1st wiring 3A 1st wiring (lower layer wiring)
3B 1st wiring (lower layer wiring)
4 2nd interlayer insulating film 4a Via first side surface 4b Via second side surface 4c Via third side surface 4d Via fourth side surface 5 Third interlayer insulating film 5a First side surface 5b Second side surface 51 Upper surface 6 First mask film (first BARC Film, first Si-containing organic film, first photoresist film)
6a Trench pattern 7 Wiring groove (trench)
7a trench pattern 7A first trench 7B second trench 8 second BARC film (trench buried film)
81 Upper surface 8a Second Si-containing organic film 8b Second photoresist film 8c Second mask film 8A First via hole pattern (second mask film pattern)
8B Second via hole pattern 8d Third side surface 8e Fourth side surface 9 Via hole 9a Via hole pattern 9A First via hole 10 Sacrificial film 10a First sidewall film 10b Second sidewall film 10c Via first sidewall film 10d Via second sidewall Film 10e Via third sidewall film 10f Via fourth sidewall film 11a First air gap (AG)
11b Second Ever Gap (AG)
11c 3rd air gap (AG)
11d 4th air gap (AG)
12 Cap insulating film 13 Second via plug 13a Opening 14 Third wiring 20a Cu diffusion barrier film 20b Cu film 20A Second wiring 20A1 First aggregate wiring 20A2 Second aggregate wiring 20B First via plug (via plug)
20B1 First via plug 20B2 Second via plug 25 Trench buried material 25b Via hole buried material 30 Mask film 30a Via pattern first side surface 30b Via pattern second side surface 30c Via pattern third side surface 30d Via pattern fourth side surface 40 Mask film 40a Trench pattern first 1 side 40b trench pattern 2nd side

Claims (14)

A first wiring disposed on the semiconductor substrate;
A via plug for burying a via hole connected to the upper surface of the first wiring;
A second wiring embedded in a trench connected to the upper surface of the via plug and extending in the first direction;
Have
A trench air gap disposed on each of two side surfaces constituting the trench;
A via air gap disposed on a side surface of the via hole;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the two side surfaces constituting the trench include a first side surface and a second side surface facing each other in a second direction orthogonal to the first direction. The via hole is composed of a rectangular pattern in plan view,
Side surfaces constituting the via hole are composed of via first side surfaces and via second side surfaces facing the second direction, and via third side surfaces and via fourth side surfaces facing the first direction.
The semiconductor device according to claim 2. The trench air gap is
A first air gap disposed between the first side surface and the second wiring;
A second air gap disposed between the second side surface and the second wiring;
Consisting of
The via air gap is
The first air gap disposed between the via first side surface and the via plug;
The second air gap disposed between the via second side surface and the via plug;
A third air gap disposed between the via third side surface and the via plug;
A fourth air gap disposed between the via fourth side surface and the via plug;
Consisting of,
The semiconductor device according to claim 3.   The first air gap, the second air gap, the third air gap, and the fourth air gap are connected to each other at a corner portion in plan view of the via hole, and a single ring-shaped air gap is used as the via air gap. The semiconductor device according to claim 4, which is configured.   The semiconductor device according to claim 2, wherein the via hole has a circular pattern in plan view. A first wiring disposed on the semiconductor substrate;
A via plug for burying a via hole connected to the upper surface of the first wiring;
A second wiring embedded in a trench connected to the upper surface of the via plug and extending in the first direction;
A trench air gap disposed on each of two side surfaces constituting the trench;
A via air gap disposed on a side surface of the via hole, and
At least a part of the trench air gap disposed on the side surface of the trench and at least a part of the via air gap disposed on the side surface of the via hole are configured to be flush with each other. apparatus.   8. The semiconductor device according to claim 7, wherein the two side surfaces constituting the trench include a first side surface and a second side surface that face each other in a second direction orthogonal to the first direction. The via hole is composed of a rectangular pattern in plan view,
Side surfaces constituting the via hole are composed of via first side surfaces and via second side surfaces facing the second direction, and via third side surfaces and via fourth side surfaces facing the first direction.
The semiconductor device according to claim 8. The trench air gap is
A first air gap disposed between the first side surface and the second wiring;
A second air gap disposed between the second side surface and the second wiring;
Consisting of
The via air gap is
The first air gap disposed between the via first side surface and the via plug;
The second air gap disposed between the via second side surface and the via plug;
A third air gap disposed between the via third side surface and the via plug;
A fourth air gap disposed between the via fourth side surface and the via plug;
Consisting of,
The semiconductor device according to claim 9.   The first air gap, the second air gap, the third air gap, and the fourth air gap are connected to each other at a corner portion in plan view of the via hole, and a single ring-shaped air gap is used as the via air gap. The semiconductor device according to claim 10, which is configured. Forming a first wiring and a first interlayer insulating film on the semiconductor substrate;
Sequentially forming a second interlayer insulating film and a third interlayer insulating film on the first wiring;
Forming a trench in the third interlayer insulating film and forming a via hole in the second interlayer insulating film;
Have
In the step of forming a trench in the third interlayer insulating film and a via hole in the second interlayer insulating film, at least a part of the side surface of the trench and at least a part of the side surface of the via hole are flush with each other. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device. Forming a sidewall film on a side surface of the trench and a side surface of the via hole;
Forming a first via plug and a second wiring so as to embed the trench and the via hole, respectively;
Removing the sidewall film to form an air gap;
The method of manufacturing a semiconductor device according to claim 12, further comprising: Forming a cap insulating film that closes an upper portion of the air gap opening on the upper surface of the third interlayer insulating film;
Forming an opening in the cap insulating film, and forming a second via plug in the opening;
Forming a third wiring connected to the second via plug on the upper surface of the cap insulating film;
The method for manufacturing a semiconductor device according to claim 13, further comprising:

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