JP3904496B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof. The present invention is applied to, for example, a chip size CSP (Chip Size Package) technique.
[0002]
[Prior art]
In recent years, various electronic devices have been increasingly demanded for miniaturization and high performance. With these demands, semiconductor devices used in electronic devices have become highly integrated circuits and high-density packaging, as well as information processing. There is an increasing demand for higher speed. That is, in response to these demands, semiconductor devices are shifting from the pin insertion type to the surface mounting type in order to improve the mounting density. Also, various packages such as DIP (dual inline package) to QFP (quad flat package) and PGA (pin grid array) have been developed to cope with the increase in the number of pins.
[0003]
However, in QFP, the connection leads for connecting to the mounting substrate are concentrated on the periphery of the package, and the connection leads themselves are thin and easily deformed, so that mounting becomes difficult as the number of pins increases. It is going
Further, the PGA has a problem that it is difficult to perform high-speed processing of information due to its characteristics because the terminals for connecting to the mounting substrate are elongated and a considerable number of terminals are concentrated. Furthermore, since it is a pin insertion type, surface mounting cannot be performed, which is disadvantageous in high-density mounting.
[0004]
Recently, a stress buffer layer is formed between a semiconductor element and a substrate on which a wiring circuit portion is formed in order to solve various problems of these packages and realize a semiconductor device capable of handling high-speed information processing. A BGA (ball grid array) package has been developed that includes bump electrodes serving as external terminals on the mounting substrate surface side of the substrate on which the wiring circuit portion is formed. BGA is disclosed, for example, in US Pat. No. 5,148,265.
[0005]
In the package disclosed in the specification of US Pat. No. 5,148,265, since the terminals connected to the mounting substrate are ball-shaped solder, the connecting leads are not deformed unlike QFP, and the terminals are distributed over the entire mounting surface. Since it is arranged, the pitch between terminals is increased, and surface mounting is facilitated. In addition, since the length of the bump electrode serving as the external terminal is shorter than that of PGA, the inductance component is reduced, the information processing speed is increased, and high-speed information processing is possible.
[0006]
On the other hand, in recent years, with the widespread use of portable information terminal devices, there has been an increasing demand for miniaturization and high-density mounting of semiconductor devices. Therefore, recently, a CSP (chip scale package) whose package size is almost the same as that of a chip has been developed. For example, “Nikkei Microdevice” (pp38-64) issued by Nikkei Business Publications, Inc. (February 1998). ) Discloses various types of CSPs. In the CSP disclosed here, after bonding a semiconductor element cut into individual pieces onto a polyimide or ceramic substrate on which a wiring layer is formed, the wiring layer and the semiconductor element are bonded by wire bonding or single point bonding, It is manufactured by electrically connecting by means of gang bonding, bump bonding or the like, sealing those connecting portions with resin, and finally forming external terminals such as solder bumps.
[0007]
Furthermore, “Nikkei Microdevice” (pp164-167) issued by Nikkei BP (April 1998) discloses a manufacturing method for mass-producing CSP. In this manufacturing method, bumps are formed by plating on a semiconductor wafer (hereinafter referred to as a unit wafer), parts other than the bumps are sealed with resin, external electrodes are formed on the bumps, and then the wafer is cut into individual pieces. Thus, individual semiconductor devices are manufactured.
[0008]
In addition, Japanese Patent Laid-Open No. 2000-260910 discloses a method for manufacturing a semiconductor device, characterized in that after wafers are processed in batches, the wafers are finally separated into individual pieces. In this method of manufacturing a semiconductor device, a semiconductor device is manufactured in which the side surfaces of individual pieces are covered with resin.
[0009]
A conventional method for manufacturing a semiconductor device will be described with reference to FIG.
(1) A wiring made of copper is formed by electroplating or the like on a wafer 2 on which a semiconductor element is formed on one surface and a metal wiring layer (not shown) including an electrode pad is formed thereon. . The copper wiring is electrically connected to electrode pads formed on the wafer 2. After the ultraviolet curable dicing tape 45 is attached to the surface of the wafer 2 opposite to the copper wiring forming surface, grooves 47 are formed on the surface of the wafer 2 by a peripheral blade (dicing saw) rotated at high speed. The groove 47 is formed in a portion that becomes a peripheral portion of each chip (semiconductor device). The blade thickness of the dicing saw used for forming the groove 47 is 35 to 150 μm (micrometer). The width of the groove 47 is formed to be 1 to 5 μm larger than the blade thickness, and the depth is, for example, 10 μm or more. By setting the depth of the groove 47 to 10 μm or more, it is possible to form the groove 47 with a stable width without depending on the shape of the tip of the blade (see (a)).
[0010]
(2) Fill the surface of the wafer 2 with a resin 49. The resin 49 filled at this time also enters the groove 47. The surface of the resin is polished with a polishing blade until a portion of the copper wiring covered with the resin 49 is exposed, and then external connection terminals 25 are formed on the exposed copper wiring by solder balls or the like. Thereafter, a groove 51 is formed in the resin 49 formed on the groove 47 by a dicing saw rotating at high speed (see (b)).
[0011]
(3) The wafer 2 in an area corresponding to the groove 51 is cut by a dicing saw that rotates at high speed to divide the wafer 2 into individual chips 53. The dicing saw used at the time of cutting is formed with a thinner blade thickness than the dicing saw used when forming the groove 51, and the groove 53 is formed with a width narrower than that of the groove 51 (see (c)).
(4) After the dicing tape 45 is cured by irradiating ultraviolet rays, the chip 53 that has been separated into pieces is pushed up and taken out using the pickup needle 37 (see (d)).
[0012]
[Problems to be solved by the invention]
In the conventional method of manufacturing a semiconductor device in which a chip here is cut out from a wafer using a dicing saw, when dicing is performed, as shown in FIG. 11, chipping (chip chipping) or cracks (cracks) on the back side of the wafer 2 are performed. As a result, the problem arises that the bending stress of the chip is lowered. Further, in the wafer level CSP, the chip back surface is engraved on the back surface of the chip, and the back surface of the chip becomes the front surface side when mounted.
[0013]
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing occurrence of chipping and cracks when a chip is cut out from a wafer, and a semiconductor device manufactured by the manufacturing method.
[0014]
[Means for Solving the Problems]
  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a dividing step of dividing a semiconductor wafer on which a plurality of semiconductor devices are formed into individual semiconductor devices.,the aboveThe dividing process has an opening on one surface of the semiconductor wafer corresponding to the divided area.,semiconductorRounded to correspond to the corners of the device forming areaIn addition, an opening for forming a marking is formed in the formation region of the semiconductor device.An etching stopper film is formed, and the semiconductor wafer is selectively removed by etching technique using the etching stopper film as a mask to divide into individual semiconductor devices.At the same time, a marking consisting of one or a plurality of recesses is formed on the semiconductor device..
[0015]
Since a chip (semiconductor device) is cut out from the wafer using an etching technique, chipping and cracking can be prevented.
Further, in the conventional chip singulation, the shape of the chip was rectangular because it was cut out in the vertical and horizontal directions by dicing technology, but according to the method for manufacturing a semiconductor device of the present invention, chip singulation is performed by etching. Thus, the chip shape can be processed into an arbitrary shape.
[0016]
  Manufacturing of the semiconductor device of the present inventionIn the wayBy cutting out the chip from the wafer using the etching stopper film having a roundness corresponding to the corner portion of the chip formation region shape as a mask, the corner portion of the chip after cutting can be rounded. This eliminates the corners of the chip and makes it smooth so that chipping and cracks can be prevented during chip transport, reducing appearance defects and improving reliability. it can.
[0020]
  furtherBy cutting out a chip from the wafer using an etching stop film having an opening for marking formation in the chip formation region as a mask, a marking consisting of one or a plurality of recesses can be formed on the chip after cutting. . As a result, simultaneously with the cutting of the chip, information such as lot information and product information can be recorded on the marking, and the chip can be recognized by the marking.
[0026]
  furtherFor example, information such as lot information and product information can be recorded on the marking composed of a plurality of recesses, and chip recognition can be performed by the marking.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
  In the method for manufacturing a semiconductor device of the present inventionOne of the plurality of corner portions of the etching stopper film for each semiconductor device is preferably rounded with a size different from that of the other corner portions. As a result, in the chip after cutting, a specific corner portion can be recognized from the roundness of the corner portion, and the orientation of the chip, for example, the position of one pin can be recognized.
[0029]
Furthermore, it is preferable to use a dry etching technique when the semiconductor wafer is selectively removed by the etching technique using the etching stopper film as a mask. As a result, by using a dry etching technique capable of anisotropic etching, the interval between a plurality of chips formed on a wafer can be significantly narrowed compared to the conventional dicing process, and one wafer The number of chips taken can be increased.
[0030]
Further, after a tape material is attached to the surface of the semiconductor wafer opposite to the surface on the side where the etching stopper film is formed, the surface of the semiconductor wafer on the side where the etching stopper film is formed is polished, It is preferable to divide the semiconductor wafer into individual semiconductor devices by forming the etching stop film on the polished surface of the semiconductor wafer with the wafer attached to the tape material. As a result, the thinned semiconductor wafer after polishing is supported by the tape material, so that it can be easily transported and the chip thickness can be reduced. Furthermore, since the dicing tape used in the prior art becomes unnecessary, it is possible to reduce waste in the manufacturing process.
[0032]
  further,One of the plurality of corner portions is preferably rounded with a size different from that of the other corner portions. As a result, a specific corner portion can be recognized from the roundness of the corner portion, and the orientation of the chip, for example, the position of one pin can be recognized.
[0033]
【Example】
  FIG. 1 shows a semiconductor device.Reference example(A) is a top view, (B) is sectional drawing in the AA position of (A).
  A base insulating film 3 made of a silicon oxide film is formed on the silicon substrate 1. A polysilicon film (not shown) such as a gate electrode or a resistor is formed on the base insulating film 3. A first interlayer insulating layer 5 made of, for example, a BPSG (boro-phosphosilicate glass) film is formed on the base insulating film 3. Although not shown, a semiconductor element such as a transistor is formed under the first interlayer insulating layer 5 in another region of the chip, and a contact hole is formed in the first interlayer insulating layer 5.
[0034]
A first metal wiring layer 7 made of, for example, an Al—Si alloy (Si: 1 w% (mass percent)) is formed on the first interlayer insulating layer 5. In FIG. 1, only the electrode pad portion of the first metal wiring layer 7 is shown.
On the first interlayer insulating layer 5 and the first metal wiring layer 7, for example, the lower layer is a PSG (phospho silicate glass) film 9 having a thickness of 0.4 μm, and the upper layer is SiN (silicon nitride) having a thickness of 1.2 μm. Film) A passivation film made of film 11 is formed. Furthermore, a photosensitive polyimide layer 13 having a film thickness of, for example, 5.3 μm is formed thereon. The PSG film 9, the SiN film 11 and the photosensitive polyimide layer 13 constitute a second interlayer insulating layer 15.
[0035]
A through hole 17 is formed in the second interlayer insulating layer 15 corresponding to the electrode pad portion of the first metal wiring layer 7. The photosensitive polyimide layer 13 portion of the through hole 17 is formed in a tapered shape.
A second metal wiring layer 19 made of, for example, an Al—Si alloy (Si: 1 w%) or copper is formed on the second interlayer insulating layer 15 and in the through hole 17. The film thickness of the second metal wiring layer 19 is 3 μm, for example, and a part thereof constitutes the second electrode pad portion.
[0036]
A photosensitive polyimide layer 21 having a film thickness of, for example, 25 μm is formed on the photosensitive polyimide layer 13 including the second metal wiring layer 19. The photosensitive polyimide layer 21 constitutes a sealing layer.
[0037]
The photosensitive polyimide layer 21 is provided with a pad opening 23 corresponding to the second electrode pad portion of the second metal wiring layer 19. An external connection terminal 25 made of, for example, solder is formed in the pad opening 23. The external connection terminal 25 has a tip portion protruding from the surface of the photosensitive polyimide layer 21.
[0038]
As shown in FIG. 1A, the corner portions 27 of the silicon substrate 1 and the photosensitive polyimide layer 21 forming the outer shape of the chip are rounded. Thereby, the occurrence of chipping and cracks during the conveyance of the chip can be prevented, and the appearance defect can be reduced and the reliability can be improved.
[0039]
  2 to 4 show a method for manufacturing a semiconductor device.Reference exampleIt is process sectional drawing which shows these.
(1) After forming a base insulating layer 3 and a semiconductor element such as a transistor (not shown) on the wafer 2, a BPSG film as the first interlayer insulating layer 5 is formed on the wafer 2. A contact hole (not shown) is formed in the first interlayer insulating layer 5, and the first interlayer insulating layer 5 and the base insulating layer 3 on the divided region for dividing the chip from the wafer are selectively removed. A first metal material layer is formed on the entire surface of the wafer 2 by depositing an Al—Si alloy (Si: 1 w%) to a thickness of 3 μm by, for example, sputtering, and the first metal is formed by photolithography and etching techniques. The material layer is patterned to form the first metal wiring layer 7 (see FIG. 2A).
[0040]
(2) The PSG film 9 is formed to a thickness of 0.4 μm on the entire surface of the wafer 2 by, for example, CVD (chemical vapor deposition), and the SiN film 11 is further formed to a thickness of 1.2 μm thereon. Then, a passivation film is formed. Further thereon, for example, a positive photosensitive polyimide material layer is formed to a thickness of 5.3 μm by spin coating.
[0041]
By exposure and development processing using a gradation mask, a tapered opening is formed in the positive photosensitive polyimide material layer corresponding to the first metal wiring layer 7, and an opening is formed in the divided region. Thereafter, a polyimide curing process at 320 ° C. is performed to form the photosensitive polyimide layer 13. The PSG film 9, the SiN film 11, and the photosensitive polyimide layer 13 constitute a second interlayer insulating layer 15 (see FIG. 2B).
[0042]
Here, the gradation mask has a two-dimensional distribution of light transmittance, and the transmittance changes stepwise or continuously in this two-dimensional distribution. A gradation mask is disclosed in, for example, JP-A-9-146259. By using the gradation mask, tapered trimming openings and pad openings can be formed in the photosensitive polyimide layer 13. Thereby, sufficient coverage (step coverage) can be obtained for the second metal wiring layer formed in the pad opening. Even if, for example, a photosensitive polybenzoxazole layer is used instead of the photosensitive polyimide layer 13, a tapered shape can be formed.
[0043]
(3) Using the photosensitive polyimide layer 13 as a mask, the SiN film 11 and the PSG film 9 are etched, and the PSG film 9, the SiN film 11, and the photosensitive polyimide layer 13 are sequentially formed on the first metal wiring layer 7 from the lower layer side. A through hole 17 is formed in the second interlayer insulating layer 15 made of and the PSG film 9 and the SiN film 11 in the divided regions are removed (see FIG. 2C).
[0044]
(4) A second metal wiring layer 19 is formed on the second interlayer insulating layer 15 and in the through hole 17. Here, since the through-hole 17 is formed in a taper shape, sufficient coverage can be obtained for the second metal wiring layer 19 serving as the second metal wiring layer (see FIG. 2D).
[0045]
The material of the second metal wiring layer 19 is, for example, an aluminum alloy layer (Al—Si alloy (Si: 1 w%), Al—Si—Cu alloy (Si: 1 w%, Cu: 0.5 w%), Al—Cu ( Cu: 1 w%), Al—Cu (Cu: 2 w%) and the like) and copper.
[0046]
When an Al—Si alloy (Si: 1 w%) is used as the material of the second metal wiring layer 19, an aluminum alloy layer made of an Al—Si alloy (Si: 1 w%) is formed to a thickness of 3 μm by sputtering. Further, a barrier metal layer (not shown) made of Ti layer / Ni layer / Ag layer (film thickness: 0.1 μm / 0.4 μm / 0.1 μm) is formed thereon by sputtering or vapor deposition. A resist pattern corresponding to the wiring pattern is formed by resist coating, exposure by photolithography and development. The barrier metal is selectively removed by wet etching, and the aluminum alloy layer is selectively removed by dry etching to form a wiring pattern. After the etching, the resist pattern is removed with a plasma asher. The barrier metal layer may be made of other metal materials such as Ti layer / Ni layer / Au layer, Ni layer / Pd layer / Au layer, and the like.
[0047]
When copper is used as the material of the second metal wiring layer 19, by sputtering, chromium for preventing copper migration and improving adhesion is sequentially formed in a thickness of 0.1 μm and copper in a thickness of 0.5 μm. Form a film. A resist pattern corresponding to the wiring pattern is formed by resist coating, exposure by photolithography and development. By electrolytic plating, a copper wiring is formed to a thickness of 3 μm, and further thereon, nickel is deposited in a thickness of 3 μm, palladium is 0.5 μm, and gold is deposited in a thickness of 1 μm. After removing the resist pattern with the asher, the portion of chromium and copper where the copper wiring is not formed is removed by wet etching to complete the second metal wiring layer 19.
[0048]
(5) For example, the negative photosensitive polyimide material 12 is applied and formed with a film thickness of 25 μm by spin coating. Exposure is performed using a reticle having a light-shielding portion corresponding to the pad opening formation region and the divided region (see arrow), and the negative photosensitive polyimide material 12 excluding the pad opening formation region and the divided region is irradiated with light. (See FIG. 2 (e)).
[0049]
(6) and a development process are performed to form a pad opening 23 corresponding to the second electrode pad portion of the second metal wiring layer 19 in the negative photosensitive polyimide material 12, so that the negative photosensitive polyimide in the divided region is formed. Material 12 is removed. Thereafter, a polyimide curing process at 320 ° C. is performed to form the photosensitive polyimide layer 13 (see FIG. 3F).
[0050]
(7) After the cream solder is formed to a thickness of 300 μm corresponding to the position of the pad opening 23 by the screen printing method, the film is heated at 260 ° C. for 10 seconds by a heating and melting method using an infrared reflow furnace. External connection terminals 25 are formed. Thereafter, the flux used in the screen printing method is removed with a dedicated cleaning solution, washed with water, and dried (see FIG. 3G). In FIG. 3G to FIG. 4N, illustration of the insulating layer and the metal wiring layer formed in the above steps (1) to (6) is omitted, and the wafer 2 is shown integrally. Further, illustration of grooves provided in the photosensitive polyimide layer 13 corresponding to the divided regions is omitted.
[0051]
(8) A wafer test is performed by bringing a test pin into contact with the external connection terminal 25. As a result, non-defective and defective chips are selected and stored for each wafer. A surface protection tape (tape material) 31 at the time of grinding is affixed to the surface 2a of the wafer 2 on the side where the external connection terminals 25 are formed. Here, as the surface protection tape 31, for example, a tape that is cured by irradiation with ultraviolet rays and loses adhesive force is used (see FIG. 3H).
[0052]
(9) The back surface 2b opposite to the front surface 2a of the wafer 2 is grind-polished so that the thickness of the wafer 2 is, for example, 50 to 200 μm (see FIG. 3I).
[0053]
(10) After the back surface 2b of the wafer 2 is polished, laser marking for chip identification is performed on the back surface 2b in a state where the surface protection tape 31 is left without being peeled off. In laser marking, a transmission type alignment function using (IR) infrared rays is used, and printing (not shown) is provided on the back surface 2b corresponding to each chip formation region. A photoresist (etching prevention film) 33 is applied onto the back surface 2b by spin coating (see FIG. 3J).
[0054]
(11) Alignment with the divided area of the wafer 2 is performed using the IR aligner, the photoresist 33 is exposed and developed, and an opening is formed in the photoresist 33 corresponding to the divided area as shown in FIG. 35 is formed (see FIG. 4 (k)). The width dimension of the opening 35 is, for example, 1 μm. The photoresist 33 has rounded corners corresponding to the shape of the chip formation region when viewed from the upper surface side (see FIG. 5).
[0055]
(12) With the surface protection tape 31 left, for example, an anodic coupled parallel plate type dry etching apparatus (ICP (Inductive Coupled Plasma) etcher) is used with the wafer 2 facing the back surface 2b toward the plasma chamber. Then, the wafer 2 is etched. SF₆(Sulfur hexafluoride) and C_FourF₈A reaction gas in which (perfluorocyclobutane) was mixed at a rate of 110 cc and 100 cc, respectively, was introduced from the inlet, the reaction chamber was maintained at a pressure of 2.1 Pa, and 600 W of high-frequency power was applied to the coil for 5.5 seconds. Then, the silicon is removed from the processed portion of the wafer 2 by causing a physicochemical reaction or the like between the exposed silicon in the processed portion and radicals or reactive gas ions remaining in the plasma. Next, SF₆Stop C_FourF₈190 cc, and the reaction chamber is maintained at a pressure of 1.6 Pa, and a high frequency power of 600 W is applied to the coil for 5 seconds to attach the reaction product to the side wall of the groove or hole from which the silicon has been removed. Etching proceeds anisotropically while repeating the steps of 5.5 seconds and 5.0 seconds while the reaction product becomes an etching mask on the side wall of the groove or hole. In this plasma etching process, the etching is stopped by the surface protection tape 31 in the divided region. As a result, the wafer 2 is divided into individual chips 4 (see FIG. 4L).
[0056]
(13) The photoresist 33 is removed by an asher (see FIG. 4M).
(14) The surface 2 a side of the wafer 2 is irradiated with ultraviolet rays by an ultraviolet irradiator to eliminate the adhesive force of the surface protection tape 31. The chip 4 is pushed up by the pick-up needle 37 and the chip 4 is picked up (see FIG. 4 (n)).
[0057]
Thus, since the chip 4 is cut out from the wafer 2 using the etching technique, the occurrence of chipping and cracks can be prevented.
Further, by cutting out the chip from the wafer 2 using the photoresist 33 having a round shape corresponding to the corner portion of the formation region shape of the chip 4 as a mask, the corner portion of the chip 4 after being cut out can be rounded. . Thereby, the occurrence of chipping and cracks during the conveyance of the chip 4 can be prevented, and the appearance defect can be reduced and the reliability can be improved.
[0058]
Further, after the front surface protection tape 31 is attached to the front surface 2a of the wafer, the back surface 2b of the wafer 2 is polished, and the wafer 2 is attached to the front surface protection tape 31, and the photo is applied to the back surface 2b after polishing of the wafer 2. Since the resist 33 is formed and the wafer 2 is divided into individual chips 4, the thinned wafer 2 after polishing is supported by the surface protection tape 31, so that it is easy to transport and the thickness of the chip 4 is reduced. Can be finished. Furthermore, since the dicing tape used in the prior art becomes unnecessary, it is possible to reduce waste in the manufacturing process.
[0059]
  FIG. 6 shows a semiconductor device.Reference example(A) is a top view, (B) is a side view.
  As shown in FIG. 4A, the corner portions 27 of the silicon substrate 1 and the photosensitive polyimide layer 21 forming the outer shape of the chip 4 are rounded. Thereby, the occurrence of chipping and cracks during the conveyance of the chip can be prevented, and the appearance defect can be reduced and the reliability can be improved.
  Further, a plurality of dots 39 made of concave portions are formed on the surface of the silicon substrate 1 which is the surface opposite to the surface on which the external connection terminals 25 are formed, and markings are formed by the dots 39.
[0060]
  FIG. 7 shows a method for manufacturing a semiconductor device.ExampleIt is process sectional drawing which shows a part of. In this embodiment, the chip shown in FIG. 6 is manufactured. Step (1) to step (10) have been described with reference to FIGS.Reference exampleThe explanation is omitted because it is almost the same. However, in this embodiment, laser marking for chip identification on the back surface of the wafer is not performed in step (10). Hereinafter, this embodiment will be described from step (11).
[0061]
(11) The wafer 2 having the photoresist 33 formed on the back surface 2b is aligned with the divided area of the wafer 2 using an IR aligner, and the photoresist 33 is exposed and developed to form the photoresist 33 in the divided area. Correspondingly, an opening 35 is formed, and an opening 41 is formed corresponding to the marking dot 39 (see FIG. 6) (see FIG. 7 (k)). The size of each opening 41 is, for example, the size of the resolution limit of photolithography. Further, the photoresist 33 has rounded corners corresponding to the shape of the chip formation region when viewed from the upper surface side.
[0062]
(12) With the surface protection tape 31 left, the wafer 2 is etched in the same manner as in the step (12) described with reference to FIG. Thereby, the wafer 2 in the separation region corresponding to the opening 35 is selectively removed to divide the wafer 2 into individual chips 4, and a recess is formed on the back surface 2 b of the wafer 2 corresponding to the opening 41. Dots 39 are formed. Since the size of the opening 41 is small, the etching rate of the wafer 2 in the region corresponding to the opening 41 is slower than that in the region corresponding to the opening 35, and the dots 39 do not penetrate the wafer 2 (FIG. 7 (l)). reference).
[0063]
(13) The photoresist 33 is removed by an asher (see FIG. 7 (m)).
(14) The surface 2 a side of the wafer 2 is irradiated with ultraviolet rays by an ultraviolet irradiator to eliminate the adhesive force of the surface protection tape 31. The chip 4 is pushed up by the pickup needle 37 to pick up the chip 4 that has been separated (see FIG. 7 (n)).
[0064]
Thus, since the chip 4 is cut out from the wafer 2 using the etching technique, the occurrence of chipping and cracks can be prevented. Furthermore, by cutting out the chip 4 from the wafer 2 using the photoresist 33 having the marking forming opening 41 in the formation area of the chip 4 as a mask, the chip 4 is cut out simultaneously with, for example, lot information or product information. Information can be recorded on the marking composed of dots 39, and the marking printing process can be eliminated.
[0065]
  FIG. 8 shows a semiconductor device.Other reference examples(A) is a top view, (B) is a side view.
  As shown in FIG. 4A, the corner portions 27 of the silicon substrate 1 and the photosensitive polyimide layer 21 forming the outer shape of the chip 4 are rounded. Thereby, the occurrence of chipping and cracks during the conveyance of the chip can be prevented, and the appearance defect can be reduced and the reliability can be improved.
  Further, a bar code 43 having an uneven shape is formed on one side surface of the chip 4. In the barcode 43, information such as lot information and product information is recorded, for example.
[0066]
  A method of manufacturing a semiconductor device for manufacturing this chip.Reference exampleWas described with reference to FIGS.Reference exampleIs almost the same. The difference is that, in the step (11) described with reference to FIG. 4 (k), an uneven shape corresponding to the barcode 43 is formed in the photoresist 33 in addition to the opening 35. Thereafter, the wafer 2 is selectively removed by using the photoresist 33 having a concavo-convex shape corresponding to the barcode 43 as a mask, so that the chip 4 is cut out from the wafer 2 and at the same time, the concavo-convex shape is formed on one side of the chip 4. A barcode 43 can be formed. Further, laser marking for chip identification on the back surface of the wafer in the step (10) described with reference to FIG. 4J may or may not be performed.
[0067]
  FIG. 9 shows still another example of the semiconductor device.Reference example(A) is a top view, (B) is a side view.
  As shown in FIG. 4A, the corners 27a and 27b of the silicon substrate 1 and the photosensitive polyimide layer 21 forming the outer shape of the chip 4 are rounded. Thereby, the occurrence of chipping and cracks during the conveyance of the chip can be prevented, and the appearance defect can be reduced and the reliability can be improved.
  Further, the corner portion 27a closest to the position of one pin, which is one of the external connection terminals 25, is formed to be larger in roundness than the other three corner portions 27b. Thereby, the position of 1 pin can be recognized from the size of the corner portions 27a and 27b.
[0068]
  A method of manufacturing a semiconductor device for manufacturing this chip.Reference exampleWas described with reference to FIGS.Reference exampleIs almost the same. The difference is that when forming the opening 35 in the photoresist 33 in the step (11) described with reference to FIG. 4 (k), the corner portion of the photoresist 33 in the region corresponding to the corner portion 27a is a corner. The opening 35 is formed so that the roundness is larger than the corner of the photoresist 33 in the region corresponding to the portion 27b. Thereafter, the wafer 2 is selectively removed using the photoresist 33 having different roundness at the corner as a mask, so that the chip 4 is cut out from the wafer 2 and the roundness at the corner 27a is changed. The chip 4 formed larger than the three corner portions 27b can be formed. Further, laser marking for chip identification on the back surface of the wafer in the step (10) described with reference to FIG. 4J may or may not be performed.
[0069]
  The embodiment shown in FIGS. 1 to 9And reference examplesThe photosensitive polyimide films 13 and 21 are used as the uppermost layer of the second interlayer insulating film 15 and the uppermost layer of the final protective film.And reference examplesHowever, the present invention is not limited to this, and other materials such as a thermoplastic resin film may be used instead of the photosensitive polyimide film.
  As mentioned above, although the Example of this invention was described, this invention is not limited to this, A various change is possible within the range of this invention described in the claim.
[0070]
【The invention's effect】
  In the method for manufacturing a semiconductor device according to claim 1, the dividing step has an opening corresponding to the divided region on one surface of the semiconductor wafer.,semiconductorRounded to correspond to the corners of the device forming areaIn addition, an opening for forming a marking is formed in the formation region of the semiconductor device.An etching stopper film is formed, and the semiconductor wafer is selectively removed by etching technique using the etching stopper film as a mask to be divided into individual semiconductor devices.At the same time, a marking consisting of one or a plurality of recesses is formed on the semiconductor device.Since it did in this way, generation | occurrence | production of a chipping and a crack can be prevented. Furthermore, since the corner portion of the semiconductor device after being cut out can be rounded, chipping and cracks can be prevented during the transportation of the semiconductor device, and the appearance defect is reduced and the reliability is improved. be able to.Furthermore, since the marking comprising one or a plurality of recesses can be formed on the semiconductor device after being cut out, simultaneously with the cutting out of the semiconductor device, for example, information such as lot information and product information can be recorded on the marking, The chip can be recognized by marking.
[0074]
  Claim2In the semiconductor device manufacturing method described in claim 1,1In the method of manufacturing a semiconductor device described in 1., one of the plurality of corner portions of the etching stopper film for each semiconductor device is rounded with a size different from that of the other corner portions. In the subsequent semiconductor device, a specific corner portion can be recognized from the roundness of the corner portion, and the orientation of the semiconductor device, for example, the position of one pin can be recognized.
[0075]
  Claim3In the manufacturing method of the semiconductor device described in the above, since the dry etching technique is used when the semiconductor wafer is selectively removed by using the etching stopper film as a mask by the etching technique, a plurality of semiconductors formed on the wafer are used. The interval between the devices can be significantly reduced as compared with the conventional dicing process, and the number of semiconductor devices that can be taken per wafer can be increased.
[0076]
  Claim4In the method of manufacturing a semiconductor device described in 1), after a tape material is pasted on the surface of the semiconductor wafer opposite to the surface on which the etching stopper film is formed, the semiconductor wafer on the side on which the etching stopper film is formed In the state where the surface of the semiconductor wafer is polished and the semiconductor wafer is adhered to the tape material, an etching stop film is formed on the polished surface of the semiconductor wafer, and the semiconductor wafer is divided into individual semiconductor devices. Since the thinned semiconductor wafer is supported by the tape material, it can be easily transported and the thickness of the semiconductor device can be reduced. Furthermore, since the dicing tape used in the prior art becomes unnecessary, it is possible to reduce waste in the manufacturing process.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating a reference example of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along a line AA in FIG.
FIG. 2 is a process cross-sectional view illustrating the beginning of a reference example of a method for manufacturing a semiconductor device;
FIG. 3 is a process sectional view illustrating a continuation of the reference example.
FIG. 4 is a process cross-sectional view showing the last of the reference example.
FIG. 5 is a plan view showing a photoresist used for dividing a wafer in the reference example.
FIG. 6 shows a semiconductor device.Reference example(A) is a top view, (B) is a side view.
FIG. 7 is a process sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device;
8A and 8B are diagrams showing another reference example of a semiconductor device, in which FIG. 8A is a plan view and FIG. 8B is a side view.
9A and 9B are diagrams showing still another reference example of the semiconductor device, in which FIG. 9A is a plan view and FIG. 9B is a side view.
FIG. 10 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
11A and 11B are diagrams showing a defect in a conventional method for manufacturing a semiconductor device, in which FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along the line AA in FIG.
[Explanation of symbols]
      1 Silicon substrate
      3 Underlying insulating layer
      5 First interlayer insulation layer
      7 First metal wiring layer
      9 PSG membrane
    11 SiN film
    13,21 Photosensitive polyimide layer
    15 Second interlayer insulating layer
    17 Through hole
    19 Second metal wiring layer
    23 Pad opening
    25 External connection terminal

Claims (4)

In a semiconductor device manufacturing method including a dividing step of dividing a semiconductor wafer on which a plurality of semiconductor devices are formed into individual semiconductor devices,
The dividing step has an opening corresponding to the divided region on one surface of the semiconductor wafer, roundness corresponding to a corner portion of the semiconductor device forming region shape, and marking formation in the semiconductor device forming region. Forming an etching stopper film having an opening for the semiconductor device, and selectively removing the semiconductor wafer by etching technique using the etching stopper film as a mask to divide the semiconductor wafer into individual semiconductor devices; A method of manufacturing a semiconductor device, comprising forming a marking comprising a recess.   2. The method of manufacturing a semiconductor device according to claim 1, wherein one of the plurality of corner portions of the etching stopper film for each semiconductor device is rounded with a size different from that of the other corner portions.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a dry etching technique is used when the semiconductor wafer is selectively removed using the etching stopper film as a mask.   After a tape material is attached to the surface of the semiconductor wafer opposite to the surface on the side where the etching stop film is formed, the surface of the semiconductor wafer on the side where the etching stop film is formed is polished, 4. The semiconductor device according to claim 1, wherein the etching stopper film is formed on a polished surface of the semiconductor wafer in a state of being attached to the tape material, and the semiconductor wafer is divided into individual semiconductor devices. 5. Production method.

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