JP2018195701A - Method of manufacturing semiconductor device - Google Patents

Abstract

To provide a method of manufacturing a semiconductor device capable of reducing the number of manufacturing steps by making a dicing step common to other steps.SOLUTION: A diode portion 11 and an element groove portion 10 are simultaneously formed by etching. That is, a dicing step of forming the dicing portion 11 is made common with a step of forming the element groove portion 10 of a semiconductor element. Thus, it is possible to make the dicing step common to other steps, and it is possible to obtain a semiconductor device manufacturing method capable of reducing the number of manufacturing steps.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor wafer is diced and divided into chips.

  Conventionally, the division of a semiconductor wafer into chips is performed by a dicing process after the formation of semiconductor elements is completed (see, for example, Patent Document 1). For example, the dicing process is performed by using a dicing dedicated apparatus such as a dicing saw, plasma dicing, and stealth dicing. Specifically, after the semiconductor wafer on which the element is formed is attached to the support material, the semiconductor wafer is cut using a dedicated dicing apparatus. Then, by separating each chip from the supporting material, a semiconductor device divided into chips is manufactured.

JP 2006-131178 A

  However, the conventional division of a semiconductor wafer into chip units involves performing the dicing process as a single process, and is necessary only for the dicing process, resulting in an increase in the number of manufacturing steps.

  In view of the above-described points, an object of the present invention is to provide a semiconductor device manufacturing method capable of reducing the number of manufacturing steps by sharing a dicing process with other processes.

  In order to achieve the above object, in the method of manufacturing a semiconductor device according to claim 1, an element formation region having a surface (1 a) and another surface (1 b) opposite to the surface and a semiconductor element is formed and dicing Preparing a semiconductor wafer (1) including a scribe region to be cut, disposing a support material (2) on one surface of the semiconductor wafer, and forming an element forming region on the other surface of the semiconductor wafer A mask (3) in which a first opening (3a) is formed at a position corresponding to, and a second opening (3b) is formed at a position corresponding to a scribe region, and is covered with a mask By etching the semiconductor wafer from the other side, the element groove (10) at the position corresponding to the first opening and the dicing section (11) at the position corresponding to the second opening of the semiconductor wafer are simultaneously formed. And forming includes.

  Thus, the dicing process for forming the dicing part is made common with the process for forming the element groove part of the semiconductor element. As a result, the dicing process can be shared with other processes, and the manufacturing method of the semiconductor device can reduce the number of manufacturing steps.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 1st Embodiment. It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 2nd Embodiment. It is the figure which showed the relationship between the line width of an etching part, and an etching rate. It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 3rd Embodiment. It is sectional drawing which showed the manufacturing process of the semiconductor device demonstrated by other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A method for manufacturing the semiconductor device according to the first embodiment will be described. As a semiconductor device to be manufactured, for example, a MEMS scanner device formed by using MEMS (Micro-Electro-Mechanical Systems) technology, that is, a variable laser scanner device that detects an obstacle by reflecting a microlaser with a MEMS mirror. Examples include a focus mirror. However, since the basic structure and manufacturing method of the semiconductor device are the same as those in the past, the detailed structure of the semiconductor element constituting the semiconductor device is not described here, and the portion of the semiconductor element related to dicing is omitted. Only will be described.

  Hereinafter, a part of the semiconductor element forming process and the dicing process in the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIG.

  First, as shown in FIG. 1A, a semiconductor wafer 1 having one surface 1a and another surface 1b opposite to the one surface 1a is prepared. About the semiconductor material which comprises the semiconductor wafer 1, although it selects according to the semiconductor element to form, silicon is used here. Then, by performing an element forming process similar to the conventional one on the semiconductor wafer 1, a semiconductor element is formed on the semiconductor wafer 1 to form an element forming region, and the semiconductor wafer 1 is diced to surround the periphery. A scribe area is formed as an area. However, not all of the semiconductor elements are formed, but the element groove portion 10 (see FIG. 1D described later) that penetrates the front and back of the semiconductor wafer 1 among the semiconductor elements is not formed.

  For example, when the semiconductor element is a variable focus mirror, the mirror unit of the variable focus mirror is provided with a support unit for the mirror unit, various driving units for driving the mirror unit, and the like. An element groove 10 penetrating the front and back of the semiconductor wafer 1 is formed between the various driving units. For this reason, in the variable focus mirror, processes other than the process of forming the element groove 10, such as patterning of the piezoelectric film and wiring layer for forming the mirror part and various driving parts, and various manufacturing such as formation of the insulating film layer, etc. Perform the process.

  Next, as shown in FIG. 1B, a support material 2 is disposed on one surface 1a of the semiconductor wafer 1 by pasting or the like. As the support material 2, an adhesive tape such as a dicing tape can be used, but here a conductor tape is used. The conductive tape is preferable because it can be easily performed by an electrostatic chuck using electrostatic attraction when attaching / detaching the stage to / from the stage of the etching apparatus.

  Then, as shown in FIG. 1C, a mask 3 is arranged on the other surface 1b side of the semiconductor wafer 1, and an opening 3a corresponding to the first opening is formed in a portion of the mask 3 corresponding to the element formation region. And an opening 3b corresponding to the second opening is formed in a portion corresponding to the scribe region. Thereafter, anisotropic etching using the mask 3 is performed to form the element trench 10 of the semiconductor element at a position corresponding to the opening 3a, and at the same time, penetrates along the scribe line to a position corresponding to the opening 3b. The dicing part 11 is formed. Thereby, the process for forming the element groove part 10 of the semiconductor element and the dicing process for forming the dicing part 11 can be made common.

Here, the opening width of the element groove portion 10, that is, the width in the left-right direction in the figure is made larger than the opening width in the same direction of the dicing portion 11, but this width can be arbitrarily set and the dimensional relationship is reversed. It may be. For anisotropic etching, for example, a reactive ion etching (RIE) method can be used. For example, if a so-called BOSCH method, in which C ₄ H ₈ and SF ₆ are alternately introduced repeatedly in an O ₂ atmosphere to repeatedly perform bottom etching and side wall protection with a polymer film, a so-called BOSCH method is used, the element groove portion 10 and dicing can be performed with a high aspect ratio. The part 11 can be formed.

  Thereafter, as shown in FIG. 1 (d), the support material 2 is peeled from the one surface 1 a of the semiconductor wafer 1. As a result, the semiconductor wafer 1 is divided into chips by the dicing part 11 and a semiconductor device having a structure in which the element groove part 10 is formed in the semiconductor element part of each chip is completed.

  As described above, the dicing process for forming the dicing part 11 is shared with the process for forming the element groove part 10 of the semiconductor element. As a result, the dicing process can be shared with other processes, and the manufacturing method of the semiconductor device can reduce the number of manufacturing steps.

  Here, a case where a semiconductor element is formed on the semiconductor wafer 1 is described as an example. However, it is not always necessary to manufacture the semiconductor element on the semiconductor wafer 1, and another semiconductor different from the semiconductor wafer 1 is used. A semiconductor element may be formed on a wafer (hereinafter referred to as another wafer). In this case, a bonded wafer obtained by bonding the semiconductor wafer 1 to another wafer is prepared, and after semiconductor elements are formed on the other wafer on the front surface side, the semiconductor wafer 1 on the back surface side is illustrated in FIG. The process of forming the element groove part 10 and the dicing part 11 shown in b) to (d) is performed. In that case, another wafer after the semiconductor elements are formed may be attached to the support material 2 and the semiconductor wafer 1 may be processed from the back side.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment will be described. In the present embodiment, the depth of the dicing unit 11 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  The manufacturing method of the semiconductor device of this embodiment is basically the same as that of the first embodiment, but is partially different. Specifically, in the present embodiment, the same steps are performed for the steps shown in FIGS. 1A, 1B, and 1D, and the steps shown in FIG. 1C are different from those of the first embodiment. As a process, the process shown in FIG. 2 is performed.

  That is, as shown in FIG. 2, the opening width of the opening 3b is made smaller than that in the first embodiment. And the element groove part 10 and the dicing part 11 are formed simultaneously by performing anisotropic etching. At this time, since the opening widths of the openings 3a and 3b are made different, the etching rate at the position where the dicing portion 11 is formed is higher than the position where the element groove portion 10 is formed due to the microloading effect due to the narrowing of the opening 3b. Become slow. For this reason, the dicing part 11 does not penetrate the semiconductor wafer 1 at this stage and can be stopped in the middle of the thickness direction of the semiconductor wafer 1.

  Specifically, the line width of the etching portion, in other words, the relationship between the opening width of the element groove portion 10 or the dicing portion 11 and the etching rate is expressed as a correlation diagram shown in FIG. Based on the relationship shown in this figure, the opening widths of the openings 3 a and 3 b are set so that the etching rate of the dicing part 11 is different from the element groove part 10. For example, in the case where the opening width of the element groove portion 10 is 30 μm or more, if the opening width of the dicing portion 11 is 10 μm or less, the etching rate becomes a difference of 2 μ / min or more. Based on this, the structure shown in FIG. 2 can be realized by setting the etching time so that the element groove portion 10 penetrates the semiconductor wafer 1 and the dicing portion 11 does not penetrate the semiconductor wafer 1.

  As described above, by controlling the depth of the dicing portion 11, it is possible to form the dicing portion 11 so as not to penetrate the semiconductor wafer 1.

  After the process shown in FIG. 2, the support material 2 is peeled off from the one surface 1 a of the semiconductor wafer 1, and stress can be applied to the semiconductor wafer 1, for example, to divide into chips. Alternatively, the dicing portion 11 may be penetrated by grinding a predetermined amount of the one surface 1a side of the semiconductor wafer 1.

  Further, it is not necessary to make all the opening widths of the dicing portion 11 equal, and the opening width is such that the depth does not penetrate the semiconductor wafer 1 as shown in FIG. 2, and the semiconductor wafer 1 is used for the remaining portions. It is good also as opening width used as the depth which penetrates. With such a configuration, in the scribe region, it is possible to reduce the number of connection portions that connect adjacent chips in the semiconductor wafer 1, that is, the portion remaining at the bottom of the dicing portion 11. Therefore, the connection location between adjacent chips can be made the same structure as the gate in the plastic model, and the structure can be easily cut by applying stress.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment will be described. In the present embodiment, the depth of the element groove portion 10 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different portions from the first embodiment will be described.

  The semiconductor device manufacturing method of this embodiment is basically the same as that of the first embodiment, but is partly different. Specifically, in the present embodiment, the same steps are performed for the steps shown in FIGS. 1A, 1B, and 1D, and the steps shown in FIG. 1C are different from those of the first embodiment. As a process, the process shown in FIG. 4 is performed.

  That is, as shown in FIG. 4, the opening width of the opening 3a is made smaller than the opening width of the opening 3b. And the element groove part 10 and the dicing part 11 are formed simultaneously by performing anisotropic etching. At this time, since the opening width of the opening portion 3a is smaller than that of the opening portion 3b, the position where the element groove portion 10 is formed rather than the position where the dicing portion 11 is formed due to the microloading effect due to narrowing of the opening portion 3a. Etching rate becomes slow. For this reason, the element groove portion 10 does not penetrate the semiconductor wafer 1 and can be stopped in the middle of the thickness direction of the semiconductor wafer 1.

  In FIG. 4, a plurality of openings 3a are provided and the openings 3a have the same opening width and are arranged at equal intervals. However, at least one of the openings 3a in a cross section different from FIG. The parts may be connected to each other, or the openings 3a may not be arranged at equal intervals. Further, the relationship between the line width of the etched portion and the etching rate is as shown in FIG. 3 as described above. Based on the relationship shown in this figure, the opening widths of the openings 3 a and 3 b are set so that the etching rate of the element groove 10 is slower than that of the dicing part 11. Thus, the structure shown in FIG. 3 can be realized in which the dicing portion 11 penetrates the semiconductor wafer 1 and the element groove portion 10 does not penetrate the semiconductor wafer 1.

  In this way, when it is desired to make the element groove portion 10 so as not to penetrate the semiconductor wafer 1, the dicing portion 11 can be formed so as not to penetrate the semiconductor wafer 1 by controlling the depth of the element groove portion 10. It becomes. For example, in the case of a variable focus mirror, when forming the structure on the other wafer side where the semiconductor element as described above is formed, a through groove such as the dicing portion 11 may be formed on the other wafer side. When manufacturing such a structure, it is preferable to apply a manufacturing method in which the element groove portion 10 has a depth that does not penetrate the semiconductor wafer 1 and the depth that the dicing portion 11 penetrates, as in the present embodiment.

  After the process shown in FIG. 2, the semiconductor wafer 1 can be divided into chips by peeling the support material 2 from the one surface 1 a of the semiconductor wafer 1.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the first and second embodiments, the structure in which only one element groove portion 10 is formed and the opening width of the element groove portion 10 is larger than the opening width of the dicing portion 11 has been described as an example. This is merely an example, and the number of element grooves 10 and the opening width can be changed as appropriate. When the opening widths of the element groove portion 10 and the dicing portion 11 are different, a difference may occur in the etching rate as shown in FIG. However, when it is desired to form both the element groove 10 and the dicing part 11 so as to penetrate the semiconductor wafer 1 as in the first embodiment, if the etching time is set in accordance with the etching rate on the side where the opening width is small, the element groove 10 and the dicing part 11 can both have a structure penetrating the semiconductor wafer 1.

1, 2, and 4 shown in the above embodiment are diagrams assuming that the element groove portion 10 and the dicing portion 11 are formed with a higher aspect ratio, for example, in the BOSCH method. In other words, in these drawings, the etching conditions and the conditions for protecting the side walls by the polymer film are set so that the side surfaces of the element groove portion 10 and the dicing portion 11 are perpendicular to the one surface 1a of the semiconductor wafer 1. However, this is only an example. For example, as shown in FIG. 5, etching is performed such that the side surfaces of the element groove 10 and the dicing portion 11 are inclined with respect to the one surface 1 a of the semiconductor wafer 1. Also good. Such a structure can be realized by increasing the thickness of the polymer film or shortening the bottom etching time as compared with the above embodiments.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a One surface 1b Other surface 2 Support material 3 Mask 3a Opening 3b Opening 10 Element groove part 11 Dicing part

Claims (4)

A semiconductor wafer (1) having one surface (1a) and the other surface (1b) opposite to the one surface and comprising an element formation region in which a semiconductor element is formed and a scribe region to be a dicing cut region is prepared. To do
Disposing a support material (2) on one side of the semiconductor wafer;
A mask in which a first opening (3a) is formed at a position corresponding to the element formation region on the other surface of the semiconductor wafer and a second opening (3b) is formed at a position corresponding to the scribe region ( 3) arranging,
The semiconductor wafer is etched from the other surface side while being covered with the mask, so that the element groove portion (10) at a position corresponding to the first opening in the semiconductor wafer corresponds to the second opening. Forming a position dicing portion (11) at the same time.   The method of manufacturing a semiconductor device according to claim 1, wherein in the simultaneous formation, both the element groove portion and the dicing portion are formed so as to penetrate the semiconductor wafer. In disposing the mask, the opening width of the second opening is made smaller than the opening width of the first opening,
In the simultaneous formation, the element groove is formed so as to penetrate the semiconductor wafer due to a difference in etching rate based on a difference in opening width between the first opening and the second opening. The method for manufacturing a semiconductor device according to claim 1, wherein the dicing portion is formed partway along a thickness direction of the semiconductor device. In disposing the mask, the opening width of the first opening is made smaller than the opening width of the second opening,
In the simultaneous formation, the dicing portion is formed so as to penetrate the semiconductor wafer due to a difference in etching rate based on a difference in opening width between the first opening and the second opening. The method for manufacturing a semiconductor device according to claim 1, wherein the element groove portion is formed halfway in the thickness direction.

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