JP6646820B2 - Device chip manufacturing method - Google Patents

Description

  The present invention relates to a device chip manufacturing method for manufacturing a device chip by dividing a substrate having a plurality of device regions into device regions.

  BACKGROUND ART An element chip such as a semiconductor element is manufactured by being divided into individual pieces from a wafer-like substrate having a plurality of element regions (for example, see Patent Document 1). In the prior art disclosed in this patent document, first, the back surface of a wafer on which a circuit is formed is polished while the front surface of the wafer is attached to a dicing tape, and the wafer is thinned by etching. Thereafter, a resist layer is formed on a portion corresponding to the element region, masking is performed, and plasma etching is performed to separate the wafer into individual semiconductor elements.

JP-A-2002-93752

  Individual chip chips cut out from a wafer-shaped substrate as described above are packaged and used as device devices, or sent to the electronic component mounting process in the form of element chips such as flip chips. There is. In such a case, the element chip is mounted in such a manner that the circuit formation surface is brought into direct contact with a conductive material such as cream solder or silver paste for bonding. In this mounting process, a so-called “creeping up” may occur in which the conductive material that has been spread when the element chip is mounted spreads not only on the bonding portion of the circuit forming surface but also on the side surface and the back surface of the element chip. Such creeping up of the conductive material causes various problems such as a short circuit between adjacent electrodes and an unnecessary electric circuit formed on the side surface of the element chip to increase current consumption. For this reason, it has been demanded to suppress the conductive material from creeping up in such a mounting process.

  Therefore, an object of the present invention is to provide a method of manufacturing an element chip capable of suppressing a rise of a conductive material in a mounting process.

  The method for manufacturing an element chip according to the present invention includes the steps of: providing a substrate having a first surface having a plurality of element regions defined by divided regions and a second surface opposite to the first surface in the divided regions. A method for manufacturing an element chip, which is divided into a plurality of element chips, wherein a side of the first surface is supported by a carrier, and a region of the second surface opposite to the element region is covered; A preparing step of preparing the substrate on which the etching resistant layer is formed so as to expose a region of the second surface opposite to the divided region, and after the preparing step, the substrate supported by the carrier A plasma processing step of performing a plasma processing, wherein the plasma processing step includes exposing the second surface to a first plasma to reduce a depth of the substrate in a region not covered with the etching resistant layer. In the first direction The substrate is divided into element chips by etching until reaching a surface, and the element chip including the first surface, the second surface, and a side surface connecting the first surface and the second surface is formed by the carrier. A dividing step in which the element chips are held at intervals above, and after the dividing step, by exposing the element chips to a second plasma while being held at an interval on the carrier, The method includes a protective film forming step of forming a protective film on the side surface of the element chip, wherein the dividing step and the protective film forming step are performed in the same processing chamber provided in a plasma etching apparatus.

  The method for manufacturing an element chip according to the present invention includes the steps of: providing a substrate having a first surface having a plurality of element regions defined by divided regions and a second surface opposite to the first surface in the divided regions. What is claimed is: 1. A method for manufacturing an element chip, comprising forming a plurality of element chips by dividing, wherein an etching-resistant layer is formed so that a side of the second surface is supported by a carrier and covers the element region and exposes the divided region. A preparing step of preparing the substrate on which is formed, and a plasma processing step of performing a plasma processing on the substrate supported by the carrier after the preparing step, further comprising the first plasma processing step. By exposing the surface to the first plasma, the substrate in an area not covered with the etching resistant layer is etched in a depth direction of the substrate until the second surface is reached, and the substrate is subjected to an element chip. Dividing into a state in which the element chips including the first surface, the second surface, and the side surface connecting the first surface and the second surface are held on the carrier at intervals. A dividing step, and after the dividing step, a protective film is formed on the side surface of the element chip by exposing the element chip to a second plasma while being held on the carrier with an interval therebetween. The method includes a protective film forming step, wherein the dividing step and the protective film forming step are performed in the same processing chamber provided in the plasma etching apparatus.

  ADVANTAGE OF THE INVENTION According to this invention, the creeping-up of the conductive material in the mounting process can be suppressed.

Process explanatory view of the first example in the method of manufacturing an element chip according to one embodiment of the present invention Process explanatory view of the first example in the method of manufacturing an element chip according to one embodiment of the present invention Configuration explanatory view of a plasma etching apparatus used in a method of manufacturing an element chip according to an embodiment of the present invention Configuration explanatory view of an element chip manufactured by the first example in the method of manufacturing an element chip according to one embodiment of the present invention. Process explanatory diagram of the second example in the method of manufacturing an element chip according to one embodiment of the present invention Process explanatory diagram of the second example in the method of manufacturing an element chip according to one embodiment of the present invention Configuration explanatory view of an element chip manufactured by the second example in the method of manufacturing an element chip according to one embodiment of the present invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. First, a first example of the method for manufacturing an element chip according to the present embodiment will be described with reference to FIGS. The method of manufacturing an element chip shown here includes a method of forming a substrate having a first surface having a plurality of element regions defined by divided regions and a second surface opposite to the first surface in the divided regions. A plurality of element chips are formed by division.

  As shown in FIG. 1A, a substrate 1 is a wafer-like substrate in which a plurality of element chips 10 having an element section 2 (see FIG. 1C) are formed. A plurality of element regions 2a defined by divided regions 1c are set on a first surface 1a which is an element surface on which the element unit 2 is formed on the substrate 1. The substrate 1 is sent to a preparation process for manufacturing an element chip, and is supported by a carrier 4 and a mask is formed as described below. As the carrier 4, a carrier such as an adhesive sheet or a support substrate which can fix and handle the thin and flexible substrate 1 is used.

  In this preparation step, as shown in FIG. 1B, the first surface 1a side of the substrate 1 is supported by the holding surface 4a of the carrier 4, and the second surface 1b functions as a mask in plasma dicing. The etching resistant layer 3 is formed by a resist mask, a surface protection film, or the like. That is, the etching-resistant layer 3 is formed on the second surface 1b so as to cover the region of the second surface 1b facing the element region 2a and expose the region 1d of the second surface 1b facing the divided region 1c. It is formed.

  After the preparation step is performed in this manner, the carrier 4 is sent to the plasma processing step to perform the plasma processing on the substrate 1 supported on the carrier 4. The configuration of the plasma etching apparatus 20 used in this plasma processing step will be described with reference to FIG. In FIG. 3, the inside of a chamber 21, which is a vacuum vessel, is a processing chamber 21a for performing plasma processing, and a stage 22 on which a carrier 4 supporting the substrate 1 to be processed is placed is disposed at the bottom of the processing chamber 21a. Have been. An antenna 23 as an upper electrode is disposed on the upper surface of the top of the chamber 21, and the antenna 23 is electrically connected to a first high-frequency power supply unit 24. The stage 22 in the processing chamber 21a also has a function as a lower electrode for plasma processing, and the stage 22 is electrically connected to the second high-frequency power supply unit 25.

  A vacuum exhaust unit 27 is connected to the chamber 21 via an exhaust port 21c, and the inside of the processing chamber 21a is evacuated by driving the vacuum exhaust unit 27. Further, the processing chamber 21a is connected to a plasma generating gas supply unit 26 via a gas inlet 21b. In the plasma etching apparatus 20 described in the present embodiment, it is possible to selectively supply a plurality of types of plasma generating gases according to the purpose of the plasma processing. Here, the first gas 26a, the second gas 26b, the third gas 26c, and the ashing gas 26d can be selected as types of the plasma generation gas.

The first gas 26a, such as SF ₆ and _C 4 _{F 8,} is used has excellent etching effect of interest silicon. In the present embodiment, the first gas 26a is used to generate a first plasma P1 for dividing the substrate 1 by plasma etching. As the second gas 26b, a mixed gas of carbon fluoride and helium such as C ₄ F ₈ , C ₂ F ₆ , CF ₄ , C ₆ F ₆ , C ₆ F ₄ H ₂ , CHF ₃ , CH ₂ F ₂ Is used. These gases are used as plasma CVD gases for forming a film by plasma processing. In the present embodiment, they are used for the purpose of forming a protective film on the side surface of the element chip 10 obtained by dividing the substrate 1. Note that the ratio of the helium flow rate to the total flow rate of the mixed gas is appropriately set according to the combination of gas types. As an example, the ratio of helium to the total flow rate of the mixed gas may be 10% to 80%.

  As the third gas 26c, a gas having an excellent physical etching effect such as an oxygen gas or an argon gas is used. In the present embodiment, the protective film is used for sputtering for removing an unnecessary portion of the protective film. The ashing gas 26d is an oxygen gas, and is used in the present embodiment for the purpose of removing the resin film such as the etching-resistant layer 3 after completing the mask function.

  In the plasma processing by the plasma etching apparatus 20, first, the substrate 1 to be processed is placed on the stage 22 together with the carrier 4, and the vacuum exhaust unit 27 is driven to evacuate the processing chamber 21a. At the same time, a plasma generation gas corresponding to the purpose of the plasma processing is supplied into the processing chamber 21a by the plasma generation gas supply unit 26 and maintained at a predetermined pressure. In this state, high-frequency power is supplied to the antenna 23 by the first high-frequency power supply unit 24, so that plasma is generated in the processing chamber 21a in accordance with the type of the supplied plasma generating gas. At this time, by applying a bias voltage to the stage 22 as a lower electrode by the second high-frequency power supply unit 25, a bias action for promoting incidence of plasma generated in the processing chamber 21a in the direction of the stage 22 is performed. The anisotropic etching can be performed by enhancing the plasma processing effect in a desired specific direction.

  In the plasma processing step, first, the processing by the first plasma P1 using the above-described first gas 26a is performed. As shown in FIG. 1C, by exposing the second surface 1b of the substrate 1 to the above-described first plasma P1, a region 1d not covered with the etching resistant layer 3 (see FIG. 1B). The substrate 1 is etched in the depth direction of the substrate 1 until the first surface 1a is reached (see arrow e), and an etching groove 11 (see FIG. 2A) separating each element chip 10 is formed. The substrate 1 is divided into individual element chips 10. That is, in the state of the substrate 1, the first surface 10a was the first surface 1a, the second surface 10b was the second surface 1b, and the side surface connecting the first surface 10a and the second surface 10b. The element chips 10 provided with 10c are held on the carrier 4 at an interval from each other (dividing step).

  The etching conditions in the dividing step can be appropriately selected according to the material of the substrate 1. When the substrate 1 is a silicon substrate, a so-called Bosch process can be used for the etching in the dividing step. In the Bosch process, by sequentially repeating a deposited film deposition step, a deposited film etching step, and a silicon etching step, a region 1d not covered with the etching resistant layer 3 can be dug vertically in the depth direction of the substrate. it can.

The conditions of the deposited film deposition step include, for example, adjusting the pressure in the processing chamber 21a to 15 to 25 Pa while supplying C ₄ F ₈ at 150 to 250 sccm as a source gas, and The input power to the lower electrode 23 may be 1500 to 2500 W, the power input to the lower electrode from the second high-frequency power supply unit 25 may be 0 W, and the processing time may be 5 to 15 seconds. As the conditions of the deposited film etching step, for example, while supplying SF ₆ at 200 to 400 sccm as a source gas, the pressure in the processing chamber 21 a is adjusted to 5 to 15 Pa, and the first high frequency power supply unit 24 , The input power from the second high-frequency power supply unit 25 to the lower electrode is 100 to 300 W, and the processing time is 2 to 10 seconds.

As the conditions of the silicon etching step, for example, while supplying SF ₆ at 200 to 400 sccm as a source gas, the pressure in the processing chamber 21 a is adjusted to 5 to 15 Pa, and the pressure from the first high-frequency power supply unit 24 to the antenna 23 is adjusted. The input power may be 1500 to 2500 W, the input power from the second high frequency power supply unit 25 to the lower electrode may be 50 to 200 W, and the processing time may be 10 to 20 seconds. Then, under these conditions, the silicon substrate can be dug at a speed of 10 μm / min by repeating the deposited film deposition step, the deposited film etching step, and the silicon etching step.

  Thereafter, ashing is performed to remove the etching-resistant layer 3 covering the second surface 10b of the individual element chip 10. That is, as shown in FIG. 2A, an ashing plasma using an ashing gas 26d is generated in a processing chamber 21a in a plasma etching apparatus 20, and the etching resistant layer 3 containing a resin as a main component is removed by ashing. I do. As a result, the second surface 10b of the element chip 10 divided into individual pieces is exposed.

Ashing conditions can be appropriately selected according to the material of the etching-resistant layer 3. For example, when the etching-resistant layer 3 is a resist film, the pressure in the processing chamber 21a is adjusted to 5 to 15 Pa while supplying oxygen as a source gas at 150 to 250 sccm and CF ₄ at 0 to 50 sccm, and The input power from the power supply unit 24 to the antenna 23 may be 1500 to 2500 W, and the input power from the second high-frequency power supply unit 25 to the lower electrode may be 0 to 30 W. Under these conditions, the etching resistant layer 3 can be removed at a speed of about 1 μm / min.

  Next, after the above dividing step, a protective film forming step is performed. That is, in the plasma etching apparatus 20, a second plasma P2 using a second gas 26b that is a mixed gas of fluorocarbon and helium is generated in the processing chamber 21a, and as shown in FIG. The element chip 10 is exposed to the second plasma P2 while being held on the carrier 4 at a distance from each other. As a result, protective films 12b and 12c are formed on the second surface 10b and the side surface 10c of the element chip 10, respectively.

  Since these protective films are formed for the purpose of suppressing creeping up of the conductive material in the mounting process of directly bonding the element chip 10 to a package substrate or the like, the protective films have a low hygroscopicity and a dense composition. It is desired that In the present embodiment, since a mixed gas of carbon fluoride and helium is used as a source gas of the second plasma P2 used for forming these protective films, a fluorocarbon film containing fluorine and carbon is used as the protective film. It is possible to form a protective film that is formed, has a low composition, is dense and has excellent adhesion. In this protective film forming step, a high frequency bias is applied to the stage 22 (see FIG. 3) on which the carrier 4 is placed. Thereby, the incidence of ions on the element chip 10 is promoted, and a denser and highly adherent protective film can be formed.

As a condition for forming the protective film, for example, while supplying C ₄ F ₈ as a source gas at 150 sccm and He at 50 sccm, the pressure in the processing chamber 21 a is adjusted to 15 to 25 Pa, and the first high-frequency power supply unit 24 The input power to the antenna 23 may be 1500 to 2500 W, and the input power from the second high-frequency power supply unit 25 to the lower electrode may be 50 to 150 W. By performing the treatment under these conditions for 300 seconds, a protective film having a thickness of 3 μm can be formed.

  In the present embodiment, a mixed gas of fluorocarbon and helium is used as a source gas. By mixing helium, separation of the source gas in plasma is promoted, and as a result, This is because a protective film having high adhesion can be formed.

In the above condition example, the ratio of the He flow rate to the total flow rate of the source gas is 25% (= 50 / (150 + 50) × 100). This ratio is preferably between 10% and 80%, as described below. That is, when the ratio of the He flow rate to the total flow rate of the source gas is greater than 10%, the separation of the source gas in the plasma is easily promoted, and as a result, a denser and highly adherent protective film is easily formed. On the other hand, when the ratio of the He flow rate to the total flow rate of the source gas is greater than 80%, the ratio of C ₄ F _{8 in} the source gas decreases, so that the components (C, F and Insufficient supply of these compounds) to the substrate surface slows down the deposition rate of the protective film on the substrate surface, and lowers productivity.

  Next, a protective film removing step for removing unnecessary portions of the protective film formed in the protective film forming step is performed. In the above-described protective film forming step, the protective film 12b is formed on the second surface 10b together with the side surface 10c of the element chip 10 (see FIG. 2B). Since the protective film 12b is unnecessary, a plasma process using the third plasma P3 for removing the protective film 12b is performed.

  That is, in the plasma etching apparatus 20, a third plasma P3 using a third gas 26c containing an argon gas or an oxygen gas as a component is generated in the processing chamber 21a, and as shown in FIG. The element chip 10 is exposed to the third plasma P3 while being held at an interval on the element 4. As a result, the protection film 12c formed on the side surface 10c of the element chip 10 is left, and the protection film 12b formed on the second surface 10b exposed on the upper surface of the element chip 10 is etched by the third plasma P3. To remove. As a result, the second surfaces 10b of the element chips 10 held on the carrier 4 with a space therebetween are exposed, and the protective film 12e attached to the upper surface of the carrier 4 is also removed.

  In the above protective film removing step, a high frequency bias is applied to the stage on which the carrier 4 is placed. This makes it possible to increase the anisotropy of the etching action of the third plasma P3. Therefore, it is possible to reliably remove the protective film 12b on the second surface 10b exposed on the upper surface, suppress the etching effect on the protective film 12c on the side surface 10c of the element chip 10, and leave the protective film 12c. It has become.

The conditions of the protective film removed, for example, 150～250Sccm the Ar as a source gas while supplying _{O 2} at 0～150Sccm, to adjust the pressure in the processing chamber 21a to 0.2～1.5Pa, first The input power from the high-frequency power supply unit 24 to the antenna 23 may be 1500 to 2500 W, and the input power from the second high-frequency power supply unit 25 to the lower electrode may be 150 to 300 W. Under this condition, the protective film exposed on the upper surface can be etched at a speed of about 0.5 μm / min.

  FIG. 4 shows a variation of the element chip 10 manufactured by such a manufacturing process. The element chip 10A shown in FIG. 4A shows the element chip 10 after the protection film forming step shown in FIG. 2B, and includes not only the protection film 12c formed on the side surface 10c but also the second surface 10b. The protective film 12b remains. The element chip 10B shown in FIG. 4B shows the element chip 10 after the protective film removing step shown in FIG. 2B, and the protective film 12b has been removed from the second surface 10b. At this time, the upper end of the protective film 12c formed on the side surface 10c is a removed portion 12c * in which the outer edge is partially removed by the third plasma etching action.

  In the element chip 10C shown in FIG. 4C, the range of removing the upper end of the protective film 12c formed on the side surface 10c is enlarged to form an exposed portion 10e in which the upper end of the side surface 10c is exposed. Things. Further, in the element chip 10D shown in FIG. 4D, the end of the exposed portion 10e where the upper end of the side surface 10c is exposed is removed by etching to form a corner cut portion 10e *.

  Each of these element chips 10A to 10D has a first surface 10a including an element region 2a in which an element portion 2 is formed, a second surface 10b opposite to the first surface 10a, and a first surface 10a. And a side surface 10c connecting the second surface 10b. In the element chips 10A to 10D having the above-described configuration, a protective film 12c having a surface property for suppressing the spread of the conductive adhesive material is formed at least in a range where the conductive adhesive material contacts in the mounting process on the side surface 10c. Therefore, it is possible to suppress the conductive material from rising during the mounting process. Further, since the element chip 10D includes the corner cut portion 10e *, the bending strength of the element chip can be improved.

  Next, a second example of the method for manufacturing an element chip according to the present embodiment will be described with reference to FIGS. 5, 6, and 7. FIG. Here, the manufacturing method of the element chip shown in the second embodiment is similar to that of the first embodiment, and has a first surface having a plurality of element regions defined by divided regions, and a method opposite to the first surface. And a plurality of element chips formed by dividing the substrate having the second surface on the side in the divided region.

  As shown in FIG. 5A, the substrate 1 is a wafer-like substrate in which a plurality of element chips 10 each having an element portion 2 (see FIG. 5C) are formed. A plurality of element regions 2a defined by divided regions 1c are set on a first surface 1a which is an element surface on which the element unit 2 is formed on the substrate 1. The substrate 1 is sent to a preparation process for manufacturing an element chip, where the carrier 4 supports and forms a mask, as described below. As in the first embodiment, a carrier that can fix and handle the thin and flexible substrate 1 such as an adhesive sheet or a support substrate is used as the carrier 4.

  In this preparation step, as shown in FIG. 5B, the side of the second surface 1b of the substrate 1 is supported by the holding surface 4a of the carrier 4, and the first surface 1a functions as a mask in plasma dicing. An etching resistant layer 3 is formed. That is, the etching resistant layer 3 is formed on the first surface 1a so as to cover the element region 2a and expose the divided region 1c.

  After the preparation step is performed in this manner, the carrier 4 is sent to the plasma processing step to perform the plasma processing on the substrate 1 supported on the carrier 4. In this plasma processing step, the plasma etching apparatus 20 (see FIG. 3) described in the first embodiment is used.

  In the plasma processing step, first, processing using the first plasma P1 using the first gas 26a is performed. As shown in FIG. 5C, by exposing the first surface 1a of the substrate 1 to the above-described first plasma P1, a divided region 1c not covered with the etching resistant layer 3 (see FIG. 5B). ) Is etched in the depth direction of the substrate 1 until it reaches the second surface 1b (see arrow e), and an etching groove 11 (see FIG. 6A) separating each element chip 10 is formed. Then, the substrate 1 is divided into individual element chips 10. That is, in the state of the substrate 1, the first surface 10a was the first surface 1a, the second surface 10b was the second surface 1b, and the side surface connecting the first surface 10a and the second surface 10b. The element chips 10 provided with 10c are held on the carrier 4 at an interval from each other (dividing step).

  Thereafter, ashing is performed to remove the etching-resistant layer 3 covering the second surface 10b of the individual element chip 10. That is, as shown in FIG. 6A, ashing plasma using an ashing gas 26d is generated in the processing chamber 21a in the plasma etching apparatus 20, and the etching resistant layer 3 containing resin as a main component is removed by ashing. I do. As a result, the second surface 10b of the element chip 10 divided into individual pieces is exposed.

  Next, after the above dividing step, a protective film forming step is performed. That is, in the plasma etching apparatus 20, the second plasma P2 using the second gas 26b, which is a mixed gas of fluorocarbon and helium, is generated in the processing chamber 21a, and as shown in FIG. The element chip 10 is exposed to the second plasma P2 while being held on the carrier 4 at a distance from each other. As a result, protective films 12a and 12c are formed on the first surface 10a and the side surface 10c of the element chip 10, respectively.

  The advantages and effects of using a mixed gas of fluorocarbon and helium as the source gas for the second plasma P2 in forming these protective films are the same as in the first embodiment. In this protective film forming step, a high frequency bias is applied to the stage on which the carrier 4 is placed. Thereby, the incidence of ions on the element chip 10 is promoted, and a more dense and highly adherent protective film can be formed.

  Next, a protective film removing step for removing unnecessary portions of the protective film formed in the protective film forming step is performed. In the above-described protective film forming step, the protective film 12a is formed on the first surface 10a together with the side surface 10c of the element chip 10 (see FIG. 6B). Since the protective film 12a is unnecessary, a plasma process using the third plasma P3 for removing the protective film 12a is performed.

  That is, in the plasma etching apparatus 20, a third plasma P3 using the third gas 26c containing an argon gas or an oxygen gas as a component is generated in the processing chamber 21a, and as shown in FIG. The element chip 10 is exposed to the third plasma P3 while being held at an interval on the element 4. Thereby, the protective film 12c formed on the side surface 10c of the element chip 10 is left, and the protective film 12a formed on the first surface 10a exposed on the upper surface of the element chip 10 is etched by the third plasma P3. To remove. As a result, the first surfaces 10a of the element chips 10 held on the carrier 4 with a space therebetween are exposed, and the protective film 12e attached to the upper surface of the carrier 4 is also removed.

  In the above protective film removing step, a high frequency bias is applied to the stage on which the carrier 4 is placed. This makes it possible to increase the anisotropy of the etching action of the third plasma P3. Therefore, it is possible to reliably remove the protective film 12a on the first surface 10a exposed on the upper surface, suppress the etching effect on the protective film 12c on the side surface 10c of the element chip 10, and leave the protective film 12c. It has become.

  FIG. 7 shows a variation of the element chip 10 manufactured by such a manufacturing process. The element chip 10A shown in FIG. 7A shows the element chip 10 after the protection film forming step shown in FIG. 5B, and not only the protection film 12c formed on the side surface 10c but also the first surface 10a. The protective film 12a remains. The device chip 10B shown in FIG. 7B shows the device chip 10 after the protection film removing step shown in FIG. 5B, and the protection film 12a has been removed from the first surface 10a. At this time, the upper end of the protective film 12c formed on the side surface 10c is a removed portion 12c * in which the outer edge is partially removed by the third plasma etching action.

  Also, in the element chip 10C shown in FIG. 7C, the range of removing the upper end of the protective film 12c formed on the side surface 10c is enlarged, and the element chip 2C formed on the upper end of the first surface 10a is removed. An exposed portion 2c whose side end is exposed is formed. Further, in an element chip 10D shown in FIG. 7D, an end of the exposed portion 2c is removed by etching to form a corner cut portion 2c *.

  Each of these element chips 10A to 10D has a first surface 10a including an element region in which the element portion 2 is formed, a second surface 10b opposite to the first surface 10a, a first surface 10a, It has a side surface 10c connecting the second surface 10b. In the element chips 10A to 10D having the above-described configuration, since the protective film 12c is formed at least on the side surface 10c in a range that comes into contact with the conductive adhesive material during the mounting process, the conductive material is prevented from rising during the mounting process. Thus, the same effect as in the first embodiment can be obtained. Further, since the element chip 10D includes the corner cut portion 2c *, the bending strength of the element chip can be improved.

  The method for manufacturing an element chip according to the present invention has an effect of suppressing the rise of a conductive material in a mounting process, and manufactures an element chip by dividing a substrate having a plurality of element regions into element regions. It is useful in the field which does.

DESCRIPTION OF SYMBOLS 1 Substrate 1a 1st surface 1b 2nd surface 1c Division area 2 Element part 2a Element area 3 Etching-resistant layer 4 Carrier 10 Element chip 10a 1st surface 10b 2nd surface 10c Side surface 12a, 12b, 12c Protective film

Claims (6)

A substrate including a first surface having a plurality of element regions defined by a divided region and a second surface opposite to the first surface is divided by the divided region to form a plurality of element chips. A method for manufacturing an element chip, comprising:
The first surface side is supported by a carrier, and covers a region of the second surface opposite to the element region and exposes a region of the second surface opposite to the division region. A preparing step of preparing the substrate on which the etching resistant layer is formed,
After the preparing step, a plasma processing step of performing a plasma processing on the substrate supported by the carrier,
The plasma processing step,
By exposing the second surface to the first plasma, the substrate in an area not covered with the etching resistant layer is etched in the depth direction of the substrate until the first surface is reached, and the substrate is etched. An element chip divided into element chips and having the first surface, the second surface, and a side surface connecting the first surface and the second surface was held at intervals on the carrier. A dividing step to be in a state,
After the dividing step, exposing the element chip to a second plasma while being held at an interval on the carrier to form a protective film on the side surface of the element chip. Become
A method for manufacturing an element chip, wherein the dividing step and the protective film forming step are performed in the same processing chamber provided in a plasma etching apparatus.   2. The method according to claim 1, wherein a high frequency bias is applied to a stage on which the carrier is placed in the protective film forming step.   The method for manufacturing an element chip according to claim 1, wherein a source gas of the second plasma includes carbon fluoride. A substrate including a first surface having a plurality of element regions defined by a divided region and a second surface opposite to the first surface is divided by the divided region to form a plurality of element chips. A method for manufacturing an element chip, comprising:
A step of preparing the substrate on which the side of the second surface is supported by a carrier, and on which the etching-resistant layer is formed so as to cover the element region and expose the divided region;
After the preparing step, a plasma processing step of performing a plasma processing on the substrate supported by the carrier,
Further, the plasma processing step includes:
By exposing the first surface to the first plasma, the substrate in a region not covered with the etching-resistant layer is etched in a depth direction of the substrate until the second surface is reached, thereby etching the substrate. An element chip divided into element chips and having the first surface, the second surface, and a side surface connecting the first surface and the second surface was held at intervals on the carrier. A dividing step to be in a state,
A protection film forming step of forming a protection film on the side surface of the element chip by exposing the element chip to a second plasma in a state where the element chip is held on the carrier at an interval after the division step; And
A method for manufacturing an element chip, wherein the dividing step and the protective film forming step are performed in the same processing chamber provided in a plasma etching apparatus.   The method according to claim 4, wherein a high-frequency bias is applied to a stage on which the carrier is placed in the protective film forming step.   The method for manufacturing an element chip according to claim 4, wherein the source gas of the second plasma includes fluorocarbon.

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