CN108417498A - A kind of packaging method and encapsulation chip of chip - Google Patents

A kind of packaging method and encapsulation chip of chip Download PDF

Info

Publication number
CN108417498A
CN108417498A CN201810209472.6A CN201810209472A CN108417498A CN 108417498 A CN108417498 A CN 108417498A CN 201810209472 A CN201810209472 A CN 201810209472A CN 108417498 A CN108417498 A CN 108417498A
Authority
CN
China
Prior art keywords
chip
electrode
packaging method
high temperature
temperature resistant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810209472.6A
Other languages
Chinese (zh)
Inventor
丁荣峥
朱玲华
李秀林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 58 Research Institute
Original Assignee
CETC 58 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 58 Research Institute filed Critical CETC 58 Research Institute
Priority to CN201810209472.6A priority Critical patent/CN108417498A/en
Publication of CN108417498A publication Critical patent/CN108417498A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A kind of packaging method and encapsulation chip of chip are provided in the present invention, belong to technical field of electronic encapsulation.By etching electroded lead frame, and high temperature resistant glued membrane is sticked on the lead frame；Chip is pasted on the high temperature resistant glued membrane；The gap between chip and electrode is filled up, and is ground until electrode exposes；Take the high temperature resistant glued membrane off, coating is coated in plating on the surface that electrode exposes；Weld tabs is sticked from chip exit pad in the coplanar printing solder mask of electrode and solder layer, carries out Reflow Soldering；It is cut and isolates finished goods.The packaging method step is simple, and chip functions area exposes completely, and encapsulation interconnection resistance is small, and package dimension is small；Packaging technology can be realized using existing process equipment and material.

Description

A kind of packaging method and encapsulation chip of chip
Technical field
The present invention relates to technical field of electronic encapsulation, more particularly to the packaging method and encapsulation chip of a kind of chip.
Background technology
The functional areas of the chips such as semiconductor resistor bridge, all kinds of highly sensitive gas detectors, photoelectricity and radiation detector need It is exposed to guarantee to reach using function and more preferably performance.Existing encapsulation is to use metal shell or ceramic shell （Such as TO types metal shell, surface install ceramics CLCC/CQFN/CDFN shells）, all kinds of ceramics or organic substrate etc. pass through core Piece bonding, wire（Such as spun gold/gold ribbon or aluminium wire/aluminium strip）Bonding interconnection, then will interconnect wire package with insulating cement（Packet Include chip pressure welding pad）And assurance function area is exposed.That there are package dimensions is big for this method, and encapsulation step is more, encapsulation effect The shortcomings of rate is low, and packaging cost is high.
Invention content
The purpose of the present invention is to provide a kind of packaging method of chip and encapsulation chips, to solve existing chip package It is oversized, the problems such as packaging efficiency is low, of high cost.
In order to solve the above technical problems, the present invention provides a kind of packaging method of chip, include the following steps：
Step 1 etches electroded lead frame, and sticks high temperature resistant glued membrane on the lead frame；
Chip is pasted on the high temperature resistant glued membrane by step 2；
Step 3 fills up the gap between chip and electrode, and grinds until electrode exposes；
Step 4 takes the high temperature resistant glued membrane off；
Step 5, on the surface that electrode exposes, coating is coated in plating；
Step 6 sticks weld tabs from chip exit pad in the coplanar printing solder mask of electrode and solder layer, carries out Reflow Soldering；
Step 7 is cut and isolates finished goods.
Optionally, the lead frame be including copper alloy and iron-nickel alloy can wet etching material.
Optionally, in the step 2, the functional area of chip facing towards high temperature resistant glued membrane.
Optionally, the gap between chip and electrode is filled up using moulding compound or filling glue in the step 3.
Optionally, the distribution of electrodes is around chip, and identical as chip thickness.
Optionally, the material of the high temperature resistant glued membrane is polyimides.
Optionally, the coating is the Ni-Pd-Au or thickness that tin layers of the thickness not less than 7 μm or thickness are not less than 1 μm Ni-Au not less than 1 μm.
Optionally, it is with 245 DEG C ~ 260 DEG C Reflow Solderings for carrying out 45s ~ 240s in the step 6.
The present invention also provides a kind of encapsulation chip prepared according to above-mentioned packaging method, the encapsulation chip includes core Piece, filler material, electrode, solder layer and solder mask；For the chip gripper between multiple electrodes, chip includes functional areas, end pad； The end pad and electrode and coating are interconnected by solder layer, and chip functions area is exposed；The chip and electricity Pole is bonded integral by filler material.
Optionally, the filler material is moulding compound or filling glue.
A kind of packaging method and encapsulation chip of chip are provided in the present invention, by etching electroded lead frame Frame, and high temperature resistant glued membrane is sticked on the lead frame；Chip is pasted on the high temperature resistant glued membrane；Fill up chip and electricity Gap between pole, and grind until electrode exposes；Take the high temperature resistant glued membrane off, plating is coated in plating on the surface that electrode exposes Layer；Weld tabs is sticked from chip exit pad in the coplanar printing solder mask of electrode and solder layer, carries out Reflow Soldering；It is cut And isolate finished goods.The packaging method step is simple, and chip functions area exposes completely, and encapsulation interconnection resistance is small, package dimension It is small；Packaging technology can be realized using existing process equipment and material.
Description of the drawings
Fig. 1 is a kind of flow diagram of the packaging method of chip provided by the invention；
Fig. 2 is the schematic diagram for etching partially copper alloy lead wire frame；
Fig. 2（a）For the sectional view along line A-A in Fig. 2；
Fig. 3 is the schematic diagram of lead frame pasted with high temperature-resistant glued membrane；
Fig. 3（a）For the sectional view along line A-A in Fig. 3；
Fig. 4 is the schematic diagram that semiconductor chip is pasted on high temperature resistant glued membrane；
Fig. 4（a）For the sectional view along line A-A in Fig. 4；
Fig. 5 is the schematic diagram that filler material fills up gap between semiconductor chip and electrode；
Fig. 5（a）For the sectional view along line A-A in Fig. 5；
Fig. 6 is the schematic diagram for being ground to electrode exposing；
Fig. 6（a）For the sectional view along line A-A in Fig. 6；
Fig. 7 is the schematic diagram taken off after high temperature resistant glued membrane；
Fig. 7（a）For the sectional view along line A-A in Fig. 7；
Fig. 8 is the schematic diagram that electrode surface plates coated layer；
Fig. 8（a）For the sectional view along line A-A in Fig. 8；
Fig. 9 is the schematic diagram of semiconductor chip exit pad, electrode print solder mask；
Fig. 9（a）For the sectional view along line A-A in Fig. 9；
Figure 10 is the schematic diagram of printing solder and Reflow Soldering；
Figure 10（a）For the sectional view along line A-A in Figure 10；
Figure 11 is that cutting detaches, and chip completes the schematic diagram of encapsulation；
Figure 11（a）For the sectional view along line A-A in Figure 11.
Specific implementation mode
Below in conjunction with the drawings and specific embodiments to a kind of packaging method and encapsulation chip work of chip proposed by the present invention It is further described.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted That attached drawing is all made of very simplified form and uses non-accurate ratio, only to it is convenient, lucidly aid in illustrating this hair The purpose of bright embodiment.
Embodiment one
This hair provides a kind of packaging method of chip, and idiographic flow schematic diagram is as shown in Figure 1.Copper alloy or iron nickel are closed first Gold etc. can the material of wet etching carry out wet method and etch partially technique and etch electroded lead frame, the ruler of the lead frame Very little and position etc. is adjusted according to specific product and application.High temperature resistant glued membrane is sticked on the lead frame.Specifically, institute The material for stating high temperature resistant glued membrane is polyimides；Then, chip is pasted on the high temperature resistant glued membrane between multiple electrodes, specifically , the distribution of electrodes around chip, the functional area of chip facing towards high temperature resistant glued membrane, and it is identical as chip thickness.It connects It and fills up the gap between chip and electrode using the filler materials such as moulding compound or filling glue, the electrode and chip are connected into whole Body.And by the filler material of grinding technics lapped face until electrode exposing, takes the high temperature resistant glued membrane off, in electrode dew Coating is coated in the surface plating gone out.The coating be thickness not less than 7 μm tin layers or thickness not less than 1 μm Ni-Pd-Au or Thickness is not less than 1 μm of Ni-Au, can ensure ability of the electrode with strong solderability and adverse environment resistant after encapsulation.From chip Exit pad sticks weld tabs electrode is coplanar using method for printing screen printing solder mask and solder layer, be used in combination 245 DEG C ~ The Reflow Soldering of 260 DEG C of progress 45s ~ 240s, finally uses the cutting methods such as grinding wheel to be cut and isolate finished goods.
When specifically used, a kind of size is the surface mount resistor bridge semiconductor chip of 2.00mm × 1.27mm × 0.40mm Encapsulation, includes the following steps：
First, the C194 copper alloys of 0.50mm thickness are etched partially into technique using wet method and etches 1.27mm × 0.40mm electrodes 3, institute It states electrode 3 muscle is connected by the technique of 0.15mm left and right thicknesses and link together, the gap between 4 electrodes is 1.20mm, etching Lead frame such as Fig. 2；
Secondly, resistance to 180 DEG C above, the high temperature resistant glued membrane 6 that thickness is 10 μm ~ 100 μm are attached on the lead frame of etching, are pasted Connect muscle face, such as Fig. 3 in technique；
From secondary, 1.10mm × 1.27mm × 0.55mm resistance bridge semiconductor chips are sticked at into the high temperature glued membrane 6 between two electrodes On, need exposed chip functions area 11 towards the high temperature glued membrane 6, such as Fig. 4；
Again, the gap between semiconductor chip 1 and the electrode 3 is filled up using the filler materials 2 such as moulding compound or filling glue, by institute State electrode 3 and the semiconductor chip 3 connect it is integral, such as Fig. 5；
Third, grinding and polishing all-in-one machine is thinned using this 200mm of ridge to be ground insert-molded leadframe frame envelope surfaces, until institute State the exposing of electrode 3, such as Fig. 6；
Then, the high temperature resistant glued membrane 6 is thrown off, such as Fig. 7；
Then, lead frame is cleaned, electroplating thickness is not less than 7 μm of tin layers 31, such as Fig. 8；
Followed by the part that need not go up solder on 1 exit pad 12 of semiconductor chip, electrode surface uses silk-screen printing side Method prints the epoxy resin solder mask 5 of 5 μm ~ 20 μ m-thicks, and cures, such as Fig. 9.
Later, 20 μm ~ 60 μ m-thick SAC305 classes solders 4 are printed, the reflux of 245 DEG C ~ 260 DEG C progress 45s ~ 240s is used in combination Weldering, such as Figure 10.
Finally, it is cut using 180 μ m-thick Carborundum wheel blades, visual examination, performance test and marking code are beaten Print completes encapsulation, as shown in figure 11.
Embodiment two
The present invention provides a kind of encapsulation chip that the packaging method by said chip is prepared, the encapsulation chip includes core Piece, filler material, electrode, solder layer and solder mask；For the chip gripper between multiple electrodes, chip includes functional areas, end pad； The end pad and electrode and coating are interconnected by solder layer, and chip functions area is exposed；The chip and electricity Pole is bonded integral by the filler materials such as moulding compound or filling glue.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims (10)

1. a kind of packaging method of chip, which is characterized in that include the following steps：
Step 1 etches electroded lead frame, and sticks high temperature resistant glued membrane on the lead frame；
Chip is pasted on the high temperature resistant glued membrane by step 2；
Step 3 fills up the gap between chip and electrode, and grinds until electrode exposes；
Step 4 takes the high temperature resistant glued membrane off；
Step 5, on the surface that electrode exposes, coating is coated in plating；
Step 6 sticks weld tabs from chip exit pad in the coplanar printing solder mask of electrode and solder layer, carries out Reflow Soldering；
Step 7 is cut and isolates finished goods.
2. the packaging method of chip exposed surface as described in claim 1, which is characterized in that the lead frame be include copper Including alloy and iron-nickel alloy can wet etching material.
3. the packaging method of chip exposed surface as described in claim 1, which is characterized in that in the step 2, chip is active Can area facing towards high temperature resistant glued membrane.
4. the packaging method of chip exposed surface as described in claim 1, which is characterized in that using molding in the step 3 Material or filling glue fill up the gap between chip and electrode.
5. the packaging method of chip exposed surface as described in claim 1, which is characterized in that the distribution of electrodes is in chip week It encloses, and identical as chip thickness.
6. the packaging method of chip exposed surface as described in claim 1, which is characterized in that the material of the high temperature resistant glued membrane For polyimides.
7. the packaging method of chip exposed surface as described in claim 1, which is characterized in that the coating is not less than for thickness Ni-Pd-Au of 7 μm of the tin layers or thickness not less than 1 μm or thickness are not less than 1 μm of Ni-Au.
8. the packaging method of chip exposed surface as described in claim 1, which is characterized in that be with 245 in the step 6 DEG C ~ 260 DEG C of Reflow Solderings for carrying out 45s ~ 240s.
9. a kind of encapsulation chip prepared according to any packaging methods of claim 1-8, which is characterized in that including core Piece, filler material, electrode, solder layer and solder mask；For the chip gripper between multiple electrodes, chip includes functional areas, end pad； The end pad and electrode and coating are interconnected by solder layer, and chip functions area is exposed；The chip and electricity Pole is bonded integral by filler material.
10. encapsulation chip as claimed in claim 9, which is characterized in that the filler material is moulding compound or filling glue.
CN201810209472.6A 2018-03-14 2018-03-14 A kind of packaging method and encapsulation chip of chip Pending CN108417498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810209472.6A CN108417498A (en) 2018-03-14 2018-03-14 A kind of packaging method and encapsulation chip of chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810209472.6A CN108417498A (en) 2018-03-14 2018-03-14 A kind of packaging method and encapsulation chip of chip

Publications (1)

Publication Number Publication Date
CN108417498A true CN108417498A (en) 2018-08-17

Family

ID=63131341

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810209472.6A Pending CN108417498A (en) 2018-03-14 2018-03-14 A kind of packaging method and encapsulation chip of chip

Country Status (1)

Country Link
CN (1) CN108417498A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022165958A1 (en) * 2021-02-05 2022-08-11 天芯互联科技有限公司 Chip packaging method and chip packaging mechanism

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646339B1 (en) * 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
WO2013065895A1 (en) * 2011-11-03 2013-05-10 주식회사 네패스 Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646339B1 (en) * 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
WO2013065895A1 (en) * 2011-11-03 2013-05-10 주식회사 네패스 Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022165958A1 (en) * 2021-02-05 2022-08-11 天芯互联科技有限公司 Chip packaging method and chip packaging mechanism

Similar Documents

Publication Publication Date Title
TWI431701B (en) Fusible i/o interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
CN105047652B (en) The encapsulating structure and production method of semiconductor devices
JP5645678B2 (en) Manufacturing method of semiconductor device
JP5798834B2 (en) Manufacturing method of semiconductor device
TW200834859A (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
TW201232673A (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
EP0753890A2 (en) Electrode structure for semiconductor device, method for forming the same, and mounted body including semiconductor device
JPH0758722B2 (en) Chip bonding method for semiconductor device
JP2003060154A (en) Semiconductor device and its manufacturing method
JP2003100948A (en) Semiconductor device and manufacturing method thereof
JP2000349194A (en) Semiconductor device and its manufacture
JP2701589B2 (en) Semiconductor device and manufacturing method thereof
CN108447840A (en) A kind of semiconductor resistor bridge encapsulating structure and technique
CN108417498A (en) A kind of packaging method and encapsulation chip of chip
JP2003100811A (en) Semiconductor device and manufacturing method thereof
CN103050463B (en) Circuit chip package and the glass flip-chip substrate structure of application
JP5414622B2 (en) Semiconductor mounting substrate and mounting structure using the same
JPH0870024A (en) Semiconductor device and its manufacture
JP2682496B2 (en) Flexible film and semiconductor device
JP2003188312A (en) Semiconductor device, laminated semiconductor unit, and its manufacturing method
JP2004179590A (en) Semiconductor device and its manufacturing method
JP4206410B2 (en) Manufacturing method of semiconductor device
JP3552660B2 (en) Method for manufacturing semiconductor device
JP2004207539A (en) Container for housing electronic component, and electronic device
CN106847788A (en) With edge-protected wafer-level chip scale package body (WLCSP)

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20180817