CN103050463B - Circuit chip package and the glass flip-chip substrate structure of application - Google Patents
Circuit chip package and the glass flip-chip substrate structure of application Download PDFInfo
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- CN103050463B CN103050463B CN201210237756.9A CN201210237756A CN103050463B CN 103050463 B CN103050463 B CN 103050463B CN 201210237756 A CN201210237756 A CN 201210237756A CN 103050463 B CN103050463 B CN 103050463B
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- circuit chip
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- copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Abstract
The present invention discloses the glass flip-chip substrate structure of a kind of circuit chip package and application.Circuit chip package includes the IC chip (IC chip) with a chip circuit face, and the multiple copper bumps being arranged on chip circuit face.Furthermore, a non-conductive adhesive (NCF) can be re-formed on chip circuit face to cover those copper bumps.Glass flip-chip substrate structure includes a glass substrate, is formed at the multiple aluminium electrodes on glass substrate, is formed on glass substrate and covers a conducting resinl of those aluminium electrodes.Conducting resinl includes multiple conducting particles.When circuit chip package is engaged with glass substrate, copper bump can be electrically connected by conducting particles with corresponding aluminium electrode.
Description
Technical field
It is the present invention relates to a kind of circuit chip package and its application and more particularly to a kind of with copper bump
Circuit chip package and the glass flip-chip substrate structure using the circuit chip package.
Background technology
The electrical transmission and glass substrate between of IC chip (IC chip) is often implemented with metal coupling (Bump),
Existing metal coupling is using golden (Au) as application material.These metal couplings are the process generations in encapsulation manufacture, and its
The mode and approach of connection, then make the actual drawing of metal coupling by encapsulating design software.The material of these metal couplings
Matter and hardness can be limited by packaging manufacturing process, also limit the electrical performance after being connected with glass substrate.
The content of the invention
It is an object of the invention to provide a kind of circuit chip package and apply the ic chip package
The glass flip-chip substrate structure of part.Copper bump is formed in the process of encapsulation manufacture, not only reduces cost, appropriate pressing can be also provided
The physical and electric sex expression of (being engaged with glass substrate).
It is up to above-mentioned purpose, according to an aspect of the invention, it is proposed that a kind of circuit chip package, including with one
One IC chip (IC chip) in chip circuit face, and the multiple copper bumps being arranged on chip circuit face.Furthermore, can
In re-forming a non-conductive adhesive (nonconductive film, NCF) on chip circuit face to cover those copper bumps.
According to another aspect of the invention, it is proposed that a kind of glass flip-chip substrate structure, it includes a glass substrate；It is formed at
Multiple aluminium electrodes on glass substrate；A conducting resinl of those aluminium electrodes is formed on glass substrate and covered (such as respectively to different
Property conducting resinl, ACF), conducting resinl includes multiple conducting particles；An IC chip (IC with a chip circuit face
), and multiple copper bumps for being arranged on chip circuit face chip.Wherein, the top surface of copper bump is by those conducting particles of part
Electrically connected with corresponding those aluminium electrodes.Similarly, a non-conductive adhesive can on an integrated circuit die be re-formed
(nonconductive film, NCF) is covering those copper bumps.
According to another aspect of the invention, a kind of circuit chip package is proposed, including with a chip circuit face
An IC chip (IC chip), multiple copper bumps for being arranged on chip circuit face and be formed at the chip circuit face
Go up and cover a non-conductive adhesive (NCF) of those copper bumps.Wherein the non-conductive adhesive has light peneration, and copper bump is alloy
Or hierarchy, the copper metal composition of those copper bumps accounts for 30% percentage by weight~100% percentage by weight of total composition.
It is that the above of the invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing, make detailed
It is described as follows：
Brief description of the drawings
Fig. 1 is the schematic diagram of the circuit chip package of first embodiment of the invention；
Fig. 2 is the schematic diagram of the circuit chip package of second embodiment of the invention；
Fig. 3 A ~ Fig. 3 G are the flow chart of the circuit chip package for manufacturing second embodiment of the invention；
Fig. 4 A are the schematic diagram for carrying out mechanical treatment to the top surface of copper bump using diamond scraper；
Fig. 4 B are the schematic diagram for carrying out mechanical treatment to the top surface of copper bump using cmp；
The flow that Fig. 5 A ~ Fig. 5 C are engaged for the circuit chip package of second embodiment of the invention with glass substrate
Figure；
Fig. 6 A- Fig. 6 C be using the projection that is covered without non-conductive adhesive and panel assembly to group when, conductive particle in conducting resinl
The dynamic schematic diagram of subflow；
Fig. 7 A- Fig. 7 C be the copper bump and the panel assembly that are covered using the non-conductive adhesive of embodiment to group when, in conducting resinl
The schematic diagram of conducting particles flowing；
Fig. 8 is non-conductive adhesive (NCF) and the viscosity of conducting resinl (ACF) and the graph of a relation of temperature；
Fig. 9 A are for the copper bump just formed on the chip circuit face of IC chip may have out-of-flatness surface or have
Highly uneven condition diagram；
Fig. 9 B are to carry out mechanical treatment to the top surface of copper bump with diamond scraper, except removing removing oxide layer, the copper after treatment
Projection has good same flatness figure；
Fig. 9 C are that can influence what is subsequently engaged with panel assembly to show using surface irregularity, highly uneven copper bump
It is intended to.
Main element symbol description
10、10’：Circuit chip package
11、31、68、81：IC chip
13、33、83：Chip circuit face
15、35、84、85：Copper bump
151、351：The bottom surface of copper bump
153、353：The top surface of copper bump
17、37：Non-conductive adhesive
171、371：One flat surfaces of non-conductive adhesive
41：Diamond scraper
42：Pure water
43：Slurry
46：Adhesive tape
47：Framework
48：Chip cutting machine
49：Chip the storage box
50：Panel assembly
51、61、71、88：Glass substrate
53、63、73、89：Aluminium electrode
55、65、75：Conducting resinl
56、66、76：Conducting particles
69：Projection
D：Distance
Specific embodiment
First embodiment
Fig. 1 is refer to, it illustrates the schematic diagram according to the circuit chip package of first embodiment of the invention.It is integrated
Circuit chip package part 10 at least includes an IC chip (IC chip) 11 and multiple copper bumps (Cu Bump) 15.It is integrated
Circuit chip 11 has a chip circuit face 13, and the bottom surface 151 of copper bump 15 is arranged on chip circuit face 13.
When product, by taking glass substrate as an example, the top surface 153 of copper bump 15 can be with for application integrated circuit chip package 10
Electrode alignment on glass substrate, and the conducting particles included by conducting resinl on glass substrate carries out copper bump 15 and electrode
Electrical connection, reach the electrical transmission between IC chip 11 and panel assembly.
In embodiment, it is fine copper more than 99% percentage by weight that copper bump is, for example, or copper metal composition accounts for assembly
It is more than 90% percentage by weight for dividing.In addition, copper bump can also be copper metal composition accounting for 30% percentage by weight of total composition
More than, the alloy or hierarchy of person below 100% percentage by weight.With copper bump as copper/hierarchy of ni au as a example by,
Thickness is, for example, 9/1/4 μm or 9/1/2 μm or 7/1/4 μm, or other ratios also may be used.
Actual manufacturing process on circuit chip package 10, can be within the shortest time (such as a few hours), by copper
Projection 15 is done directly the electrical connection with aluminium electrode on glass substrate (such as ITO), short with copper ion migration to avoid copper from aoxidizing
Road (Migration).In addition, in the manufacture craft of copper bump, the mode that suppresses oxide layer generation or directly can be also added
The step of removing removing oxide layer.Suppress oxide layer generation mode be, for example,：Nitrogen is passed through when those copper bumps 15 are formed；Or
After copper bump 15 is formed, by an oxidation retarder spraying or immersion way is processed those copper bumps 15.Can apply
Oxidation retarder be, for example, one 5%~30% sulfuric acid solution or be one 5%~30% hydrofluoric acid solution.Directly remove removing oxide layer
Mode be, for example,：After forming copper bump 15, to the top surface of those copper bumps 15 with diamond scraper or cmp (CMP)
Mode removes removing oxide layer, and can thus control the same flatness and surface roughness of those copper bumps 15.
Tradition is compared to using golden projection, the copper bump 15 that embodiment is proposed can be produced in the process of encapsulation manufacture,
There is provided lower cost, and then there is the physical and electrical resistance of appropriate pressing (being engaged with glass substrate) when being applied to product
Performance.
Second embodiment
Fig. 2 is refer to, it illustrates the schematic diagram according to the circuit chip package of second embodiment of the invention.Second
The circuit chip package 10 ' of embodiment is same with the circuit chip package 10 of first embodiment to have integrated electricity
Road chip 11 and the multiple copper bumps 15 being arranged on chip circuit face 13, but also include a non-conductive adhesive (nonconductive
Film, NCF) 17 it is formed on chip circuit face 13 and covers those copper bumps 15, copper bump 15 is not exposed, to avoid copper oxygen
Change and copper ion migration short circuit (Migration).As shown in Fig. 2 the non-conductive adhesive 17 for covering those copper bumps 15 preferably has
One flat surfaces 171, and the flat surfaces 171 to copper bump 15 top surface 153 in one apart from d.
Such as first embodiment, it is fine copper more than 99% percentage by weight that copper bump is, for example, or copper metal composition
Account for more than 90% percentage by weight of total composition.In addition, copper bump can also be copper metal composition accounting for 30% weight of total composition
It is more than percentage, the alloy or hierarchy of person below 100% percentage by weight.With copper bump as copper/hierarchy of ni au
As a example by, thickness is, for example, 9/1/4 μm or 9/1/2 μm or 7/1/4 μm, or other ratios also may be used.
In a second embodiment, non-conductive adhesive (NCF) 17 is covered into copper bump 15 as diaphragm, copper can be avoided to aoxidize
With copper ion migration short circuit, can also make copper bump 15 pot-life (i.e. shipment to pressing before during) elongation.
In one embodiment, the material of non-conductive adhesive 17 is, for example, that including weak acid or weak base material, pH-value pH is between 4 ~ 6.5
Or between 7.5 ~ 10, copper can be avoided from aoxidizing.
In one embodiment, the material of non-conductive adhesive 17 is, for example, using macromolecule resin (Base Resin), its die-size
Between 0.05nm ~ 500nm, moisture in air infiltration can be resisted and corroded, can also avoid copper from aoxidizing.
In one embodiment, to avoid halide ion (such as chlorion or bromide ion halide) from corroding copper bump or and copper
The erosion composition of metallic circuit (aluminium electrode) on destruction integrated circuit is formed, the material of non-conductive adhesive 17 is, for example, in itself addition ion
Capture function material, for example with NaOH or Ca (OH)2OH ion roots, be, for example, 20ppm-5% into doses, make free point
The OH ions root of cloth can catch free copper ion and halide ion, it is to avoid copper ion migration short circuit and halide ion corrode.
It is non-conductive to avoid halide ion (such as chlorion or bromide ion halide) from corroding copper bump in one embodiment
The content of halide ions of the own material composition of glue 17 is for example controlled at below 20ppm (0 ~ 20ppm)；Due to measurement error, separately
A content of halide ions of non-conductive adhesive is below 2ppm in one embodiment.
In one embodiment, the material of non-conductive adhesive 17 be, for example, including macromolecule resin 30-40%, (Filler Silica)
50-60%, (Dilution Epoxy) 2%-10%, ion capturing agent NaOH (NaOH) or calcium hydroxide (Ca (OH)2)
The macromolecule chemical materials such as 20ppm-5%.
Fig. 3 A ~ Fig. 3 G are the flow chart of the circuit chip package for manufacturing second embodiment of the invention.Such as Fig. 3 A institutes
Show, there is provided a chip 31, the chip 31 has a chip circuit face 33, and multiple copper bumps are formed on chip circuit face 33
35, the bottom surface 351 of those copper bumps 35 contacts with chip circuit face 33.Can be required according to application, but without limitation, to the table of chip 31
(such as with photoresist) carries out surface planarisation in face, and manufacture craft (such as diamond wheel is ground to the back side of chip 31
The back side to chip 31 carries out the mechanical polishing twice such as rough lapping and fine lapping).
In embodiment, copper bump 35 formation after, using diamond scraper 41 (as shown in Figure 4 A, coordinating with pure water 42),
Or it is right using cmp (CMP) mode (as shown in Figure 4 B, using the CMP slurries 43 being made up of slurries and abrasive particle)
The top surface of those copper bumps 35 carries out mechanical treatment, more controllable except can remove oxide layer produced after copper bump 35 grows up to
The surface roughness and same flatness of copper bump processed.
Then, as shown in Figure 3 B, a non-conductive adhesive (NCF) 37 is formed on chip circuit face 33 and covering copper bump 35.
The implementation method of this step is, for example, in rotary coating (Spin Coating) mode, using rotary centrifugal force by non-conductive adhesive 37
On uniform application；Adhesive tape type laminating (Film Taping) mode can also be used and forms non-conductive adhesive 37.Cover those copper bumps 35
Non-conductive adhesive 37 can have a flat surfaces 371, its to copper bump 35 top surface 353 in one apart from d.
Afterwards, such as Fig. 3 C, baking procedure is optionally carried out, so that non-conductive adhesive 37 solidifies and stable form.
Afterwards, as shown in Figure 3 D, chip bonding die (wafer mounting) is carried out, adhesive tape can be sticked by chip back surface
(blue tape) 46 is placed on framework (iron or steel or copper framework) 47, and chip is fitted into framework 47.
Then, as shown in FIGURE 3 E, then by the chip on framework 47 deliver to after being fixed on the Cutting platform of chip cutting machine 48
Cut.Form that integrated circuit chip structure 10 is in good order one by one is arranged on adhesive tape 46 after having cut.
Then, as illustrated in Figure 3 F, separate and pick (pick up) those integrated circuit chip structures 10.And by integrated electricity
Road chip structure 10 is loaded into chip the storage box (Tray) 49, as shown in Figure 3 G.
It is worth noting that, in a second embodiment, copper bump 35 is covered with non-conductive adhesive (NCF) 37, due in chip
Non-conductive adhesive 37 is coated on 31 as diaphragm, is that (Fig. 3 E) can be accurately cut in process, the color of non-conductive adhesive 37 is preferable
It is transparent or at least partly transparent with light peneration, contraposition camera lens is picked out the contraposition mark on chip 31 (as aligned
Metal).Likewise, performing the program as shown in Fig. 3 D, Fig. 3 F, Fig. 3 G for convenience, the color of non-conductive adhesive 37 is preferably transparent
Or it is at least partly transparent or with penetrability feature.
The stream that Fig. 5 A ~ Fig. 5 C are engaged for the circuit chip package 10 ' of second embodiment of the invention with glass substrate
Cheng Tu.First, as shown in Figure 5A, there is provided a panel assembly 50, the panel assembly 50 may include a glass substrate 51, multiple aluminium electricity
Pole 53 is formed on glass substrate 51 and a conducting resinl 55 is formed on glass substrate 51 and covers those aluminium electrodes 53.It is conductive
Glue 55, an e.g. anisotropy conductiving glue (ACF) fits (Film Taping) on glass substrate 51, and is contained within multiple
Conducting particles 56.
It is worth noting that, the conventional structure of general conventional anisotropy conductiving glue (ACF) is bilayer conductive glue material knot
Structure, is built up by a non-conductive layer (NCF) and a conductive layer are compound.But because circuit chip package 10 ' has had non-leading
Electric glue (NCF) 37, when being engaged with glass substrate 51, the conducting resinl 55 in the aluminium electrode 53 of implementation can be used the conduction of simple layer
Glue material (ACF) structure (is not required to the double-deck ACF as generally used NCF).
Afterwards, as shown in Figure 5 B, by those copper bumps 35 of the circuit chip package 10 ' of second embodiment and face
Those aluminium electrodes 53 of board component 50 are aligned, and optionally carry out pre- laminating (toasting as before), with temporary transient securing integrated circuit.
As shown in Figure 5 C, toasted, with securing integrated circuit chip package 10 ' and panel assembly 50, made integrated electricity
The top surface 353 of the copper bump 35 of road chip package 10 ' by the conducting particles 56 of part in conducting resinl 55 with corresponding face
The aluminium electrode 53 of board component 50 is electrically connected, to complete the assembly journey of circuit chip package 10 ' and panel assembly 50
Sequence.Wherein, after circuit chip package 10 ' and 50 pairs of groups of panel assembly, those copper bumps 35 are electrically connected with those aluminium electricity
The conducting particles 56 of pole 53 pierces through the surface of the non-conductive adhesive 37.
It has been observed that accurately to cut (Fig. 3 D- Fig. 3 F) in process, the color of non-conductive adhesive 37 need to have light peneration
It is transparent or at least partly transparent.Likewise, for that can be sealed in contraposition process (program of Fig. 5 B) accurate contraposition IC chip
Aluminium electrode 53 on the copper bump 35 and glass substrate 51 of piece installing 10 ', the color of non-conductive adhesive 37 on chip be preferably it is transparent or
It is at least partly transparent or with light transmissibility, contraposition camera lens is picked out the contraposition mark on chip (such as contraposition metal).
In addition, as shown in Figure 5 C to group circuit chip package 10 ' and during panel assembly 50, conducting resinl (such as ACF)
55 when being pressed, and the flowing of inner conductive particle 56 can be influenceed by the viscosity B coefficent of non-conductive adhesive 37.
Fig. 6 A- Fig. 6 C illustrate using the projection that is covered without non-conductive adhesive and panel assembly to group when, it is conductive in conducting resinl
The schematic diagram of particle flow.(such as include glass substrate 61, aluminium electrode with panel assembly in the projection 69 that could be used without non-conductive adhesive
63rd, conducting resinl 65 and inner conductive particle 66) to group when (Fig. 6 A), conducting resinl (such as ACF) 65 is squeezed, and ic core
On piece 68 because without non-conductive adhesive cover projection 69 influence, during pressing conducting particles 66 flow (arrow of Fig. 6 B) will not because squeeze
Press through journey and flow too soon, also than less likely causing that the conducting particles 66 grasped number is mended after pressing has very few situation (figure
6C)。
Fig. 7 A- Fig. 7 C illustrate the copper bump covered using non-conductive adhesive with panel assembly (as included glass substrate 71, aluminium electricity
Pole 73, conducting resinl 75 and inner conductive particle 76) to group when, in conducting resinl conducting particles flowing schematic diagram.Typically integrated
Hardness e.g., about more than the 80HV of the copper bump 35 on circuit chip 31 is more than 100HV.With panel assembly to group when
(Fig. 7 A), conducting resinl (such as ACF) 75 is squeezed, but the non-conductive adhesive 37 covered on copper bump 35 can account for original conductive particle
The dynamic space of subflow, it is easy to influence conducting particles to flow speed (arrow of Fig. 7 B), conducting particles 76 flows easily during pressing
Flowed because of extrusion process too fast, may make to mend the conducting particles 76 grasped after pressing to count and have very few situation (Fig. 7 C).
Fig. 8 is refer to, it is non-conductive adhesive (NCF) and the viscosity of conducting resinl (ACF) and the graph of a relation of temperature.One embodiment
In, non-conductive adhesive (NCF) is, for example, the temperature dependence characteristic for coordinating conducting resinl ACF.The viscosity of conducting resinl ACF as shown in Figure 8-
Temperature curve (curve-▲-represent；The viscosity-temperature data of one non-conductive adhesive by curve-◆-represent), non-conductive adhesive (NCF)
Viscosity coefficient may be selected (to optimize straight line B's to -8KPaS/ DEG C -0.3KPaS/ DEG C the slope of A (optimize straight line)
Slope) between (i.e. when rising every 1 DEG C, viscosity declines 0.3 ~ 8K PaS).Can be observed, when gluing for non-conductive adhesive (NCF)
Degree coefficient is greater than about -0.3KPaS/ DEG C or during less than about -0.3KPaS/ DEG C, the conductive particle subnumber captured on copper bump
It is less, or even have the situation less than 2.Conversely, when non-conductive adhesive (NCF) viscosity coefficient -0.3KPaS/ DEG C to -
In 8KPaS/ DEG C of interval, the conductive particle subnumber captured on copper bump is substantially good, effective particle even up to 20 with
On.Another embodiment, the viscosity coefficient of non-conductive adhesive (NCF) also may be selected -4KPaS/ DEG C (optimizing the slope of straight line C)
Between to -5KPaS/ DEG C.In one embodiment, make copper bump 35 that the number of the conducting particles 76 of conducting is electrically connected with aluminium electrode 73
About 2 ~ 200, another embodiment is about 3 ~ 30.
Either first embodiment or second embodiment whether there is non-conductive adhesive 37 and cover, it is preferred that can be in copper bump
In manufacturing process, removing oxide layer or suppression are imposed in copper bump top surface (afterwards with the contact surface of the electrode engagement of panel assembly)
The treatment that oxide layer grows up to.More specifically, Shi Yugai areas can be manufactured in copper bump and fills nitrogen preparation, kept away with driving away oxygen
Exempt from the generation of oxide layer.Or after copper bump is formed (such as after Fig. 3 A), sprinkling or the sour agent of immersion are (to go removing oxide layer and suppression
Grow up to) or removing oxide layer is gone with diamond scraper or cmp (CMP) grinding.
Fig. 9 A illustrate the copper bump 84 just formed on the chip circuit face 83 of IC chip 81 may have out-of-flatness
There is highly uneven situation on surface.Fig. 9 B are illustrated carries out machinery with diamond scraper 41 to the top surface of those copper bumps 84
Treatment, except removing removing oxide layer, the copper bump 85 after treatment has good same flatness (highly flushing).Fig. 9 C are illustrated and used
Surface irregularity, highly uneven copper bump 84 can influence the schematic diagram for subsequently being engaged with panel assembly.In this embodiment
In, the same flatness and surface roughness that can make copper bump by the process of mechanical treatment are controlled, and make copper bump and panel
Component (aluminium electrode 89 such as on glass substrate 88) is engageable good.
If it is worth noting that, the surface roughness of copper bump 85 is excessive (for example>2um), pressing program can be made (as schemed
5B- Fig. 5 C) when carrying out, conducting particles loose contact or effective number are very few.When surface roughness is too small (for example<0.05um),
When can make pressing program (such as Fig. 5 B- Fig. 5 C) and carrying out, conducting particles is because of gripping power is not enough loose contact or slips to copper
Region beyond projection.In one embodiment, the surface roughness of copper bump 85 is between 0.05 μm ~ 2 μm.Another embodiment is
Between 0.8 μm ~ 1.2 μm.
Summary, replaces the existing golden material can to reduce cost using copper bump, and it is in encapsulation to encapsulate copper bump
The process of manufacture is produced, it is possible to provide the physical and electric sex expression of appropriate pressing (being engaged with glass substrate).In embodiment, can
Copper bump is covered using non-conductive adhesive (NCF), to avoid copper from aoxidizing the problems such as with copper ion migration short circuit, can also make copper bump
Pot-life (during before shipment to pressing) is elongated, and it is single 1 layer that can reduce the structure sheaf of glass substrate conducting resinl (ACF)
Conductive adhesive layer (the conventional conducting resinl of original is double-layer structure, including non-conductive adhesive NCF and ACF conducting resinl composite laminate), there is provided lead
Electric glue (ACF) cost is reduced.Furthermore, special composition can be more added in the material of non-conductive adhesive and avoids copper bump from producing to be lifted
The oxidation effect short-circuit with copper ion migration.Furthermore, more can by the physical characteristic (such as viscosity) of non-conductive adhesive material with it is existing
The material matching of conducting resinl (ACF), reaches the electrical combination good with glass substrate, obtains real volume production.In addition, embodiment
Copper bump encapsulating structure cut crystal and pick tube core mode, can control as non-conductive adhesive (NCF) material of diaphragm
(Peeling) is peeled off in the deformation of material, realizes that segmentation chip removes chip unit, and ensure quality after shipment.In addition, being worth note
Meaning, though enumerate different embodiments above illustrate respectively, but in practical application, can combine different embodiments.
In sum, the present invention is disclosed with reference to above example, but it is not limited to the present invention.Institute of the present invention
Skilled person in category technical field, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Cause
This, protection scope of the present invention should be by being defined that the claim enclosed is defined.
Claims (31)
1. a kind of circuit chip package, including：
IC chip, with a chip circuit face；With
Multiple copper bumps, on its bottom surface directly contact chip circuit face；
The circuit chip package also includes a non-conductive adhesive, is formed on the chip circuit face and to cover those copper convex
Block, and the non-conductive adhesive has light peneration；
Wherein, a surface roughness of those copper bumps is between 0.05 μm~2 μm.
2. circuit chip package as claimed in claim 1, wherein the non-conductive adhesive for covering those copper bumps has
One flat surfaces, and the flat surfaces to the top surface of those copper bumps is in a distance.
3. circuit chip package as claimed in claim 1, the wherein non-conductive adhesive are a transparent non-conductive glue.
4. circuit chip package as claimed in claim 1, the wherein non-conductive adhesive include macromolecule resin, its tube core
Size is between 0.05nm~500nm.
5. circuit chip package as claimed in claim 1, the wherein non-conductive adhesive include weak acid or weak base material, acid
Base number pH be 4~6.5 between or 7.5~10 between.
6. circuit chip package as claimed in claim 1, the wherein non-conductive adhesive include hydroxyl ion root, and content is
20ppm~5%.
7. circuit chip package as claimed in claim 1, the wherein non-conductive adhesive include NaOH or hydroxide
Calcium.
8. circuit chip package as claimed in claim 1, a content of halide ions of the wherein non-conductive adhesive is
Below 20ppm.
9. circuit chip package as claimed in claim 1, a content of halide ions of the wherein non-conductive adhesive is
Below 2ppm.
10. circuit chip package as claimed in claim 1, the wherein viscosity coefficient of the non-conductive adhesive-
Between 0.3KPaS/ DEG C to -8KPaS/ DEG C.
11. circuit chip packages as claimed in claim 1, wherein the viscosity coefficient of the non-conductive adhesive is in -4KPa
Between S/ DEG C to -5KPaS/ DEG C.
12. circuit chip packages as claimed in claim 1, wherein the hardness of those copper bumps is in more than 80HV.
One surface roughness of 13. circuit chip packages as claimed in claim 1, wherein those copper bumps is in 0.8 μ
Between m~1.2 μm.
14. circuit chip packages as claimed in claim 1, wherein those copper bumps are alloy or hierarchy, are somebody's turn to do
The copper metal composition of a little copper bumps accounts for 30% percentage by weight~100% percentage by weight of total composition.
15. circuit chip packages as claimed in claim 14, wherein those copper bumps are the hierarchy of cupro-nickel gold.
The copper metal composition of 16. circuit chip packages as claimed in claim 1, wherein those copper bumps accounts for total composition
90% percentage by weight more than.
17. circuit chip packages as claimed in claim 1, wherein those copper bumps are more than 99% percentage by weight
Fine copper.
A kind of 18. glass flip-chip substrate structures, including：
The circuit chip package of claim 1；
Glass substrate；
Multiple aluminium electrodes, are formed on the glass substrate；And
Conducting resinl, is formed at the glass substrate and covers those aluminium electrodes, and the conducting resinl includes multiple conducting particles, wherein
The top surface of those copper bumps in the circuit chip package by part those conducting particles with it is corresponding those
Aluminium electrode is electrically connected.
19. glass flip-chip substrate structures as claimed in claim 18, the wherein conducting resinl are a single layer of conductive glue material.
20. glass flip-chip substrate structures as claimed in claim 18, the wherein conducting resinl are an anisotropy conductiving glue, its bag
Include a composite laminate of non-conductive layer and conductive layer.
21. glass flip-chip substrate structures as claimed in claim 18, it is non-that those conducting particles of the wherein conducting resinl wear out this
The surface of conducting resinl, to electrically connect those copper bumps and those aluminium electrodes.
22. glass flip-chip substrate structures as claimed in claim 21, wherein electrically connecting those copper bumps with those aluminium electrodes
The number of those conducting particles is 2~200.
23. glass flip-chip substrate structures as claimed in claim 21, wherein electrically connecting those copper bumps with those aluminium electrodes
The number of those conducting particles is 3~30.
A kind of 24. circuit chip packages, including：
IC chip, with chip circuit face；
Multiple copper bumps, its bottom surface is arranged on the chip circuit face, and those copper bumps are alloy or hierarchy, and those copper are convex
The copper metal composition of block accounts for 30% percentage by weight~100% percentage by weight of total composition, and a surface of those copper bumps is thick
Rugosity is between 0.05 μm~2 μm；With
Non-conductive adhesive, is formed on the chip circuit face and covers those copper bumps, and the non-conductive adhesive has light peneration.
25. circuit chip packages as claimed in claim 24, the wherein non-conductive adhesive are a transparent non-conductive glue.
26. circuit chip packages as claimed in claim 24, wherein those copper bumps are the hierarchy of cupro-nickel gold.
The copper metal composition of 27. circuit chip packages as claimed in claim 24, wherein those copper bumps accounts for assembly
It is more than 90% percentage by weight for dividing.
28. circuit chip packages as claimed in claim 24, wherein those copper bumps be 99% percentage by weight with
On fine copper.
A kind of 29. glass flip-chip substrate structures, including：
The circuit chip package of claim 25；
Glass substrate；
Multiple aluminium electrodes, are formed on the glass substrate；And
Conducting resinl, is formed at the glass substrate and covers those aluminium electrodes, and the conducting resinl includes multiple conducting particles, wherein
The top surface of those copper bumps in the circuit chip package by part those conducting particles with it is corresponding those
Aluminium electrode is electrically connected.
30. glass flip-chip substrate structures as claimed in claim 29, the wherein conducting resinl are a single layer of conductive glue material.
31. glass flip-chip substrate structures as claimed in claim 30, the wherein circuit chip package also include non-leading
Electric glue, is formed on the chip circuit face and covers those copper bumps, and it is non-conductive that those conducting particles of the conducting resinl wear out this
The surface of glue is electrically connecting those copper bumps and those aluminium electrodes.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161546094P | 2011-10-12 | 2011-10-12 | |
| US61/546,094 | 2011-10-12 |
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| CN103050463B true CN103050463B (en) | 2017-06-09 |
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| TW (1) | TWI492342B (en) |
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| US10741482B2 (en) | 2017-12-29 | 2020-08-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
| CN111384005B (en) * | 2020-03-23 | 2022-03-04 | 甬矽电子(宁波)股份有限公司 | Microelectronic package, flip-chip process and application thereof, and microelectronic device |
| CN112820764B (en) * | 2021-01-15 | 2022-09-23 | 昆山国显光电有限公司 | Display screen and preparation method thereof |
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|---|---|---|---|---|
| CN101345199A (en) * | 2007-07-11 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Packaging structure and its forming method |
| CN102054811A (en) * | 2009-10-29 | 2011-05-11 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7960830B2 (en) * | 2003-11-14 | 2011-06-14 | Industrial Technology Research Institute | Electronic assembly having a multilayer adhesive structure |
| KR100746330B1 (en) * | 2005-11-24 | 2007-08-03 | 한국과학기술원 | Method for bonding between electrical devices using ultrasonication |
| TWI299555B (en) * | 2006-04-28 | 2008-08-01 | Taiwan Tft Lcd Ass | Semiconductor flip-chip package component and fabricating method |
| TWI335654B (en) * | 2007-05-04 | 2011-01-01 | Advanced Semiconductor Eng | Package for reducing stress |
| KR100838647B1 (en) * | 2007-07-23 | 2008-06-16 | 한국과학기술원 | Wafer-level acf flip chip package using double-layered acf/ncf |
| TW200916879A (en) * | 2007-10-02 | 2009-04-16 | Int Semiconductor Tech Ltd | Bonding method for chip on glass |
| JP6041463B2 (en) * | 2009-12-25 | 2016-12-07 | デクセリアルズ株式会社 | Epoxy resin composition, method for producing joined body using the same, and joined body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345199A (en) * | 2007-07-11 | 2009-01-14 | 台湾积体电路制造股份有限公司 | Packaging structure and its forming method |
| CN102054811A (en) * | 2009-10-29 | 2011-05-11 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
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| TW201316465A (en) | 2013-04-16 |
| CN103050463A (en) | 2013-04-17 |
| TWI492342B (en) | 2015-07-11 |
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