JP2003100811A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP2003100811A
JP2003100811A JP2001298253A JP2001298253A JP2003100811A JP 2003100811 A JP2003100811 A JP 2003100811A JP 2001298253 A JP2001298253 A JP 2001298253A JP 2001298253 A JP2001298253 A JP 2001298253A JP 2003100811 A JP2003100811 A JP 2003100811A
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JP
Japan
Prior art keywords
semiconductor
resin
layer
wiring
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001298253A
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Japanese (ja)
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JP3836349B2 (en
Inventor
Soichi Honma
荘一 本間
Original Assignee
Toshiba Corp
株式会社東芝
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Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2001298253A priority Critical patent/JP3836349B2/en
Publication of JP2003100811A publication Critical patent/JP2003100811A/en
Application granted granted Critical
Publication of JP3836349B2 publication Critical patent/JP3836349B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Abstract

(57) Abstract: In a semiconductor device in which a semiconductor element is connected to a wiring board via a metal bump, the connection strength is increased and the reliability is improved. SOLUTION: In the semiconductor device of the present invention, a first resin layer 6 is formed on an outer periphery of a solder bump 5 connecting an electrode pad 4 of a semiconductor chip 3 and a wiring pad 2 of a wiring board 1; Resin layer 6 is composed of solder bump 1 and wiring board 1
And a fillet between them. The bump bonding and the formation of the first resin layer 6 are performed by forming a flux component-containing resin layer on the outer periphery of the solder bump 5 of the semiconductor chip 3 by a squeezing method or the like, and then connecting the solder bump 5 and the wiring. This is performed by aligning and temporarily fixing the wiring pads 2 of the substrate 1 and joining them by heating. Next, the first resin layer 6 in the form of a fillet is formed by curing the resin layer containing the flux component.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a semiconductor element or a semiconductor package is connected to a substrate via a metal material, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, flip-chip connection is one of the techniques for mounting a semiconductor chip on a wiring board.
In the flip chip connection part, for example, a semiconductor chip is mounted face down on one main surface (wiring pad formation surface) of a wiring board, and its electrode terminals and wiring pads on the board side are bumps of metal such as solder. It has a structure connected by. The electrode terminals of the semiconductor chip and the wiring pads of the wiring board may be joined by soldering via gold (Au) bumps or the like.

In such a flip-chip connection portion, thermal stress due to the difference in coefficient of thermal expansion between the wiring board and the semiconductor chip is concentrated in the metal bump portion to cause distortion, resulting in a decrease in connection reliability. There is. To prevent that,
A sealing layer made of an insulating resin such as epoxy resin is formed between the wiring board and the semiconductor chip by potting or the like.

[0004]

However, in such a conventional flip-chip connection portion, there are problems that voids are likely to occur inside the insulating resin layer and the warp of the wiring board is likely to be large.

Further, by coating resin on the surface of the semiconductor chip having metal bumps formed on the electrode terminals,
A method has been developed in which a resin layer is formed around metal bumps, the tops of the metal bumps are polished, and then the obtained semiconductor chips are flip-chip connected via the metal bumps.

However, in this method, since the resin layer around the bumps is hardened in the step of flip-chip connecting the semiconductor chips, the adhesiveness between the resin layer and the wiring board is weak,
The reliability was insufficient. Further, there is a problem that the process becomes complicated.

Further, as a method of forming the resin layer, a method of applying a photosensitive resin, exposing and developing the resin layer is adopted.
Although a resin layer is formed only around the metal bumps, this method not only complicates the process, but also weakly adheres the resin layer to the wiring board, as in the above method. It was not possible to obtain sufficient reliability.

The present invention has been made to solve these problems, and in a semiconductor device in which a semiconductor element or a semiconductor package is connected to a substrate through a metal material and a manufacturing method thereof, the connection strength is increased and the reliability is improved. The purpose is to improve.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device in which a wiring layer is formed on at least one main surface of an insulating substrate, and a wiring layer is formed on the wiring substrate. A semiconductor element mounted face down and a metal bump formed on an electrode terminal of the semiconductor element are provided, and an electrode terminal of the semiconductor element and a wiring layer of the wiring board are bonded via the metal bump. And a fillet of the first resin layer is formed between the metal bump and the wiring board.

In the semiconductor device of the first invention, the metal bumps are made of Au, Ag, Cu, Ni, Fe, Pd, S.
It can be composed of a metal selected from n, Pb, Bi, Zn, In, Sb, and Ge alone, or a mixture or compound thereof. Also, between the semiconductor element and the wiring board,
It is possible to have a sealing layer made of a second resin. Furthermore, a fillet of a resin layer may be further formed between the metal bump and the semiconductor element.

Further, in the semiconductor device having the sealing layer made of the second resin, among the plurality of metal bumps for joining the electrode terminals of the semiconductor element and the wiring layer of the wiring board,
The fillet of the first resin layer is formed on the joints of some of the metal bumps, and the sealing layer made of the second resin is formed around the joints of the other metal bumps. Can be configured. Further, the fillets of the first resin layer formed at the joint portions of the plurality of adjacent metal bumps can be configured to be connected to each other.

A semiconductor device according to a second aspect of the present invention is a mounting substrate in which a wiring layer is formed on at least one main surface of an insulating substrate, and a semiconductor mounted on the wiring layer forming surface of the mounting substrate. A package; and a metal bump connecting the semiconductor package and a wiring layer of the mounting substrate, wherein a fillet of a first resin layer is formed between the metal bump and the mounting substrate. Is characterized by.

In the semiconductor device of the second invention, the metal bumps are made of Au, Ag, Cu, Ni, Fe, Pd, Sn,
Pb, Bi, Zn, In, Sb and Ge may be used alone, or may be composed of a metal selected from a mixture or compound thereof. In addition, a fillet of a resin layer may be further formed between the metal bump and the semiconductor package.

A semiconductor device according to a third aspect of the present invention is a mounting substrate in which a wiring layer is formed on at least one main surface of an insulating substrate, and leads mounted on the wiring layer forming surface of the mounting substrate. A semiconductor package having a frame; and a low melting point metal layer for joining the lead frame of the semiconductor package and a wiring layer of the mounting substrate to each other. The first melting point metal layer is provided between the low melting point metal layer and the mounting substrate. Is characterized in that a fillet of the resin layer is formed.

In the semiconductor device of the second and third inventions, a sealing layer made of the second resin can be provided between the semiconductor package and the mounting substrate.

A fourth invention of the present invention is a method for manufacturing a semiconductor device, in which a semiconductor element is mounted on a substrate via a metal bonding member, wherein the resin bonding layer containing a flux component is formed on the outer periphery thereof. A step of aligning the substrate and the semiconductor element while interposing a member, and curing the resin layer containing the flux component to form a fillet of the resin layer between the metal bonding member and the substrate. And a step of performing.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first resin containing a flux component is provided on the outer periphery of a metal bump provided on an electrode terminal of a semiconductor element or on a wiring pad of a wiring board. Forming a layer consisting of
A step of arranging the semiconductor element face down on a wiring pad formation surface of the wiring board and aligning the metal bumps with the wiring pads of the wiring board; and the aligned metal bumps and the wiring pads. And a step of bonding the flux and the first resin layer containing the flux component is cured to form a fillet of the first resin layer between the metal bump and the wiring board. It is characterized by doing.

In the method for manufacturing a semiconductor device of the fifth invention, the method further comprises the step of forming a second resin layer between the wiring board and the semiconductor element and then curing the second resin layer. You can Further, the formation of the second resin layer can be performed subsequent to the step of forming the layer made of the first resin containing the flux component.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a flux component is contained on the outer periphery of a metal bump provided on an external terminal of a semiconductor package or on a wiring pad of a mounting substrate. A step of forming a layer made of a resin, a step of arranging the semiconductor package on a wiring pad formation surface of the mounting board, and a step of aligning the metal bump with a wiring pad of the mounting board, And a step of heating the metal bump and the wiring pad to bond them together, and curing the first resin layer containing the flux component to provide a space between the metal bump and the mounting substrate. A fillet of the first resin layer is formed.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a low melting point metal layer on a wiring pad of a mounting substrate, and a first step of containing a flux component on the low melting point metal layer. A step of forming a layer made of a resin, a step of mounting a semiconductor package having a lead frame on a wiring pad formation surface of the mounting board, and aligning the lead frame with the wiring pad of the mounting board; A step of heating and bonding the aligned lead frame and the wiring pad, and curing the first resin layer containing the flux component to thereby form the low melting point metal layer and the mounting material. A fillet of the first resin layer is formed between the substrate and the substrate.

In the method of manufacturing a semiconductor device of the sixth and seventh inventions, a step of forming a second resin layer between the mounting substrate and the semiconductor package and then hardening the second resin layer is performed. You can have more.

In the semiconductor device of the present invention, at least a part of the outer periphery of the metal joining member or the first wiring layer on the wiring layer of the substrate is provided.
The resin layer is formed, and the first resin layer is formed so as to form a fillet between the metal joining member and the wiring layer, and the concentration of thermal stress on the metal joining member is relaxed. Therefore, distortion is not generated in the joint portion, the joint strength is increased, and the reliability of the connection portion is improved.

Furthermore, in the step of connecting the semiconductor element or the semiconductor package, the first resin layer is adhered to the surface of the substrate facing the semiconductor element or the semiconductor package. And adhesiveness are good. Therefore, the reflow resistance and the life for the temperature cycle are improved.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a schematic structure of a first embodiment of a semiconductor device of the present invention. In the figure, reference numeral 1
Is the wiring pad 2 on one surface (the upper surface in the figure) of the insulating substrate 1a.
The wiring board in which the is formed is shown.

Here, examples of the insulating substrate 1a include a glass substrate, a ceramic substrate, a resin-impregnated glass cloth substrate, and a resin substrate such as a polyimide resin tape. Then, the wiring board 1 in which a wiring layer made of copper, a copper-based alloy, gold or the like is formed on at least one main surface of the insulating substrate 1a is used. The wiring layer is formed by etching copper foil on a resin-impregnated glass cloth substrate or a resin substrate, and by using an inorganic material-based insulating substrate such as a glass substrate or a ceramic substrate, a physical layer such as vacuum deposition or sputtering is used. A method of forming a thin film by a vapor deposition (PVD) method or a chemical vapor deposition (CVD) method and then patterning it, or a method of printing a conductive paste in a predetermined pattern and then firing it can be used.

Further, on the copper wiring layer, in order to prevent the oxidation of copper and strengthen the bonding with the bumps described later, Ni is used.
It can be formed by stacking a layer and an Au layer. Although the Ni—Au layer may be formed over the entire wiring layer, it is possible to sufficiently enhance the effect by forming only the connection wiring pad 2. Further, a solder resist layer of epoxy resin or the like can be provided in a region other than the wiring pad 2.

On the other hand, reference numeral 3 indicates a semiconductor chip made of silicon or the like, and has an electrode pad 4 made of Al. On the electrode pad 4, a barrier metal layer (not shown) is formed by sequentially stacking a Ti film, a Ni film and a Pd film. Then, Sn-P is formed on the barrier metal layer.
Bumps 5 made of solder b are formed. further,
The first resin layer 6 is formed on at least a part of the outer periphery of the solder bump 5. The first resin layer 6 is obtained by curing a resin coating layer that removes the solder oxide film and contains a flux component that prevents solder oxidation.

Then, the semiconductor chip 3 having such solder bumps 5 is placed face down on the wiring substrate 1 and mounted, and the tips of the solder bumps 5 are brought into contact with the wiring pads 2 and soldered. Are joined by melting. In addition, a fillet of the first resin layer 6 is formed between the solder bump 5 and the wiring board 1 thus joined.

The semiconductor device of the first embodiment having such a structure can be manufactured as follows. First, as shown in FIG. 2, a semiconductor wafer 7 made of silicon or the like (for example, a diameter of 6 inches and a thickness of 625 μm) is
After the l electrode pad 4 is formed, a passivation film 8 having an opening (50 μm square) in the center of the electrode pad 4 is formed thereon. The size of the electrode pad 4 is, for example, 100 μm square, and is formed at a pitch of 250 μm in a region corresponding to the peripheral portion of each semiconductor chip (15 mm × 15 mm) formed in a later step.

Next, as shown in FIG. 3, a Ti film 9, a Ni film 10 and a Pd film 11 are formed on the entire surface of the semiconductor wafer 7.
Are sequentially laminated by a method such as sputtering and electron beam evaporation to form a barrier metal layer.

Next, as shown in FIG. 4, a photoresist is applied on the barrier metal layer to form a resist layer 12 having a thickness of about 50 μm, and then the resist layer 12 is formed.
Is exposed and developed so that it overlaps with the Al electrode pad 10
A 0 μm square opening is formed. Then, the resist layer 12
Solder plating is performed in the openings to form a solder layer 13 for forming bumps having a thickness of 50 μm.

The solder plating is carried out as follows. For example, to plate Sn-Pb solder,
Tin 30g / L, Lead 20g / L, Alkylsulfonic acid 1
The semiconductor wafer 7 on which the pattern of the resist layer 12 is formed is dipped in a solution containing 00 g / L and an additive containing a surfactant as a main component, and the barrier metal layer is made into a cathode and Sn is formed at a bath temperature of 20 ° C. Using the Pb solder plate as an anode, electrolytic plating is performed under conditions of a current density of 1 A / dm 2 while gently stirring.

Then, as shown in FIG. 5, after the resist pattern was stripped using acetone or a known resist stripping solution, the Pd film 11 and the Ni film 1 remaining as the underlying electrodes were formed.
0 is removed by etching using an aqua regia etchant. Further, the Ti film 9 is etched using an ethylenediaminetetraacetic acid-based solution.

Then, after applying a rosin-based flux to the semiconductor wafer 7, the solder is reflowed by heating it to a temperature of 220 ° C. for 30 seconds in a nitrogen atmosphere, and as shown in FIG. Solder bump) 5 is formed. Then, after conducting an electrical test, the semiconductor wafer 7 is diced into individual semiconductor chips 3.

Next, as shown in FIG. 7, a resin (flux component-containing resin) 14 containing a flux component for preventing solder oxidation except the solder oxide film is prepared in a paste form, and this is prepared as a flat container 15 After applying an appropriate amount therein, the squeegee 16 is used to evenly level (hereinafter referred to as squeegee) to make the resin thickness 60 μm, for example.

Then, as shown in FIG. 8, the semiconductor chip 3 having the solder bumps 5 is adsorbed on the tool, the tip of the bumps is pressed against the surface of the flux component containing resin 14, and the solder bumps 5 are coated with the resin. To do. Here, it is possible to control the amount of resin applied to the solder bumps 5 by adjusting the thickness of the flux component-containing resin 14 layer after squeezing.

On the other hand, as shown in FIG. 9, an insulating substrate 1a such as a polyimide resin tape, a resin substrate, or a ceramic substrate.
A wiring board 1 having a Cu wiring pad 2 provided on one side thereof and a solder resist layer (not shown) made of epoxy resin or the like formed in a region other than the wiring pad 2 is prepared, and on the wiring pad 2, It is formed by stacking a Ni layer and an Au layer (both not shown) by electroless plating or the like.

The wiring pad 2 of the wiring board 1 and the resin 14 containing the flux component are attached to the tip portion.
The layered solder bumps 5 are aligned and temporarily fixed. Since the flux component-containing resin 14 layer having adhesiveness and adhesiveness is formed on the tip end portion of the solder bump 5, it can be easily temporarily fixed only by applying pressure.

Then, the solder bumps 5 and the wiring pads 2 are joined by passing through a reflow furnace and heating to reflow the solder. The reflow condition is, for example, 15
Set the peak temperature to 220 ° C. for 1 minute at 0 ° C.
A layer of the flux component-containing resin 14 is formed on the outer periphery of the solder bump 5, and the flux component contained in this resin removes the solder oxide film on the bump surface during solder reflow. The pad 2 is well joined. After that, the resin is cured by heating at 150 ° C. for 3 hours to form the first resin layer 6, and the semiconductor device is completed. If the resin is sufficiently hardened by the heating during the solder reflow, the heating here can be omitted.

Further, as shown in FIG. 10, a second resin layer 17 mainly composed of epoxy resin, acrylic resin, silicone resin or the like is formed between the semiconductor chip 3 and the wiring board 1 to further It is possible to increase the reliability of the connection. Furthermore, as shown in FIG. 11, a third resin layer 18 can be coated / formed on the outside of the second resin layer 17. With such a structure, since the adhesion of the resin layer is further improved, the occurrence of resin cracks can be prevented, and the reflow resistance is further improved.

As the first resin, the second resin, and the third resin, the same kind of resin may be used, but those having different physical properties may be used by changing the amount of filler.
When another resin having different physical properties from the first resin is used as the second resin, compared with the structure in which the gap between the semiconductor chip 3 and the wiring board 1 is sealed with one kind of resin. , Can be more reliable. For example, by adding a filler to the second resin, the coefficient of thermal expansion can be lowered, and the stress strain caused by the difference in the coefficient of thermal expansion between the semiconductor chip 3 and the wiring board 1 can be relaxed.

Furthermore, the physical properties of the third resin can be changed from those of the first resin and / or the second resin. For example, by using, as the third resin, a resin having a glass transition temperature Tg higher than those of the first resin and the second resin,
Further, it becomes possible to improve the reflow resistance.

The semiconductor device of the first embodiment thus manufactured has the first resin layer 6 on at least a part of the outer periphery of the solder bump 5, and the first resin layer 6 is provided.
However, since it is formed so as to have a fillet between the solder bump 5 and the wiring substrate 1, the strength of the bump bonding portion is improved. That is, since the first resin layer 6 formed in a fillet shape on the wiring board 1 relieves the concentration of thermal stress on the solder bumps 5, distortion is less likely to occur at the bump bonding portions, and the connection reliability is improved. To do.

Further, since the first resin layer 6 is formed only on the outer periphery of the solder bump 5, no void is generated. Therefore, for example, even when moisture absorption reflow is performed, defects due to voids do not occur. Although voids may occur in the second resin layer 17 formed between the semiconductor chip 3 and the wiring board 1,
Since no voids are generated in the first resin layer 6 formed near the joint of the solder bump 5, a semiconductor device with high connection reliability can be obtained.

Further, since the first resin layer 6 is formed by the method of applying the squeezed paste-like resin to the solder bumps 5, the solder bumps 5 are adjusted by adjusting the resin thickness of the squeegee. It is possible to easily quantify the amount of resin applied to the resin, and to control the formation thickness of the first resin layer 6.

In the semiconductor device of the first embodiment, the first resin layer is formed so as to cover the entire outer circumference of the solder bump, and the resin layer serves as the electrode pad of the semiconductor chip and the wiring pad of the wiring board. It can also be configured to be adhered to each.

The semiconductor device of the first embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to examine the connection reliability. As the semiconductor chip, a 15 mm square silicon chip having 2500 solder bumps formed in the peripheral region was used, and this was mounted on a polyimide resin substrate to prepare a test sample. The temperature cycle test is (-65 ° C x 30 minutes) to (25 ° C x 5 minutes)
~ (150 ° C x 30 minutes) was performed as one cycle.

As a result of the temperature cycle test, no breakage was observed at the connection portion (flip chip connection portion) even after 500 cycles. Further, the same temperature cycle test was performed on the epoxy resin as the second resin filled between the silicon chip and the polyimide resin substrate and then cured, and the same temperature cycle test was performed. I was not able to admit.

Further, as the third resin, epoxy resin, silicone resin, acrylic resin, polyimide resin, or the like is formed on the outside of the silicon chip so as to form a fillet between the resin and the wiring board. When the same temperature cycle test was performed, no fracture was observed at the connection point even after 5000 cycles. further,
The reflow resistance was also improved, and even at a moisture absorption reflow level of 1, no connection failure or resin peeling occurred.

In the first embodiment, the case where Sn—Pb solder bumps are provided as metal bumps has been described.
Au, Ag, Cu, Ni, Fe, Pd, Sn, Pb, B
The bump may be made of a metal selected from i, Zn, In, Sb, and Ge alone, a mixture thereof, or a compound thereof. Also, the wiring pads on the wiring board are made of Au, Ag, C
u, Ni, Fe, Pd, Sn, Pb, Bi, Zn, I
n, Sb, Ge alone, a mixture or compound thereof,
Alternatively, it may be a laminated film. Further, the joining between them is not limited to the fusion joining of metals, but may be, for example, the diffusion joining of metals.

Next, the second to fifth embodiments will be described.

The semiconductor device of the second embodiment is manufactured as follows. First, as shown in FIG. 12, after forming an Al electrode pad 4 on a semiconductor wafer 7 made of silicon or the like (for example, a diameter of 6 inches and a thickness of 625 μm), the central portion of the electrode pad 4 is provided with an opening ( A 90 μm square passivation film 8 is formed. The size of the Al electrode pad 4 is, for example, 100 μm square, and individual semiconductor chips (10 mm × 15 mm) formed in a later step.
Are formed at a pitch of 250 μm in a region corresponding to the peripheral portion of the.

On the Al electrode pad 4 of this semiconductor wafer 7, a ball-shaped gold bump 19 having a small protrusion at its tip is formed.
Form one by one with a wire bonder. The gold bump 19 has a diameter of 85 μm and a height of 70 μm. Then, after conducting an electrical test, the semiconductor wafer is diced into individual semiconductor chips.

Next, a resin containing a flux component (a resin containing a flux component) is prepared in the form of a paste, which is applied in a flat container in an appropriate amount and squeezed to make the resin thickness uniform, for example, 60 μm. You Then, the tip of the gold bump 19 is pressed against the surface of this resin layer, and the flux component containing resin 14 is applied to the outer periphery of the gold bump 19. Here, the amount of resin applied to the gold bumps 19 can be controlled by adjusting the thickness of the flux component-containing resin 14 after squeezing.

Next, this semiconductor chip is flip-chip connected as shown below to form a semiconductor device. That is, as shown in FIG. 13, Cu is formed on one surface of the insulating substrate 1a such as a polyimide resin tape, a resin substrate, or a ceramic substrate.
A wiring board 1 is provided on which wiring pads 2 are provided and a solder resist layer 20 of epoxy resin or the like is formed in a region other than the wiring pads 2, and a Ni layer 21 is formed on the wiring pad 2 by electroless plating or the like. The Au layer 22 is formed by stacking. Next, on the Au layer 22 of the wiring pad 2, Sn-
The 3.5 Ag solder layer 23 is formed by printing or the like.

Then, as shown in FIG. 14, Sn-Ag
The wiring pad 2 having the solder layer 23 formed thereon and the gold bump 19 having the flux component-containing resin 14 layer formed on the outer periphery thereof are aligned and temporarily fixed. At this time, gold bump 1
Since the layer of the flux component-containing resin 14 having adhesiveness and adhesiveness is formed at the tip portion of 9, it can be easily temporarily fixed by only applying pressure.

Then, it is passed through a reflow furnace and heated to Sn.
-By reflowing Ag solder, gold bump 1
9 and the wiring pad 2 (Au layer 22) are joined. The reflow condition is, for example, 150 ° C. for 1 minute, and the peak temperature is set to 220 ° C.

The flux component contained in the resin layer formed on the outer periphery of the gold bump 19 removes the oxide film on the surface of the Sn—Ag solder layer 23 during solder reflow, so that the gold bump 19 and the wiring pad 2 are separated from each other. A good bond is obtained. Then, if necessary, the resin is cured by heating at 150 ° C. for 3 hours, for example. Thus, the first resin layer 6 having a fillet is formed between the gold bump 19 and the wiring pad 2, and the semiconductor device is completed.

It is also possible to carry out the joining by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves without using the solder reflow furnace. In the ultrasonic combined thermocompression bonding method, for example, heating is performed to a temperature of about 200 ° C. with an ultrasonic wave applying tool, ultrasonic waves are applied for 1 second at an ultrasonic intensity of 5 W, and a load of 5 kg is applied to each silicon chip to perform bonding. To do.

In the semiconductor device of the second embodiment thus manufactured, the first resin layer 6 is provided on at least a part of the outer periphery of the gold bump 19, and the first resin layer 6 is
Since the gold bump 19 and the wiring board 1 are formed so as to have a fillet, the strength of the bump bonding portion is improved. That is, since the first resin layer 6 formed in the fillet shape on the wiring pad 2 relaxes the concentration of thermal stress on the bonding portion of the gold bump 19, distortion is less likely to occur at the bump bonding portion, and connection reliability is improved. The property is improved.

Further, since the first resin layer 6 is formed only on the outer periphery of the gold bump 9, no void is generated and no defect caused by the void is generated. Further, the squeegeeed paste-like resin is used for the gold bump 9
Since the first resin layer 6 is formed by applying the squeegee, the amount of resin applied to the gold bumps 19 can be easily quantified by adjusting the resin thickness of the squeegee. It is possible to control the formation thickness of the first resin layer 6.

In the semiconductor device of the second embodiment as well as the first embodiment, the semiconductor chip 3 and the wiring board 1 are
By forming a second resin layer mainly composed of an epoxy resin, an acrylic resin, a silicone resin, or the like, the connection reliability can be further improved. Furthermore, a third resin layer can be coated / formed on the outside of the second resin layer. With such a structure, since the adhesion of the resin layer is further improved, the occurrence of resin cracks can be prevented, and the reflow resistance is further improved.

The semiconductor device of the second embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to check the connection reliability. In addition, as a semiconductor chip, 10 m in which 100 gold bumps were formed in the peripheral region was used.
A m × 15 mm silicon chip was used and mounted on a polyimide resin substrate to give a test sample. The temperature cycle test is (-65 ° C x 30 minutes) to (25 ° C x 5 minutes).
Min) to (150 ° C. × 30 min) as one cycle.

As a result of the temperature cycle test, even after 500 cycles, no breakage was observed at the connection portion.
Also, between the silicon chip and the polyimide resin substrate,
The same temperature cycle test was performed on the epoxy resin filled as the second resin and then cured. As a result, no fracture was observed at the connection point even after 3000 cycles. Further, as the third resin, epoxy resin, silicone resin, acrylic resin, polyimide resin, or the like formed on the outside of the silicon chip so as to have a fillet between the third substrate and the wiring board, the same temperature When a cycle test was conducted, no fracture was observed at the connection point even after 5000 cycles. Further, the reflow resistance was also improved, and even at the moisture absorption reflow level 1, the connection failure and the resin peeling did not occur.

In the second embodiment, the same kind of resin may be used as the first resin, the second resin and the third resin, but the physical properties were changed by changing the amount of filler. You may use the thing. As the metal bumps formed on the electrode pads of the silicon chip, Au ball bumps containing solder or Cu or Pd can be used in addition to gold ball bumps. These ball-shaped bumps are formed by solder wire, Cu wire or Pd.
This can be done by a wire bonder using Au wires mixed with

Next, the semiconductor device of the third embodiment will be described. In this semiconductor device, as shown in FIG.
The tape BGA package 25 is provided on one surface of the mounting substrate 24 in which the Cu wiring pad 2 is provided on one surface of the insulating substrate 1a.
Is installed. The tape BGA package 25 includes a TAB tape 26 made of polyimide resin or the like and an LSI chip 27.
Is mounted face down and mounted via gold bumps 28, and a metal cap 29 is attached to the upper surface. The package size is 30mm square, and Sn-Pb solder ball 30 is 1m on the external terminal of TAB tape.
800 pieces are formed at a pitch of m. Note that reference numeral 31
Indicates an adhesive layer, and 32 indicates a sealing resin layer.

The first resin layer 6 is formed on at least a part of the outer periphery of the solder ball 30. The formation of the first resin layer 6 can be performed using a squeegeeing method as described below. That is, the paste containing flux component-containing resin is applied to a flat container and the surface is squeezed to even out the resin thickness to, for example, 100 μm, and then the solder ball 30 is formed on the surface of the resin layer. The tip is pressed and the resin containing the flux component is applied to the outer periphery.

Then, the solder ball 30 having the layer of the resin containing the flux component formed at the tip and the wiring pad 2 of the mounting substrate 24 are aligned and pressed to temporarily fix them, and then heated to reflow the solder. By doing so, the solder balls 30 and the wiring pads 2 of the mounting substrate 24 are joined. The reflow condition is, for example, 150 ° C. for 1 minute, and the peak temperature is set to 220 ° C.

Since the flux component contained in the resin layer formed on the outer periphery of the solder ball 30 removes the oxide film on the surface during the solder reflow, the solder ball 30
And a good connection with the wiring pad 2 can be obtained. After that, if necessary, for example, by heating at 150 ° C. for 3 hours,
Cure the resin. Thus, the first resin layer 6 having a fillet is formed between the solder ball 30 and the wiring pad 2, and the semiconductor device is completed.

In the semiconductor device of the third embodiment thus manufactured, the first resin layer 6 is provided on at least a part of the outer circumference of the solder ball 30 of the BGA package 25,
Moreover, since the first resin layer 6 forms a fillet with the mounting substrate 24, the strength of the joint portion is improved. That is, since the first resin layer 6 formed in the fillet shape on the mounting substrate 24 relieves the concentration of thermal stress on the joint portion of the solder ball 30, distortion is unlikely to occur at the joint portion, and the connection reliability is improved. Is improved.

In the semiconductor device of this embodiment,
The first resin layer 6 may be formed so as to cover the entire outer circumference of the solder ball 30, and the resin layer may be bonded to the tape BGA package 25 and the mounting substrate 24, respectively.

The semiconductor device of the third embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to check the connection reliability. As a semiconductor package, 30 solder balls having 800 solder ball bumps were formed.
A mm-square tape BGA package was used and mounted on a polyimide resin mounting substrate to obtain a test sample. The temperature cycle test is (-55 ° C x 30 minutes) to (25 ° C x
5 minutes) to (125 ° C. × 30 minutes) were performed as one cycle.

As a result of the temperature cycle test, no breakage was observed at the connection portion even after 1000 cycles. In addition, a similar temperature cycle test was performed on a second resin filled with an epoxy resin as a second resin between the BGA package and the polyimide resin substrate and then cured. Was not recognized. Further, as the third resin, epoxy resin, silicone resin, acrylic resin, polyimide resin or the like formed on the outside of the BGA package 25 so as to have a fillet between the mounting substrate 24, When the same temperature cycle test was performed, no fracture was observed at the connection point even after 5000 cycles. Further, the reflow resistance was also improved, and even at the moisture absorption reflow level 1, the connection failure and the resin peeling did not occur.

In the third embodiment, the same kind of resin may be used as the first resin, the second resin and the third resin, but the physical properties are changed by changing the amount of filler. You may use the thing. Also, an example in which Sn-Pb solder balls are formed as ball bumps of a BGA package has been described, but Ag, Cu, Bi, Zn, In, S
The bump may be a single metal such as b, Cu, or Ge, or a mixture or compound thereof.

Further, the first resin layer 6 was formed on the outer circumference of the solder ball 30 by the squeezing method.
You may perform on the wiring pad 2 of the mounting substrate 24 by the method shown below. That is, as shown in FIG. 16, the flux component-containing resin 14 may be printed on the wiring pad 2 of the mounting substrate 24 by using the screen mask 33, and further, as shown in FIG. It can also be used for transfer onto the wiring pad 2 of the mounting substrate 24.

Next, a fourth embodiment will be described. In the fourth embodiment, as shown in FIG. 18, a plurality of (for example, four) semiconductor chips 3 having solder bumps 5 are mounted face down on the wiring pad 2 formation surface of the wiring substrate 1. ing. The chip size is 8 mm square,
The number of bumps is 1200.

Then, in each semiconductor chip 3, the solder bumps 5 are brought into contact with the wiring pads 2 and joined by melting the solder. Further, a first resin layer 6 which is a cured layer of a resin containing a flux component is formed on at least a part of the outer periphery of the solder bump 5, and a fillet of the first resin layer 6 is formed between the solder bump 5 and the wiring board 1. Has been done.

The bonding of the bumps and the formation of the first resin layer 6 can be performed as follows. That is, the paste containing flux component-containing resin is applied in a flat container and the surface is squeezed to even out the resin thickness to, for example, 60 μm, and then the solder bumps 5 are formed on the surface of the resin layer. The tip portion is pressed, and the flux component containing resin is applied to the outer periphery of the solder bump 5.

Next, with respect to the first semiconductor chip 3, first, the solder bumps 5 having the resin layer containing the flux component formed on their tip portions and the wiring pads 2 of the wiring board 1 are aligned and pressed to temporarily fix them. . Next, the second semiconductor chip is also temporarily pressure-bonded and fixed on the wiring board 1 by the same method, and similarly the third and fourth semiconductor chips are also temporarily pressure-bonded.

Even if the semiconductor chips 3 are arranged with a very small gap of 0.5 mm, the flux component-containing resin applied to the outer periphery of the solder bump 5 reaches the mounting area of the adjacent semiconductor chip 3. Without protruding, the second and subsequent semiconductor chips can be easily temporarily press-bonded similarly to the first semiconductor chip.

Then, heat is applied to reflow the solder,
The solder bumps 5 of all the semiconductor chips 3 are joined to the wiring pads 2 of the wiring board 1. The reflow condition is
For example, the temperature is set to 150 ° C. for 1 minute, and the peak temperature is set to 220 ° C.

With respect to each semiconductor chip 3, the flux component contained in the resin layer formed on the outer periphery of the solder bump 5 removes the oxide film on the surface during solder reflow. Good bonding with the pad 2 can be obtained. Then, if necessary, for example, 1
The flux component-containing resin is cured by heating at 50 ° C. for 3 hours. Thus, the first resin layer 6 having a fillet is formed between the solder bumps 5 and the wiring board 1, and the semiconductor device is completed.

In the semiconductor device of the fourth embodiment thus manufactured, the first resin layer 6 is provided on at least a part of the outer periphery of the solder bump 5, and the first resin layer 6 is provided.
However, since the fillet is formed between the wiring board 1 and the wiring board 1, the strength of the bump bonding portion is improved. That is, the first resin layer 6 formed in a fillet shape on the wiring board 1 is
Since the concentration of thermal stress on the joint portion of the solder bump 5 is relaxed, the joint portion is less likely to be distorted, and the connection reliability is improved.

Further, although the plurality of semiconductor chips 3 are arranged close to each other, the flux component containing resin does not extend to the mounting region of the adjacent semiconductor chips 3, so that the plurality of semiconductor chips 3 are grouped together. It can be flip-chip mounted. Therefore, it is not necessary to repeat the complicated steps of flux application, reflow, and cleaning for each semiconductor chip, the process is simplified, and the thermal history during solder reflow can be reduced to one time, and reliability is improved. improves.

The semiconductor device of the fourth embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to check the connection reliability. As the semiconductor chip, four 8 mm square silicon chips having 1200 solder bumps were used, and these were mounted on a polyimide resin substrate to obtain a test sample having an MCM (multi-chip module) structure. . The temperature cycle test is
(-65 ° C x 30 minutes) ~ (25 ° C x 5 minutes) ~ (150 ° C
X 30 minutes) was performed as one cycle.

As a result of the temperature cycle test, even after 500 cycles, no breakage was observed at the connection portion.
Further, as shown in FIG. 19, the same applies to the device in which the second resin layer 17 is formed by filling the epoxy resin between the semiconductor chips 3 and the wiring board 1 of the polyimide resin and curing the epoxy resin. When a temperature cycle test was conducted, no fracture was observed at the connection point even after 3000 cycles.

Further, as shown in FIG. 20, on the outside of the second resin layer 17, epoxy resin, silicone resin,
A similar temperature cycle test was performed on the third resin layer 18 made of an acrylic resin, a polyimide resin, or the like, which was coated so as to form a fillet with the wiring board 1. No breakage was observed at the connection points. Further, the reflow resistance was also improved, and even at the moisture absorption reflow level 1, the connection failure and the resin peeling did not occur.

In the fourth embodiment, the same kind of resin may be used as the first resin, the second resin and the third resin, but the physical properties were changed by changing the amount of filler. You may use the thing.

Although the example in which the solder bump is formed as the metal bump has been described, Au, Ag, Cu, Ni, Fe,
The bump may be made of a metal selected from Pd, Sn, Pb, Bi, Zn, In, Sb, and Ge alone, or a mixture or compound thereof. Further, the wiring pads of the wiring board are also made of Au, Ag, Cu, Ni, Fe, Pd, Sn, P.
It may be b, Bi, Zn, In, Sb, Ge alone, a mixture or compound thereof, or a laminated film. Further, the joining between them is not limited to the fusion joining of metals, but may be, for example, the diffusion joining of metals.

Next, the fifth embodiment will be described. In the fifth embodiment, as shown in FIG. 21, two semiconductor chips 3a and 3b having solder bumps 5 are arranged face down on the wiring pad 2 formation surface of the wiring board 1 in two stages. It is mounted in a stack.

In each of the semiconductor chips 3, a first resin layer 6 which is a cured layer of a resin containing a flux component is formed on at least a part of the outer periphery of the solder bump 5. In addition, the first semiconductor chip 3a arranged on the lower side
The solder bumps 5a are brought into contact with the wiring pads 2 of the wiring board 1 and joined by melting the solder. Then, the solder bumps 5a of the first semiconductor chip 3a and the wiring board 1
A fillet of the first resin layer 6 is formed between and.

In addition, the second semiconductor chip 3b is placed on the back surface of the first semiconductor chip 3a thus flip-chip mounted, and the solder bumps 5b of the second semiconductor chip 3b and the back surface of the first semiconductor chip 3a are mounted. The connection pads (not shown) formed on the above are joined by melting the solder. A fillet of the first resin layer 6 is formed between the solder bump 5b of the second silicon chip 3b and the first semiconductor chip 3a.

The semiconductor device of the fifth embodiment is manufactured as follows. First, at a predetermined position of a semiconductor chip such as silicon (first semiconductor chip 3a), R
After forming a hole having a depth of 70 μm by using IE (reactive ion etching), an oxide film such as SiO 2 is formed on the inner wall surface of the hole.

Then, the surface on the hole thus formed is T-shaped.
After forming the i / Cu sputtered film, the inside of the hole is filled with Cu plating. Further, the solder bumps 5a are formed on the electrode terminals on the surface of the first semiconductor chip 3a in the same manner as in the first embodiment.
To form. Then wrap the back of this chip and
Grind to a thickness of 0 μm. By this lapping, the hole filled with Cu becomes a conduction hole (through plug) 35 penetrating from the front surface to the back surface of the first chip 3a.

Next, the paste containing flux component-containing resin is applied in a flat container and the surface is squeezed to even out the resin thickness to, for example, 60 μm. The tips of the solder bumps 5a of the first semiconductor chip 3a are pressed against the solder bumps 5a.
A resin containing a flux component is applied to the outer periphery of a.

Next, the solder bumps 5a having the flux component-containing resin layer formed on the tips thereof and the wiring pads 2 of the wiring board 1 are aligned and pressed to temporarily fix them. Then
The first semiconductor chip 3 is heated by reflowing the solder.
For a, the solder bump 5a is bonded to the wiring pad 2 of the wiring board 1. The reflow condition is, for example, 150 ° C. for 1 minute, and the peak temperature is set to 220 ° C.

With respect to the first semiconductor chip 3a, since the flux component contained in the resin layer formed on the outer periphery of the solder bump 5a removes the oxide film on the surface during solder reflow, the solder bump 5a and the wiring board 1 Good connection with the wiring pad 2 can be obtained. Thereafter, if necessary, the flux component-containing resin is cured by heating at 150 ° C. for 3 hours, for example. Thus, the first resin layer 6 having a shape having a fillet is formed between the solder bump 5a of the first semiconductor chip 3a and the wiring board 1.

Next, similarly to the first semiconductor chip 3a, the second semiconductor chip 3b having the solder bumps 5b formed on the electrode terminals is prepared, and the first semiconductor is also attached to the tip portions of the solder bumps 5b. A flux component-containing resin layer is formed by a squeezing method similarly to the chip 3a. And
Such a second semiconductor chip 3b is placed on the back surface of the first semiconductor chip 3a in an overlapping manner, and the solder bumps 5b of the second semiconductor chip 3b are connected to the back surface of the first semiconductor chip 3a. Align the pad (land of the through plug) with the pad and temporarily secure it. After that, by heating the reflow furnace to reflow the solder,
The solder bumps 5b of the semiconductor chip 3b are bonded to the connection pads on the back surface of the first semiconductor chip 3a. Then, if necessary, for example, by heating at 150 ° C. for 3 hours,
The resin containing the flux component is cured. Thus, the second
The first resin layer 6 having a shape having a fillet is formed between the solder bump 5b of the semiconductor chip 3b and the first semiconductor chip 3a (back surface).

In the semiconductor device of the fifth embodiment thus manufactured, the first and second semiconductor chips 3a,
3b has a first resin layer 6 on at least a part of the outer periphery of the solder bumps 5a, 5b, and the first resin layer 6 is between the wiring substrate 1 and the back surface of the first semiconductor chip 3a. Since the fillet is formed on the bump, the strength of the bump bonding portion is improved. That is, the first resin layer 6 formed in a fillet shape on the wiring board 1 or the first semiconductor chip 3a is connected to the solder bumps 5a and 5b, respectively.
Since the concentration of the thermal stress on the joint portion of b is relaxed, the joint portion is less likely to be distorted and the connection reliability is improved.

Since the first resin layer 6 is formed by the squeezing method in each semiconductor chip,
By adjusting the resin thickness of the squeegee, the solder bumps 5
The amount applied to a and 5b can be easily quantified, and the defect that the applied resin wraps around to the back surface of the semiconductor chip does not occur. That is, in a conventional semiconductor device in which thin semiconductor chips having a thickness of about 50 μm are stacked in a plurality of layers and resin-sealed, a large amount of resin squeezes out, and the squeezed-out resin crawls along the side surface of the semiconductor chip. Although there is a problem that it wraps around on the back surface and adheres to the electrode on the back surface and the tool for flip chip connection, in the fifth embodiment,
Since the first resin layer 6 is formed only on the outer peripheries of the solder bumps 5a and 5b, the amount of resin is small and the phenomenon of wrapping around the back surface of the semiconductor chip does not occur.

The semiconductor device of the fifth embodiment manufactured according to the above steps was actually subjected to a temperature cycle test to check the connection reliability. The temperature cycle test is (-6
5 ° C x 30 minutes) ~ (25 ° C x 5 minutes) ~ (150 ° C x 30 minutes)
Min) as one cycle.

As a result of the temperature cycle test, no breakage was observed at the connection portion even after 500 cycles.
Further, as shown in FIG. 22, epoxy resin is filled and cured between the first semiconductor chip 3a and the second semiconductor chip 3b and between the first semiconductor chip 3a and the wiring board 1. As a result, a similar temperature cycle test was performed on the device on which the second resin layer 17 was formed.
Even after 3000 cycles, no fracture was observed at the connection points.

Further, as shown in FIG. 23, on the outside of the second resin layer 17, epoxy resin, silicone resin,
A similar temperature cycle test was performed on the third resin layer 18 made of an acrylic resin, a polyimide resin, or the like, which was coated so as to form a fillet with the wiring board 1. No breakage was observed at the connection points. Further, the reflow resistance was also improved, and even at the moisture absorption reflow level 1, the connection failure and the resin peeling did not occur.

In the fifth embodiment, the same kind of resin may be used as the first resin, the second resin and the third resin, but the physical properties were changed by changing the amount of filler. You may use the thing.

Although the example in which the solder bump is formed as the metal bump has been described, Au, Ag, Cu, Ni, Fe,
The bump may be made of a metal selected from Pd, Sn, Pb, Bi, Zn, In, Sb, and Ge alone, or a mixture or compound thereof. Further, the wiring pads of the wiring board are also made of Au, Ag, Cu, Ni, Fe, Pd, Sn, P.
It may be b, Bi, Zn, In, Sb, Ge alone, a mixture or compound thereof, or a laminated film. Further, the joining between them is not limited to the fusion joining of metals, but may be, for example, the diffusion joining of metals.

Although the example of the structure in which the semiconductor chips are stacked in two stages is shown, the semiconductor chips may be stacked in three stages or more, or the semiconductor chips may be stacked in a plurality of stages in the MCM structure shown in the fourth embodiment. Good.

Next, sixth to eighth embodiments of the present invention will be described.

The semiconductor device of the sixth embodiment is manufactured as follows. First, an Al electrode pad is formed on a semiconductor wafer such as silicon (for example, a diameter of 6 inches and a thickness of 625 μm), and then a passivation film having an opening at the center of the electrode pad is formed thereon. In addition,
The size of the Al electrode pad is, for example, 80 μm square, and individual semiconductor chips (3 mm × 3 mm) formed in the subsequent process
Are formed at a pitch of 120 μm in a region corresponding to the peripheral portion of the.

On the Al electrode pad of this semiconductor wafer,
Ball-shaped gold bumps each having a small protrusion at the tip are formed one by one with a wire bonder. The diameter of the gold bump is 60μ
m, and the height is 70 μm. Note that gold bumps can also be formed by a plating method. Then, after conducting an electrical test, the semiconductor wafer is diced into individual semiconductor chips.

On the other hand, as shown in FIG. 24, an insulating substrate 1 such as a polyimide resin tape, a resin substrate or a ceramic substrate is used.
A wiring board 1 having a Cu wiring pad 2 provided on one surface of a and a solder resist layer 20 such as an epoxy resin formed in a region other than the wiring pad 2 is prepared, and Sn-Pb, A solder layer 23 of Sn-Ag or the like is formed by a printing method. The solder layer 23 may be formed by a plating method or a ball forming and mounting method using a wire bonder. Alternatively, the solder layer 23 may be formed on the Au layer 22 after the Ni layer 21 and the Au layer 22 are formed on the wiring pad 2 by electroless plating.

Next, the solder layer 23 thus formed
A resin containing a flux component prepared in a paste form (a resin containing a flux component) is printed and formed on the above by, for example, squeezing from above a screen mask to form a resin layer 14 containing a flux component. Then, so as to cover the flux component-containing resin layer 14,
A film-shaped or paste-shaped second resin layer 17 mainly composed of epoxy resin, acrylic resin, silicone resin or the like is formed on the entire surface of the wiring board 1.

Next, the above semiconductor chips are flip-chip connected as shown below to obtain a semiconductor device.

That is, as shown in FIG. 25, the wiring pad 2 on which the solder layer 23 and the flux component containing resin layer are respectively formed and the gold bump 19 formed on the electrode pad 4 of the semiconductor chip 3 are aligned with each other. Then, joining is performed by a thermocompression bonding method, an ultrasonic combined thermocompression bonding method, or the like.

In the thermocompression bonding method, for example, at a temperature of 200 degrees, 2
Heat for 0 seconds to bond. In the ultrasonic thermocompression bonding method, 2
Heating is performed at a temperature of 00 degrees, ultrasonic waves are applied at an ultrasonic wave intensity of 5 W for 1 second, and a load of 100 g per bump is applied to perform bonding.

In this way, the gold bump 19 and the wiring pad 2 are bonded to each other via the solder layer 23. Then, for example, 1
By heating at 50 ° C. for 3 hours, the flux component-containing resin layer and the second resin layer 17 formed thereon are cured. Thus, as shown in FIG. 25, the first resin layer 6 having a fillet is formed between the gold bumps 19 and the wiring board 1, and the outer side thereof is covered and sealed with the second resin layer 17. A semiconductor device having the above structure is completed.

The semiconductor device of the sixth embodiment thus manufactured has the first resin layer 6 on the outer circumference of the solder layer 23 on the wiring pad 2, and the first resin layer 6 is a gold bump. Since it is formed so as to have a fillet between 19, the solder layer 23 and the wiring board 1, the strength of the bump bonding portion is improved. That is, since the fillet-shaped first resin layer 6 relaxes the concentration of thermal stress on the bonding portion of the gold bump 19, distortion is less likely to occur at the bump bonding portion, and the connection reliability is improved.

In addition, during the solder reflow, the solder layer 23
The flux component contained in the resin layer formed above removes the oxide film on the surface of the solder layer 23. Therefore, even if an excessive load or high temperature is not applied, Au-S
The n intermetallic compound is uniformly formed, and good bonding between the gold bump 19 and the wiring pad 2 is obtained. Further, since the second resin layer 17 mainly composed of epoxy resin, acrylic resin, silicone resin or the like is formed outside the first resin layer 6, the connection reliability is further improved.

The semiconductor device of the sixth embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to check the connection reliability. As the semiconductor chip, a 3 mm square silicon chip in which 50 gold bumps were formed in the peripheral region was used, and this was mounted on a polyimide resin substrate to obtain a test sample. The temperature cycle test is (-65 ° C x 30 minutes) to (25 ° C x 5 minutes) to (15
One cycle was performed at 0 ° C. for 30 minutes.

As a result of the temperature cycle test, even after 3000 cycles, no breakage was observed at the connection portion.

The semiconductor device of the seventh embodiment is manufactured as follows. First, as shown in FIG. 26, as in the sixth embodiment, a semiconductor wafer 7 made of silicon or the like is used.
After forming the gold bumps 19 on the Al electrode pads 4 (for example, diameter 6 inches and thickness 625 μm), the gold bumps 1
9 is pressed against the surface of the resin containing the flux component, and the resin 14 containing the flux component is attached to the outer periphery of the gold bump 19.
Apply. Reference numeral 8 indicates the passivation film 8. Then, after conducting an electrical test, the semiconductor wafer is diced into individual semiconductor chips.

On the other hand, as shown in FIG. 27, an insulating substrate 1 such as a polyimide resin tape, a resin substrate, or a ceramic substrate is used.
A wiring board 1 having a Cu wiring pad 2 provided on one surface of a and a solder resist layer 20 such as an epoxy resin formed in a region other than the wiring pad 2 is prepared, and Sn-Pb, Solder layer 23 such as Sn-Ag
Are formed by a printing method, a plating method, or a ball forming and mounting method using a wire bonder. Wiring pad 2
Ni layer 21 and Au layer 22 by electroless plating or the like
Alternatively, the solder layer 23 may be formed on the Au layer 22 after the layers are laminated. Then, epoxy resin, on the entire surface of the wiring substrate 1 on which the solder layer 23 is formed in this way,
A film-shaped or paste-shaped second resin layer 17 mainly containing acrylic resin, silicone resin or the like is formed.

Next, the above-mentioned semiconductor chip is flip-chip connected as shown below to obtain a semiconductor device.
That is, the wiring pad 2 of the wiring board 1 and the gold bump 19 having the flux component-containing resin 14 layer formed on the outer periphery thereof are aligned with each other and bonded by a thermocompression bonding method, an ultrasonic combined thermocompression bonding method or the like.

In the thermocompression bonding method, for example, at a temperature of 200 degrees, 2
Heat for 0 seconds to bond. In the ultrasonic thermocompression bonding method, 2
Heating is performed at a temperature of 00 degrees, ultrasonic waves are applied at an ultrasonic wave intensity of 5 W for 1 second, and a load of 100 g per bump is applied to perform bonding. Thus, the gold bump 19 and the wiring pad 2
And are joined via the solder layer 23. Then, the flux component-containing resin 14 layer and the second resin layer 17 formed on the wiring board 1 are cured by heating at 150 ° C. for 3 hours, for example.

Thus, as shown in FIG. 28, the first resin layer 6 having a shape having a fillet is formed between the gold bump 19 and the wiring board 1, and the outer side thereof is covered with the second resin layer 17. -A semiconductor device having a sealed structure is completed.

In the semiconductor device of the seventh embodiment thus manufactured, the first resin layer 6 having the fillet is formed between the gold bump 19, the solder layer 23 and the wiring board 1, and the first resin layer 6 is formed. Since the resin layer 6 reduces the concentration of thermal stress on the joint portion of the gold bump 19, the strength of the bump joint portion is improved.

Further, during the solder reflow, the gold bumps 19
The oxide film on the surface of the solder layer 23 is removed by the flux component contained in the resin layer formed on the outer periphery of the solder layer 23. Therefore, even if an excessive load or high temperature is not applied, Au-
The Sn intermetallic compound is uniformly formed, and good bonding between the gold bump 19 and the wiring pad 2 is obtained. Further, since the second resin layer 17 mainly composed of epoxy resin, acrylic resin, silicone resin or the like is formed outside the first resin layer 6, the connection reliability is further improved.

The semiconductor device of the seventh embodiment manufactured according to the above steps was actually subjected to a temperature cycle test to check the connection reliability. As the semiconductor chip, a 3 mm square silicon chip in which 50 gold bumps were formed in the peripheral region was used, and this was mounted on a polyimide resin substrate to obtain a test sample. The temperature cycle test is (-65 ° C x 30 minutes) to (25 ° C x 5 minutes) to (15
One cycle was performed at 0 ° C. for 30 minutes.

As a result of the temperature cycle test, even after 3000 cycles, no breakage was observed at the connection portion.

The semiconductor device of the eighth embodiment is manufactured as follows. First, in the same manner as in the sixth embodiment, after gold bumps were formed on the Al electrode pads of a semiconductor wafer such as silicon (for example, a diameter of 6 inches and a thickness of 625 μm) and an electrical test was performed, The semiconductor wafer is diced into individual semiconductor chips.

On the other hand, as shown in FIG. 29, an insulating substrate 1 such as a polyimide resin tape, a resin substrate, or a ceramic substrate is used.
A wiring board 1 having a Cu wiring pad 2 provided on one surface of a and a solder resist layer 20 such as an epoxy resin formed in a region other than the wiring pad 2 is prepared, and Sn-Pb, A solder layer 23 of Sn-Ag or the like is formed by a printing method. The solder layer 23 may be formed by a plating method or a ball forming and mounting method. In addition, the Ni layer 2 is formed on the wiring pad 2 by electroless plating or the like.
1 and the Au layer 22 are laminated to form the Au layer 22.
You may form the said solder layer 23 on it.

Then, a layer of the resin 14 containing a flux component prepared in a paste form is formed on the entire surface of the wiring board 1 on which the solder layer 23 is formed in this manner. After that, the wiring board 1 is formed so as to cover the 14 layers of the flux component-containing resin.
A film-shaped or paste-shaped second resin layer 17 mainly composed of an epoxy resin, an acrylic resin, a silicone resin, or the like is formed on the upper surface.

Next, the above-mentioned semiconductor chip is flip-chip connected as shown below to obtain a semiconductor device.
That is, as shown in FIG. 30, the wiring pads 2 of the wiring substrate 1 and the gold bumps 1 of the semiconductor chip 3 on which the 14 layers of the flux component-containing resin and the second resin layer 17 are formed on the entire surface.
9 and 9 are aligned and joined by a thermocompression bonding method, a thermocompression bonding method using ultrasonic waves, or the like.

In the thermocompression bonding method, for example, at a temperature of 200 degrees, 2
Heat for 0 seconds to bond. In the ultrasonic thermocompression bonding method, 2
Heating is performed at a temperature of 00 degrees, ultrasonic waves are applied at an ultrasonic wave intensity of 5 W for 1 second, and a load of 100 g per bump is applied to perform bonding.

Thus, the gold bump 9 and the Cu wiring pad 2
After being joined via the solder layer 23, for example, at 150 ° C.
By heating for 3 hours, the flux component containing resin 14 layer formed on the entire surface of the wiring board 1 and the second resin layer 17 formed thereon are cured.

In the semiconductor device of the eighth embodiment thus manufactured, the first resin layer 6 having the fillet is formed between the gold bump 19, the solder layer 23 and the wiring board 1, and the first resin layer 6 is formed. Since the resin layer 6 reduces the concentration of thermal stress on the joint portion of the gold bump 19, the strength of the bump joint portion is improved.

At the time of solder reflow, the oxide film on the surface of the solder layer 23 is removed by the flux component contained in the resin layer formed on the entire surface of the wiring board 1. Therefore, even if an excessive load or high temperature is not applied, Au-S
The n intermetallic compound is uniformly formed, and good bonding between the gold bump 19 and the wiring pad 2 is obtained. Further, the first resin layer 6 corresponds to the solder layer 23 corresponding to the area of the wiring pad 2.
The second resin layer 17 is formed not only on the upper side but also on the area where the wiring pad 2 is not formed, so that the adhesiveness between the resin layers and the first resin layer are formed. Adhesion between 6 and the wiring board 1 is improved, and reflow resistance is improved.

The semiconductor device of the eighth embodiment manufactured according to the above-described steps was actually subjected to a temperature cycle test to check the connection reliability. As the semiconductor chip, a 3 mm square silicon chip in which 50 gold bumps were formed in the peripheral region was used, and this was mounted on a polyimide resin substrate to obtain a test sample. The temperature cycle test is (-65 ° C x 30 minutes) to (25 ° C x 5 minutes) to (15
One cycle was performed at 0 ° C. for 30 minutes.

As a result of the temperature cycle test, even after 3000 cycles, no breakage was observed at the connecting portion.

Next, another embodiment of the present invention will be described.

The semiconductor device of the ninth embodiment is manufactured as follows. First, as shown in FIG. 31, a semiconductor package 37 (for example, TSOP package) having a lead frame 36 is prepared. As the material of the lead frame 36, Cu, 42 alloy or the like is used.

On the other hand, as shown in FIG. 32, an insulating substrate 1 such as a polyimide resin tape, a resin substrate, or a ceramic substrate is used.
A Cu wiring pad 2 is provided on one surface of a, and a solder resist layer (not shown) is provided in a region other than the wiring pad 2.
A mounting board 24 (board size 50 mm square) on which is formed is prepared, and Sn-Pb and Sn-A are mounted on the wiring pad 2.
The solder layer 23 such as g is formed by a printing method, a plating method, or a ball forming and mounting method. Next, a resin containing a flux component prepared in a paste form (a resin containing a flux component) is formed on the solder layer 23 thus formed.
Is applied by, for example, a printing method to form a flux component-containing resin 14 layer.

Next, the semiconductor package 37 is aligned and mounted on the mounting substrate 24. That is, as shown in FIG. 33, the solder layer 23 and the flux component-containing resin 1
After aligning the wiring pad 2 in which four layers are sequentially formed with the lead frame 36 of the semiconductor package 37, the solder is reflowed by passing through a reflow furnace,
The lead frame 36 and the wiring pad 2 of the mounting substrate 24 are joined. The reflow condition is, for example, 150 ° C. for 1 minute, and the peak temperature is set to 220 ° C.

Thereafter, if necessary, the flux component-containing resin layer is cured by heating, for example, at 150 ° C. for 3 hours. In this way, the lead frame 36 and the wiring pad 2 of the mounting substrate 24 are bonded via the solder layer 23, and the first resin layer 6 having a shape having a fillet is formed between the solder bonding portion and the mounting substrate 24. The completed semiconductor device is completed.

The semiconductor device of the ninth embodiment manufactured according to the above steps was actually subjected to a temperature cycle test to check the connection reliability. As the semiconductor package, a TSOP package having a 16-pin lead frame was used, and this was mounted on a wiring board for mounting to obtain a test sample. The temperature cycle test is (-40 ℃
× 30 minutes)-(25 ° C × 5 minutes)-(125 ° C × 30 minutes)
Was performed as one cycle.

As a result of the temperature cycle test, no breakage was observed at the connection portion even after 1000 cycles.

In this embodiment, S is placed on the wiring pad.
Although the example of forming the n-Pb solder layer is described, Ag, C
A layer of a metal selected from u, Bi, Zn, In, Sb, Cu and Ge alone, or a mixture or compound thereof may be formed.

Further, in order to form the layer of the flux component containing resin 14 on the solder layer 23, for example, a coating method using a metal mask can be adopted. The flux component-containing resin 14 layer may be formed on the entire surface of the mounting substrate 24. Further, 14 layers of resin containing flux components may be formed on the lead frame side of the semiconductor package.

The semiconductor device of the tenth embodiment is manufactured as follows. First, as shown in FIG.
After forming a layer 38 of a low melting point metal such as solder on a region of the wiring board 1 where wiring pads (not shown) are formed, a resin containing a flux component is formed on the low melting point metal layer 38. 14 layers are formed by a printing method or a dispensing method.

Next, as shown in FIG. 35, the face-up semiconductor chip 3 is mounted on the low melting point metal layer 38 and die bonded. That is, the low melting point metal such as solder is melted by heating to fuse the semiconductor chip 3. Next, the electrode pads of the semiconductor chip 3 and the wiring board 1
After connecting (wire bonding) with the wiring pad (not shown) of (1) by the gold wire 39, the resin sealing layer 40 is formed on the outer side to complete the semiconductor device.

In the semiconductor device of the tenth embodiment thus manufactured, the first resin having the fillet is formed between the low melting point metal layer 38 and the wiring board 1 by hardening the resin 14 layer containing the flux component. Since the layer 6 is formed and the first resin layer 6 relieves the concentration of thermal stress on the die bonding portion, the strength of the joint portion is improved.

When the low melting point metal layer 38 is heated and melted,
The flux component contained in the resin layer formed on this layer removes the oxide film on the surface of the low melting point metal layer 38. Therefore, good joining with a low melting point metal can be obtained.

In this embodiment, the example in which the semiconductor chip is die-bonded on the wiring pad of the wiring board has been described. However, when the semiconductor chip is mounted on the island of the lead frame serving as the board, the die-bonding is similarly performed. You may go.

Furthermore, in each of the following embodiments,
The same effects as those of the above-described embodiments can be obtained.

In the eleventh embodiment, as shown in FIG. 36, in the semiconductor device formed in the same manner as in the first embodiment, the first resin formed on the joint portion of the solder bumps 5 adjacent to each other. The fillets of the layer 6 are connected to each other.

In such a structure, the solder bumps 5 are formed on the semiconductor chip 3 side as in the first embodiment, while the resin layer containing the flux component is thinly formed on the entire surface of the wiring board 1 to a thickness of, for example, 20 μm. It is possible to form it to a thickness. After the solder bumps 5 and the wiring pads 2 of the wiring board 1 are aligned with each other and pressed and temporarily fixed, 220 ° C.
The solder bumps 5 are bonded to the wiring pads 2 by reflowing the solder by placing them in a reflow furnace whose peak temperature is set to.

In this way, the first portion is formed on the joint portion of the solder bump 5.
The fillet of the resin layer 6 is formed, and the entire wiring board 1 is covered with the first resin layer 6. Further, a second resin layer may be formed between the first resin layer 6 and the semiconductor chip 3.

In the twelfth embodiment, as shown in FIG. 37, in the structure in which the electrode pads (not shown) of the semiconductor chip 3 and the wiring pads 2 of the wiring board 1 are joined by a large number of solder bumps 5. The first resin layer 6 having a fillet with the wiring board 1 is formed only at the joints of the solder bumps 5 arranged in the peripheral region of the semiconductor chip 3. Then, a second resin layer 17 is formed on the outside of the solder bumps 5 arranged in the other region (the central portion of the semiconductor chip) and is sealed with this resin layer. Such a structure is applied by controlling the amount of the resin 14 containing the flux component applied on the solder bumps 5 of the semiconductor chip 3 or on the wiring substrate 1 side to be small, or in the peripheral region and the central portion. It can be easily created by changing the amount.

Further, in the thirteenth to sixteenth embodiments, as shown in FIGS. 38 to 41, the connection pads 42 of the semiconductor chip or the semiconductor package 41 and the wiring pads 2 of the wiring board 1 have a large number of solder bumps 5. In the structure joined by, the fillet of the first resin layer 6 is formed between each solder bump 5 and the wiring board 1, and the resin bump is formed between the solder bump 5 and the semiconductor chip or the semiconductor package 41. The fillet of layer 43 is formed. The resin forming the resin layer 43 may be the same as or different from the resin forming the first resin layer 6, but the resin layer containing the flux component is cured.

The solder bumps 5 do not have to be ball-shaped, but may be elongated protrusions. Further, a sealing layer made of a second resin may be formed between the first resin layer 6 and the resin layer 43.

To manufacture a semiconductor device having such a structure, first, solder bumps are formed on a semiconductor wafer in the same manner as in the first embodiment, and a resin layer containing a flux component is formed at the tip of the solder bump. After forming, the resin which is the same as or different from the resin containing the flux component is applied to the entire wafer by spin coating. A centrifugal force forms a fillet-shaped resin layer that covers the solder bumps. After that, the tops of the solder bumps are polished to expose the metal portions, and then flip-chip connection is performed as in the first embodiment to complete the semiconductor device.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.

[0163]

As is apparent from the above description, in the present invention, the resin layer is formed in a fillet shape between the metal material and the substrate, so that the concentration of thermal stress on the metal material is relaxed. To be done. Therefore, distortion is not generated in the joint portion, the joint strength is increased, and the reliability of the connection portion is improved.

Further, since the resin layer is adhered to the surface of the substrate facing the semiconductor element or the semiconductor package, the adhesion and the adhesion between the resin layer and the substrate are good. Therefore, the reflow resistance and the life for the temperature cycle are improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 7 is a drawing for explaining the manufacturing method of the semiconductor device according to the first embodiment.

FIG. 8 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 9 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 10 is a sectional view showing a structure in which a second resin layer is further formed in the semiconductor device of the first embodiment.

FIG. 11 is a cross-sectional view showing a structure in which second and third resin layers are further formed in the semiconductor device of the first embodiment.

FIG. 12 is a sectional view for explaining the manufacturing method for the semiconductor device according to the second embodiment.

FIG. 13 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 14 is a sectional view for explaining the manufacturing method for the semiconductor device according to the second embodiment.

FIG. 15 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

FIG. 16 is a sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment.

FIG. 17 is a drawing for explaining the manufacturing method of the semiconductor device of the third embodiment.

FIG. 18 is a sectional view showing the structure of the semiconductor device of the fourth embodiment.

FIG. 19 is a cross-sectional view showing a structure in which a second resin layer is further formed in the semiconductor device of the fourth embodiment.

FIG. 20 is a cross-sectional view showing a structure in which second and third resin layers are further formed in the semiconductor device of the fourth embodiment.

FIG. 21 is a sectional view showing the structure of the semiconductor device of the fifth embodiment.

FIG. 22 is a cross-sectional view showing a structure in which a second resin layer is further formed on the semiconductor device of the fifth embodiment.

FIG. 23 is a cross-sectional view showing a structure in which second and third resin layers are further formed in the semiconductor device of the fifth embodiment.

FIG. 24 is a sectional view for explaining the manufacturing method for the semiconductor device according to the sixth embodiment.

FIG. 25 is a sectional view showing the structure of the semiconductor device obtained in the sixth embodiment.

FIG. 26 is a sectional view for explaining the manufacturing method for the semiconductor device according to the seventh embodiment.

FIG. 27 is a sectional view for explaining the manufacturing method for the semiconductor device according to the seventh embodiment.

FIG. 28 is a cross-sectional view showing the structure of the semiconductor device obtained in the seventh embodiment.

FIG. 29 is a sectional view for explaining the manufacturing method for the semiconductor device according to the eighth embodiment.

FIG. 30 is a cross-sectional view showing the structure of the semiconductor device obtained in the eighth embodiment.

FIG. 31 is a sectional view for explaining the manufacturing method for the semiconductor device according to the ninth embodiment.

FIG. 32 is a sectional view for explaining the manufacturing method for the semiconductor device according to the ninth embodiment.

FIG. 33 is an enlarged cross-sectional view showing the structure of the semiconductor device obtained in the ninth embodiment.

FIG. 34 is a sectional view for explaining the manufacturing method for the semiconductor device according to the tenth embodiment.

FIG. 35 is a sectional view showing the structure of the semiconductor device obtained in the tenth embodiment.

FIG. 36 is a sectional view showing the structure of a semiconductor device according to an eleventh embodiment.

FIG. 37 is a sectional view showing the structure of a semiconductor device according to a twelfth embodiment.

FIG. 38 is a sectional view showing the structure of the semiconductor device of the thirteenth embodiment.

FIG. 39 is a sectional view showing the structure of the semiconductor device of the fourteenth embodiment.

FIG. 40 is a sectional view showing the structure of the semiconductor device according to the fifteenth embodiment.

FIG. 41 is a sectional view showing the structure of the semiconductor device according to the sixteenth embodiment.

[Explanation of symbols]

1 ... Wiring substrate, 2 ... Wiring pad, 3 ... Semiconductor chip, 4 ... Electrode pad, 5 ... Solder bump, 6 ... First resin layer, 14 ... Flux Component-containing resin, 16 ... Squeegee, 17 ... Second resin layer, 18 ... Third resin layer, 19 ... Gold bump, 2
3 ... Sn-Ag solder layer, 24 ... Mounting substrate,
25 ……… Tape BGA package, 26 ……… TAB
Tape, 27 ... LSI chip, 30 ... Solder ball, 33 ... Screen mask, 34 ... Transfer pin, 36 ... Lead frame, 37 ... Semiconductor package having lead frame, 38 ... ...... Low melting point metal layer, 39 ...... Gold wire, 41 ...... Semiconductor chip or semiconductor package

Claims (18)

[Claims]
1. A wiring board having a wiring layer formed on at least one main surface of an insulating substrate, a semiconductor element mounted facedown on the wiring layer formation surface of the wiring board, and electrode terminals of the semiconductor element. A metal bump formed above, the electrode terminal of the semiconductor element and the wiring layer of the wiring board are bonded via the metal bump, and between the metal bump and the wiring board A semiconductor device having a fillet of a first resin layer formed thereon.
2. The metal bump is made of Au, Ag, Cu,
Ni, Fe, Pd, Sn, Pb, Bi, Zn, In, S
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises a metal selected from b, Ge alone, or a mixture or compound thereof.
3. The semiconductor device according to claim 1, further comprising a sealing layer made of a second resin between the semiconductor element and the wiring board.
4. The semiconductor device according to claim 1, further comprising a fillet of a resin layer formed between the metal bump and the semiconductor element.
5. A fillet of the first resin layer is formed at a joint portion of some of the metal bumps among a plurality of metal bumps for joining the electrode terminals of the semiconductor element and the wiring layer of the wiring board. The semiconductor device according to claim 3, wherein a sealing layer made of the second resin is formed around the bonding portion of the other metal bumps.
6. The fillets of the first resin layer formed at the joints of the plurality of adjacent metal bumps are connected to each other. Item of semiconductor device
7. A mounting substrate in which a wiring layer is formed on at least one main surface of an insulating substrate, a semiconductor package mounted on the wiring layer formation surface of the mounting substrate, the semiconductor package and the mounting substrate. A semiconductor device comprising: a metal bump for connecting to a wiring layer of a substrate; and a fillet of a first resin layer formed between the metal bump and the mounting substrate.
8. The metal bumps are Au, Ag, Cu,
Ni, Fe, Pd, Sn, Pb, Bi, Zn, In, S
8. The semiconductor device according to claim 7, wherein the semiconductor device comprises a metal selected from b, Ge alone, or a mixture or compound thereof.
9. The semiconductor device according to claim 7, further comprising a fillet of a resin layer formed between the metal bump and the semiconductor package.
10. A mounting substrate in which a wiring layer is formed on at least one main surface of an insulating substrate, a semiconductor package having a lead frame mounted on the wiring layer formation surface of the mounting substrate, and the semiconductor package. Of the lead frame and the wiring layer of the mounting substrate, and a fillet of the first resin layer is formed between the low melting point metal layer and the mounting substrate. A semiconductor device characterized by the above.
11. The semiconductor device according to claim 7, further comprising a sealing layer made of a second resin between the semiconductor package and the mounting substrate.
12. A method of manufacturing a semiconductor device in which a semiconductor element is mounted on a substrate via a metal bonding member, wherein a resin layer containing a flux component is interposed while interposing the metal bonding member formed around the resin layer. A step of aligning the substrate and the semiconductor element, and a step of curing the resin layer containing the flux component to form a fillet of the resin layer between the metal bonding member and the substrate. A method for manufacturing a characteristic semiconductor device.
13. A step of forming a layer made of a first resin containing a flux component on the outer circumference of a metal bump provided on an electrode terminal of a semiconductor element or on a wiring pad of a wiring board, and the semiconductor element A step of arranging the metal bumps and the wiring pads of the wiring board face down on the wiring pad formation surface of the wiring board, and heating the aligned metal bumps and the wiring pads. And a step of bonding the first resin layer containing the flux component to form a fillet of the first resin layer between the metal bump and the wiring board. And a method for manufacturing a semiconductor device.
14. The method according to claim 1, further comprising the step of forming a second resin layer between the wiring board and the semiconductor element and then curing the second resin layer.
3. The method for manufacturing a semiconductor device according to 3.
15. The manufacturing of a semiconductor device according to claim 14, wherein the formation of the second resin layer is performed subsequent to the step of forming the layer made of the first resin containing the flux component. Method.
16. A step of forming a layer made of a first resin containing a flux component on the outer periphery of a metal bump provided on an external terminal of a semiconductor package or on a wiring pad of a mounting substrate, and the semiconductor package. Is placed on the wiring pad formation surface of the mounting substrate, and the metal bump and the wiring pad of the mounting substrate are aligned, and the aligned metal bump and the wiring pad are heated. Forming a fillet of the first resin layer between the metal bump and the mounting substrate by curing the first resin layer containing the flux component. A method for manufacturing a characteristic semiconductor device.
17. A step of forming a low melting point metal layer on a wiring pad of a mounting substrate, a step of forming a layer made of a first resin containing a flux component on the low melting point metal layer, and a lead frame. Mounting the semiconductor package having on the wiring pad formation surface of the mounting substrate, aligning the lead frame and the wiring pad of the mounting substrate, and the aligned lead frame and wiring pad And a step of heating and joining, wherein by curing the first resin layer containing the flux component, a fillet of the first resin layer is provided between the low melting point metal layer and the mounting substrate. A method of manufacturing a semiconductor device, comprising:
18. The method according to claim 16, further comprising the step of forming a second resin layer between the mounting substrate and the semiconductor package and then curing the second resin layer. 17. The method for manufacturing a semiconductor device according to item 17.
JP2001298253A 2001-09-27 2001-09-27 Semiconductor device and manufacturing method thereof Active JP3836349B2 (en)

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KR100919632B1 (en) * 2007-10-16 2009-09-30 삼성전기주식회사 Package Substrate and the Manufacturing Method Thereof
US8814029B2 (en) 2011-08-11 2014-08-26 Sanyo Electric Co., Ltd. Metal bonding method and metal bonded structure
CN104081520A (en) * 2012-01-06 2014-10-01 美光科技公司 Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
US8939348B2 (en) 2011-02-28 2015-01-27 Sanyo Electric Co., Ltd. Metal bonded structure and metal bonding method
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Publication number Priority date Publication date Assignee Title
JP2006156996A (en) * 2004-11-04 2006-06-15 Ngk Spark Plug Co Ltd Wiring board with semiconductor component
JP4667208B2 (en) * 2004-11-04 2011-04-06 日本特殊陶業株式会社 Wiring board with semiconductor parts
KR100919632B1 (en) * 2007-10-16 2009-09-30 삼성전기주식회사 Package Substrate and the Manufacturing Method Thereof
US8939348B2 (en) 2011-02-28 2015-01-27 Sanyo Electric Co., Ltd. Metal bonded structure and metal bonding method
US8814029B2 (en) 2011-08-11 2014-08-26 Sanyo Electric Co., Ltd. Metal bonding method and metal bonded structure
CN104081520A (en) * 2012-01-06 2014-10-01 美光科技公司 Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
JP2015507359A (en) * 2012-01-06 2015-03-05 マイクロン テクノロジー, インク. Integrated circuit structure having through substrate via and method of forming integrated circuit structure having through substrate via
US9536855B2 (en) 2013-07-10 2017-01-03 Mitsubishi Electric Corporation Semiconductor device and method of fabricating same
US10546796B2 (en) 2016-02-18 2020-01-28 Apple Inc. Backplane structure and process for microdriver and micro LED

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