KR100919632B1 - Package Substrate and the Manufacturing Method Thereof - Google Patents

Abstract

A package substrate and a method of manufacturing the same are disclosed. A package substrate including an insulating material, a conductive bump penetrating through the insulating material, and a circuit pattern recessed in the conductive bump forms a fine circuit by reducing the via pitch, the circuit pattern pitch, and the wire bonding pad pitch, thereby increasing the density of the circuit pattern and the package substrate. It can be miniaturized, and the circuit pattern is formed by being recessed in the bumps, thereby improving the flatness of the surface of the solder resist, thereby improving the reliability of adhesion between the die bonding tape and the substrate.

Description

Package Substrate and the Manufacturing Method Thereof}

The present invention relates to a package substrate and a method of manufacturing the same.

Conventionally, after forming a via hole in an insulating layer using a drill bit or a laser for electrical connection between metal layers of a semiconductor package substrate. The method of conducting metal layer conduction by copper plating via-holes was used. In the case of using the interlayer conduction method, a via hole land is required for reliable electrical connection between the circuit pattern and the via hole in the circuit forming process.

On the other hand, as a method for improving circuit density for miniaturization of packaged products, researches for reducing the width of the circuit pattern and the size of the via hole land have been continued. The size of the via hole land is determined by the size of the via hole and the circuit exposure matching capability between the via hole and the via hole land. Therefore, most waste substrate manufacturers are researching technologies for reducing the size of via holes and increasing the matching force between via holes and via hole lands. In order to reduce the size of the via holes and increase the matching force, investment in high precision drill facilities and exposure machines must be made. However, the investment of such expensive production equipment has the problem of raising the manufacturing cost and lowering the productivity.

In addition, there is a tendency to form a thin copper thickness of the surface of the copper foil resin layer in order to form a fine circuit, but there is a limit to lower the copper thickness of the surface in the prior art of copper plating the via hole and the copper foil resin layer at the same time.

In addition, as the number of stacks of dies increases when assembling a package, an adhesive material applied on a solder resist of a substrate for die bonding is changing from a paste to a tape type. However, there is a problem that the adhesion reliability between the substrate and the tape is degraded due to the flatness of the solder resist of the substrate.

Therefore, the present invention minimizes via pitch with the same circuit exposure matching force to the same via size as before, forms a fine circuit pattern by a semi-additive method, and improves the flatness of solder resist, thereby improving package reliability. We have developed a technology to improve the

According to the present invention, in the method of forming a via of a package substrate, by using an interlayer connection structure through bumps, a circuit pattern and a via landless connection method are adopted to reduce via pitch, circuit pitch, and wire bonding pad pitch, thereby reducing fine circuits. The present invention provides a package substrate on which a pattern can be formed and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a package substrate including an insulating material, a conductive bump penetrating the insulating material, and a circuit pattern recessed in the conductive bump.

In addition, the wire bonding pads and the solder ball pads formed by nickel (Ni) or gold (Au) plating are formed on a circuit pattern that needs to be connected to an external terminal, and solder is formed on one or both sides of an insulating material accommodating conductive bumps and circuit patterns. A resist is formed.

Here, the insulating material is a core layer penetrated by the conductive bumps during the press operation process, and is made of a resin-based or epoxy-based insulating material that can prevent an unintended short circuit between bumps or circuit patterns in a completed package substrate state. Is formed.

The conductive bumps may be formed by a conductive material such as silver (Ag) or copper (Cu) as a passage that serves as an interlayer conduction of circuit patterns formed on upper and lower layers of the substrate. The bumps have a columnar shape through which the upper and lower circuit patterns are electrically connected to each other by contacting the upper and lower circuit patterns.

Meanwhile, in the present invention, the circuit pattern is formed on the top, bottom, or both the top and the bottom of the conductive bump, and the connection between the circuit pattern of the upper and lower substrates is made by the bump, which is an interlayer conduction passage, and the circuit is recessed in the bump. The width of the pattern is characterized by being smaller than the diameter of the bumps. Therefore, the interlayer connection is possible with an area smaller than the area of the substrate required for forming the vias and via lands in the conventional package substrate.

On the other hand, according to another aspect of the invention, providing a first carrier, forming a first seed layer on one surface of the first carrier, forming a first circuit pattern on the first seed layer, the first circuit A method of manufacturing a package substrate comprising printing a conductive bump over a pattern, and laminating an insulating material to a first substrate formed through the step so that the conductive bump penetrates the insulating material.

The stacking of the insulating material on the first substrate may be performed by pressing the insulating material so that the bump penetrates the insulating material.

Here, a method of manufacturing a package substrate is further provided, in which a step of stacking a second substrate having a second circuit pattern formed on a second carrier and a second seed layer on an insulating material so that the second circuit pattern faces the conductive bumps is provided.

In addition, there is provided a method of manufacturing a package substrate further comprising the step of removing the first and second carriers and the first and second seed layers formed on the outer side of the laminated substrate.

After removing the carrier and seed layer described above, a wire bonding pad or solder ball pad is formed on the circuit pattern through nickel (Ni) or gold (Au) plating, and one surface of the insulating material accommodating the conductive bumps and the circuit pattern or Disclosed is a method of manufacturing a package substrate further comprising forming solder resists on both surfaces.

The seed layer formed on the carriers of the first and second substrates described above may be formed through a nickel (Ni) or chromium (Cr) plating process.

Here, the step of forming the circuit pattern is performed by the additive technique, the step of applying a photosensitive material on the nickel plating layer, the step of adhering the artwork film printed circuit pattern on the photosensitive material, the artwork film Transferring the shape of the circuit pattern to the photosensitive material by exposing to ultraviolet light, developing the plating resist by removing the photosensitive material which is not cured by ultraviolet light through a developing solution, forming a circuit pattern through electrolytic copper plating, Removing the plating resist.

As described above, the bump may be made of a conductive material such as silver (Ag) or copper (Cu). The printing of the conductive bumps on the plating layer may be performed through a screen printing method of supplying a conductive paste to a location of a circuit pattern requiring interlayer conduction using a metal mask.

On the other hand, the step of removing the carrier and seed layer formed on the outer side of the laminated substrate by etching the carrier formed on the outer surface of the laminated substrate using the etching solution, the seed formed on the outer side of the laminated substrate from which the carrier is removed This may be done by etching the layer.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

As described above, according to the exemplary embodiment of the present invention, by reducing the via pitch, the circuit pitch, and the wire bonding pad pitch, a microcircuit may be formed to increase the compactness of the circuit pattern and miniaturize the package substrate. By being recessed, the flatness of the surface of the solder resist can be improved, thereby improving the reliability of adhesion between the die bonding tape and the substrate.

1 is a cross-sectional view showing a package substrate according to the prior art.

2 is a flow chart showing a method for manufacturing a package substrate according to an embodiment of the present invention.

3 to 12 are flowcharts illustrating a manufacturing process of a package substrate according to an embodiment of the present invention.

13 is a sectional view showing a package substrate according to an embodiment of the present invention.

14 is a three-dimensional view comparing the via and the circuit pattern according to an embodiment of the present invention and the prior art.

15 is a plan view comparing a via and a circuit pattern according to an embodiment of the present invention with the prior art.

FIG. 16 is a cross-sectional view taken along line AA ′ and line B-B ′ of FIG. 15.

17 is a plan view comparing the via pitch according to the prior art and the embodiment of the present invention.

18 is a cross-sectional view comparing a circuit pitch according to an embodiment of the present invention with the prior art.

19 is a cross-sectional view comparing the wire bonding pad pitch according to an embodiment of the present invention with the prior art.

20 and 21 are cross-sectional views comparing the surface flatness of the solder paste on the pattern according to the prior art and the embodiment of the present invention.

22 and 23 are cross-sectional views comparing surface flatness of solder paste on vias in accordance with one embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2: via hole 4: via land

5: copper foil 6: circuit pattern

8: insulation material 10: first carrier

12: first seed layer 14: first circuit pattern

16: conductive bump 18: insulating material

19: first substrate 20: second substrate

21: second carrier 22: second seed layer

24: second circuit pattern 30: laminated substrate

40: package substrate 42: solder resist

44: wire bonding pad 46: circuit pattern

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, an embodiment of a package substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate explanations will be omitted.

1 is a cross-sectional view showing a package substrate according to the prior art. Referring to FIG. 1, a via hole 2, a via land 4, a circuit pattern 6, an insulating material 8, a solder resist 42, and a wire bonding pad 44 are illustrated. Conventionally, a copper clad laminate is put in and a through hole is formed using a drill bit or a laser, and then electroless copper plating and electrolytic copper plating are sequentially performed for electrical connection between the upper and lower metal layers. The manufacturing of the package substrate shown in FIG. 1 is completed by forming the circuit pattern 6 and the via land 4 thereon and applying the solder resist 42 to the portion except the connection portion with the external terminal. That is, as shown in FIG. 1, the via package 4 is required for the electrical connection between the circuit pattern 6 and the via hole 2, which is an interlayer connecting passage.

2 is a flowchart illustrating a method of manufacturing a package substrate according to an embodiment of the present invention, and FIGS. 3 to 12 are flowcharts illustrating a manufacturing process of a package substrate according to an embodiment of the present invention. 3 to 12, the first carrier 10, the first seed layer 12, the first circuit pattern 14, the conductive bumps 16, the insulating material 18, the first substrate 19, The second substrate 20, the second carrier 21, the second seed layer 22, the second circuit pattern 24, the laminated substrate 30, the package substrate 40, and the solder resist 42 are shown. have. Hereinafter, a description will be given according to the flow of the manufacturing process illustrated in FIGS. 3 to 12.

The first carrier 10 is introduced and the first seed layer 12 is formed on the surface of the first carrier 10. The first seed layer 12 is a plating layer formed on the surface of the first carrier 10 by nickel (Ni) or chromium (Cr) plating. Next, as shown in FIG. 5, the first circuit pattern 14 is formed on the first seed layer 12 described above.

The process of forming the first circuit pattern 14 may be formed by an additive technology. For example, a photosensitive material is applied onto the first seed layer 12, and the artwork film on which the circuit pattern is printed is brought into close contact with the photosensitive material, and then the artwork film is exposed to ultraviolet rays. Thereafter, the plating resist is developed through a developer. The photosensitive material selectively exposed to ultraviolet rays by the artwork film partially forms a plating resist and part is removed by a developer. Next, a circuit pattern is formed through electroplating, and after the plating process, the plating resist is removed on the first seed layer 12 formed on the first carrier 10 as shown in FIG. The circuit pattern 14 is printed.

As such, after providing the first substrate 19 on which the first circuit pattern 14 is printed on the first carrier 10 and the first seed layer 12 (S100), the interlayer conduction role illustrated in FIG. 6 is provided. A conductive bump 16 is formed (S200). The bump 16 may be made of a conductive material such as silver (Ag) or copper (Cu). The bump 16 serves to connect the upper and lower circuit patterns, and has a columnar shape in contact with both the upper and lower circuit patterns. In addition, the process of printing the bumps 16 may be performed by a screen printing process of supplying a conductive paste on the circuit pattern 14 using a metal mask.

As described above, after the bumps 16 are formed on the first circuit pattern 14 (S200), an insulating material is placed on the bumps 16 and compressed, so that the bumps 16 are insulated from the insulating material 18 as shown in FIG. 7. ) To pass through (S300). This is for interlayer conduction of circuit patterns formed on both surfaces of the insulating material 18 through the bumps 16 penetrating the insulating material 18. Through this press process, the bump 16 is exposed to the top of the insulating material 18 as shown in FIG.

Next, referring to FIG. 8, the bump 16 penetrating the insulating material of FIG. 7 through the second substrate 20 having the second circuit pattern 24 formed on the second carrier 21 and the second seed layer 22. The second circuit pattern 24 is placed so as to face the conductive bumps 16. In this case, the second circuit pattern 24 formed on the second substrate 20 is formed to be connected to the bump 16 at a portion requiring electrical connection, and the first circuit pattern 14 of the lower layer is formed through a pressing process to be described later. It is conducting.

Next, the laminated substrate 30 illustrated in FIG. 9 may be formed by pressing the second substrate 20 stacked above (S400). This pressing process can be carried out smoothly at a temperature of at least 200 ℃ and a pressure of 30kgf / ㎠ or more. As a result, the circuit patterns 14 and 24 formed on the upper and lower layers are electrically connected by the bumps 16.

Next, the first carrier 10 and the second carrier 21 formed on the outermost side of the laminated substrate 30 are removed. A cross section of the laminated substrate 30 from which the outer first carrier 10 and second carrier 21 are removed is shown in FIG. 10. 11, the first seed layer 12 and the second seed layer 22 formed on the outer side of the laminated substrate 30 from which the first carrier 10 and the second carrier 21 are removed are removed. The formed substrate can be formed. Removing the carrier and seed layer (S500) may be performed through a wet etching method. Referring to FIG. 11, the circuit patterns 14 and 24 are recessed in the bumps 16, and the upper and lower circuit patterns 14 and 24 are connected by the conductive bumps 16. The width of the circuit patterns 14 and 24 recessed in the bump 16 is smaller than the diameter of the bump 16. Accordingly, it is not necessary to form a via land surrounding the via for connecting the via hole and the circuit pattern in the conventional package substrate. The area on the substrate required for connecting the circuit patterns 14 and 24 and the via holes is reduced as compared with the prior art.

Meanwhile, in the substrate shown in FIG. 11, both the conductive bumps 16 and the circuit patterns 14 and 24 are exposed to the outside. When mounting a semiconductor chip or component in the future, a wire bonding pad or solder ball on the circuit patterns 14 and 24 through a nickel (Au) or gold (Au) plating process in order to prevent a circuit error by a bridge of the conductor. The circuit patterns 14 and 24, which form pads and do not need to be connected to external terminals, may be coated with the solder resist 42 (S600). Referring to FIG. 12, there is shown a cross section of a package substrate 40 coated with a solder resist 42 on the substrate of FIG. 11.

13 is a cross-sectional view showing a package substrate according to an embodiment of the present invention. Referring to FIG. 13, a circuit pattern 46, a bump 16, an insulating material 18, a solder resist 42, and a wire bonding pad 44 are illustrated. The wire bonding pad 44 or the solder ball pad is formed in the circuit pattern 46 of the portion for connection with the external terminal, and the solder resist 42 is coated on the remaining circuit pattern 46. The circuit pattern 46 may be recessed in the insulating material, the bump 16 or both the insulating material and the bump 16, unlike the circuit pattern of the conventional package substrate. Since the circuit pattern 46 is directly recessed and electrically connected to the bumps 16, the via land, which has been formed to ensure electrical connection in the prior art, is not necessary. That is, by forming the circuit pattern 46 and the bump 16 in accordance with an embodiment of the present invention to manufacture a package substrate 40 for directly connecting the bump 16 and the circuit pattern 46 through the via land. Can be. Therefore, interlayer conduction is possible only by the required area of the bump 16 without the required area on the substrate of the via land formed around the via and formed during the circuit pattern.

14 is a three-dimensional view comparing the via and the circuit pattern according to the prior art and the embodiment of the present invention. Referring to FIG. 14, via holes 2, via lands 4, circuit patterns 6 and 46, bumps 16, and wire bonding pads 44 are illustrated. In the interlayer conduction method according to the prior art, a via hole 2 and a via land 4 surrounding the via hole are required. Therefore, in order to connect the via hole 2 and the circuit pattern 6, the area of the via land 4 larger than the area of the via hole must be secured on the substrate. On the other hand, in the interlayer conduction method according to an exemplary embodiment of the present invention, the circuit pattern 46 is recessed and directly connected to the bump 16, thereby eliminating the need for the via land 4. Therefore, the circuit pattern 46 and the bump 16 may be electrically connected to each other only by the area of the bump 16 on the substrate. Referring to FIG. 14, a diameter C of a bump 16 according to an embodiment of the present invention and a diameter C ′ of a via land according to the prior art are shown. When using the same sized via and circuit pattern for interlayer conduction, it can be seen that the diameter C of the bump 16 is smaller than the diameter C 'of the via land 4. Through the interlayer conduction method according to an embodiment of the present invention, a via substrate, a circuit pitch, and a wire bonding pad pitch may be reduced compared to the prior art. Therefore, it is possible to form a finer circuit pattern on the substrate of the same area.

15 is a plan view comparing a via and a circuit pattern according to an exemplary embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line A-A 'and line B-B' of FIG. 15. Referring to FIG. 15, the via hole 2, the via land 4, the circuit pattern 46, the bump 16, the wire bonding pad 44, the diameter D of the bumps, and the diameter D ′ of the via lands are illustrated. Referring also to FIG. 16, the diameter E of the bump 16 and the diameter E 'of the via land 4 are shown. When using the same sized vias and circuit patterns for interlayer conduction, it can be seen that the diameters D and E of the bumps 16 are smaller than the diameters D 'and E' of the via lands 4, respectively.

17 is a plan view comparing the via pitch according to the prior art and the embodiment of the present invention. Referring to FIG. 17, via holes 2, via lands 4, circuit patterns 46, bumps 16, via pitches F and F ′ are shown. When using the same sized vias and circuit patterns for interlayer conduction, it can be seen that via pitch F according to one embodiment of the present invention is smaller than via pitch F 'according to the prior art. That is, in the prior art, the via land 4 is formed by expanding 50 μm to 100 μm or more on one side in consideration of the degree of matching during the exposure of the circuit. Can be greatly reduced.

18 is a cross-sectional view comparing a circuit pitch according to an embodiment of the present invention with the prior art. Referring to FIG. 18, a copper foil 10, a circuit pattern 46, an insulating material 18, and circuit pitches G and G ′ are shown. When forming the circuit pattern of the same size, it can be seen that the circuit pitch G according to an embodiment of the present invention is smaller than the G 'of the prior art. One embodiment of the present invention forms a circuit pattern 48 in a form in which a circuit is embedded in an insulating material by applying a thin electroless copper plating on a surface, plating a circuit pattern thereon, and etching the electroless copper plating layer. Therefore, by copper plating on the copper foil, a circuit pitch of about 20 μm or more can be made smaller than in the conventional art of forming a circuit pattern.

19 is a cross-sectional view comparing the wire bonding pad pitch according to an embodiment of the present invention with the prior art. Referring to FIG. 19, the wire bonding pads 44 and the wire bonding pad pitches H and H ′ are formed on the circuit pattern 46 of FIG. 18 by nickel or gold plating. When forming the circuit pattern of the same size, it can be seen that the wire bonding pad pitch H according to an embodiment of the present invention is smaller than the prior art H '. In an embodiment of the present invention, since the circuit pattern 46 is buried in the insulating material 18 and the pad is formed on the insulating material 18, the wire bonding pad pitch may be smaller than about 30 μm than in the related art.

20 and 21 are cross-sectional views comparing surface flatness of a solder paste on a pattern according to the prior art and the embodiment of the present invention, and FIGS. 22 and 23 are vias according to the prior art and the embodiment of the present invention. This is a cross-sectional view comparing the surface flatness of the solder paste. 20 to 23, the solder paste 42, the insulating materials 8 and 18, the circuit patterns 46, the via holes, the bumps 16, and the via lands 4 are illustrated. As shown in FIG. 20 and FIG. 22, according to the circuit pattern and the via formation method of the prior art, the surface of the solder paste 42 has a step of up to 10 μm on the circuit pattern 6 and up to 15 μm on the via. This prior art has a trap between the tape and the solder resist 42 due to the height difference of the solder resist 42 when the die bonding tape is adhered to the substrate during the package assembly process. This reduces the reliability of the package. On the other hand, as shown in Figure 21 and 23, according to an embodiment of the present invention, since the circuit pattern 46 is recessed in the insulating material 18 and the via is filled with a conductive paste penetrates the insulating material 18 Since there is little height step after application of the solder paste 42, the reliability of the package is improved as compared with the prior art.

In other words, according to one embodiment of the present invention, the package substrate 40 without the formation of the via land 4 may be manufactured according to the flow of the manufacturing process illustrated in FIGS. 3 to 12. Also provided is a package substrate 40 shown in FIG. 13 in accordance with one embodiment of the present invention. Meanwhile, as shown in FIGS. 14 to 23, an embodiment of the present invention reduces via pitch, circuit pitch, wire bonding pad 44 pitch, and improves the flatness of the surface of the solder paste 42 as compared with the related art. Can be improved. That is, according to an embodiment of the present invention, the compactness of the circuit pattern 46 may be improved by miniaturizing the package substrate 40 by the above-described effects, and the reliability of close contact between the die bonding tape and the package substrate 40 may be improved. Can be improved.

Many embodiments other than the above-described embodiment exist within the claims of the present invention, the shape of the bump according to an embodiment of the present invention may be a variety of shapes that can connect the upper and lower circuit patterns as well as the cylinder. have. That is, the spirit and scope of the present invention are not limited to the circular vias shown in the embodiment of the present invention.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (14)

Insulation material; A conductive bump penetrating the insulating material; And A package substrate comprising a circuit pattern recessed in the conductive bumps. The method of claim 1, The circuit pattern is a package substrate, characterized in that the recessed on the top and bottom of the conductive bump. The method of claim 1, The package substrate further comprises a solder resist formed on one surface or both surfaces of the insulating material for receiving the conductive bumps and the circuit pattern. The method of claim 1, The conductive bump is a package substrate, characterized in that made of a material containing silver (Ag) or copper (Cu). The method of claim 1, The width of the circuit pattern recessed in the bump is a package substrate, characterized in that less than the diameter of the bump. Providing a first substrate having a first circuit pattern formed on the first carrier and the first seed layer; Printing a conductive bump to bury the first circuit pattern; Stacking the insulating material on the first substrate such that the conductive bumps penetrate the insulating material. The method of claim 6, And stacking a second substrate having a second circuit pattern on the second carrier and the second seed layer on the insulating material such that the second circuit pattern is recessed in the conductive bumps. The method of claim 6, Removing the first carrier and the first seed layer. The method of claim 8, After removing the first carrier and the first seed layer, And forming a solder resist on one or both surfaces of the insulating material accommodating the conductive bumps and the first circuit pattern. The method of claim 6, The first seed layer is a package substrate manufacturing method, characterized in that made of a material containing nickel (Ni) or chromium (Cr). The method of claim 6, Forming the first circuit pattern on the first carrier and the first seed layer, Package substrate manufacturing method characterized in that performed by electroplating. The method of claim 6, The conductive bump is a package substrate manufacturing method, characterized in that made of a material containing silver (Ag) or copper (Cu). The method of claim 6, The printing of the conductive bumps may include: Package substrate manufacturing method characterized in that it is carried out through the screen printing method. The method of claim 8, Removing the first carrier and the first seed layer, Package substrate manufacturing method characterized in that it is carried out through a wet etching method.