JP7283027B2 - printed circuit board - Google Patents

Description

The present invention relates to printed circuit boards.

Advances in the computer industry have led to the development of technology for integrated circuits (dies) that can be produced at lower costs while still having high performance. Accordingly, technologies related to package substrates containing a large number of dies have also been developed.

U.S. Pat. No. 8,754,514

According to one aspect of the present invention, there is provided a printed circuit board including a plurality of element mounting portions, wherein a first laminate including a plurality of insulating layers and a first circuit; A second laminate including a cavity open to the upper surface of one laminate and a plurality of resin layers laminated in the cavity and a second circuit, wherein the first circuit is exposed by the cavity. The second laminate includes connection vias that penetrate through the resin layer positioned at the bottom layer and are in contact with the connection pads, and the second circuit is electrically connected to the plurality of element mounting portions. A printed circuit board is provided.

The part of the second circuit can electrically connect the plurality of element mounting parts to each other, and the part of the second circuit electrically connects any one of the element mounting parts and the connection via. can be directly connected.

The resin layer may contain a photosensitive resin, and the thickness of the resin layer may be smaller than the thickness of the insulating layer.

The circuit width of the first circuit can be greater than the circuit width of the second circuit.

The first circuit located on the top layer of the first stack may be embedded in an upper surface of the insulating layer located on the top layer, and the first circuit located on the top layer of the first stack may include: , may protrude from the insulating layer located at the uppermost layer.

The top surface of the second stack may be positioned below the top surface of the first stack.

A second resin layer formed on the top surface of the first laminate and the top surface of the second laminate may be further included. A via hole is formed in the uppermost insulating layer, a via is formed in the via hole, and the via hole is filled so that the second resin layer surrounds the via. .

A solder resist layer laminated on the second resin layer may be further included. The device may further include a third circuit formed on the second resin layer and electrically connected to the second circuit.

A solder resist layer laminated on the first laminate and the second laminate may be further included. A metal post may be further included to provide the device mounting portion penetrating the solder resist layer. The metal posts may include post vias penetrating the solder-resist layer, and post pads protruding from the solder-resist layer and formed on the post vias.

1 is a diagram showing a printed circuit board according to a first embodiment of the present invention; FIG. 1 illustrates a package including a printed circuit board according to a first embodiment of the present invention; FIG. FIG. 4 is a diagram showing a printed circuit board according to a second embodiment of the present invention; FIG. 4 is a diagram showing a printed circuit board according to a third embodiment of the present invention; FIG. 4 is a diagram showing a printed circuit board according to a fourth embodiment of the present invention; FIG. 5 is a diagram showing a printed circuit board according to a fifth embodiment of the present invention; FIG. 5 is a diagram showing a package including a printed circuit board according to a fifth embodiment of the invention; FIG. 6 is a diagram showing a printed circuit board according to a sixth embodiment of the present invention; FIG. 10 is a diagram showing a printed circuit board according to a seventh embodiment of the present invention; It is a figure which shows the manufacturing method of the package based on one Example of this invention. It is a figure which shows the manufacturing method of the package based on one Example of this invention. FIG. 5 is a diagram showing a method of manufacturing a package according to another embodiment of the present invention; FIG. 5 is a diagram showing a method of manufacturing a package according to another embodiment of the present invention;

Exemplary embodiments of printed circuit boards in accordance with the present invention will now be described in detail with reference to the accompanying drawings, wherein like or corresponding components are identified by like reference numerals, Duplicate explanation is omitted.

In addition, terms such as "first" and "second" used below are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are the first, second, etc. is not limited by the term

In addition, in the contact relationship between each component, the term "bond" does not mean only the case where each component is in direct physical contact, but another configuration is interposed between each component, It is used as a concept that includes the case where each component is in contact with another configuration.

Various embodiments of the printed circuit board are described below separately, without excluding that the description of one embodiment is applicable to other embodiments. A description of one embodiment is also applicable to other embodiments, unless they are incompatible.

<Printed circuit board>
[First embodiment]
FIG. 1 is a diagram showing a printed circuit board according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a package including the printed circuit board according to the first embodiment of the present invention.

A printed circuit board according to an embodiment of the present invention may provide a plurality of device mounting portions so that a plurality of electronic devices can be mounted thereon. The device mounting part is an area where an electronic device is coupled, and may include a plurality of mounting pads. Here, the electronic device may be variously selected from active devices, passive devices, integrated circuits, etc., and may include chips, dies, and the like.

In the description of the printed circuit board according to the embodiment of the present invention, the description will be based on the printed circuit board having the first element mounting portion M1 and the second element mounting portion M2. do not rule out becoming

The first device mounting portion M1 and the second device mounting portion M2 are separated from each other, and each device mounting portion may include a plurality of different mounting pads. The first electronic element E1 is mounted on the first element mounting portion M1, and the second electronic element E2 is mounted on the second element mounting portion M2. can be selected from active devices, passive devices, integrated circuits, and the like. For example, the first electronic device E1 may be an HBM and the second electronic device E2 may be a GPU, but is not limited thereto.

Referring to FIG. 1, the printed circuit board according to the first embodiment of the present invention may include a first laminate 100, a cavity 120 and a second laminate 200. As shown in FIG.

The first stacked body 100 is formed by vertically stacking a plurality of insulating layers 110 . The insulating layer 110 is a layer formed of an organic or inorganic insulating material, and may include resin. Examples of the resin of the insulating layer 110 include thermosetting and thermoplastic resins, and specific examples include epoxy resin, imidazole resin, polyimide resin, BT (bismaleimide triazine) resin, and fluorine-based resin. It can include at least one of resins, but is not limited thereto.

The insulation layer 110 may include a fiber reinforcing material such as glass fiber therein, and the specific insulation layer 110 may be prepreg. Also, the insulating layer 110 can contain a filler such as an organic filler or an inorganic filler. Silica is an example of the inorganic filler contained in the insulating layer 110 .

A plurality of insulating layers 110 made of the same or different materials may be laminated layer by layer to form the first laminate 100 . Although two insulating layers 110 are shown in FIG. 1, the number of insulating layers 110 can be changed by design or the like.

A circuit can be formed on the first laminate 100, and the circuit formed on the first laminate 100 will be referred to as a first circuit C1. The first circuit C1 can be made of metal, and the metal of the first circuit C1 can include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The first circuit C1 may be formed on one surface of each insulating layer 110 . When there are two insulating layers 110, the first circuit C1 may be formed in three layers. The first circuits C1 located in different layers can be electrically connected through vias (first vias V1). Referring to FIG. 1, among the first circuits C1, the outermost first circuit C1′ located closest to the element mounting surface is embedded in the upper surface of the outermost insulating layer 110, and the outermost first circuit C1 ' can be covered with the outermost insulating layer 110 except for the top surface.

The first circuit C1 may include multiple circuit lines. A pad may be provided at the end of each circuit line. This pad can be connected to a via, such as the first via V1.

On the other hand, among the first circuits C1, the outermost first circuit C1' positioned closest to the device mounting surface may provide a device mounting portion including mounting pads for mounting an electronic device.

A cavity 120 may be formed in the first stack 100 . A cavity 120 is formed in the first stack 100 and opened upward. However, since the lower portion of the cavity 120 is not open, the cavity 120 penetrates only part of the thickness of the first laminate 100 . As shown in FIG. 1, the depth of the cavity 120 can correspond to the N thicknesses of the insulating layer 110 of the first stack 100 . Also, the bottom surface of the cavity 120 may be positioned at the interface between the two insulating layers 11 .

The cavity 120 allows a portion of the first circuit C1 to be exposed. A first circuit C1 located in the insulating layer 110 in contact with the cavity 120 among the plurality of insulating layers 110 can be exposed by the cavity 120, and the pads provided at the ends of the first circuit C1 are exposed. be able to. The pads of the first circuit C1 exposed by the cavity 120 can be called connection pads 300. FIG. In other words, the cavity 120 exposes the connection pads 300 of the first circuit C1, and the connection pads 300 are the pads of the first circuit C1 located below the cavity 120. As shown in FIG.

The second laminate 200 is formed in the cavity 120 and may be formed by vertically stacking a plurality of resin layers 210 . A plurality of resin layers 210 may be sequentially stacked within the cavity 120 0 .

The resin layer 210 includes resin, specifically, epoxy resin, imidazole resin, polyimide resin, liquid crystal polymer (LCP), BT (bismaleimide triazine) resin, and fluorine-based resin. At least one may be included, but is not limited to these.

The resin layer 210 may contain a photosensitive resin. In this case, the resin layer 210 may react to light and may be processed through a photolithography process.

The resin layer 210 containing photosensitive resin may be a PID (photo imageable dielectric). Also, the photosensitive resin may be of a positive type or a negative type.

In the case of the positive resin layer 210, the photopolymer bond of the portion exposed to light is broken during the exposure process. After that, when a developing process is performed, the part where the photopolymer polymer bond is cut by exposure to light is removed.

In the case of the negative type resin layer 210, the portion exposed to light in the exposure process undergoes a photopolymerization reaction and changes from a single structure to a chain structure three-dimensional network structure. is removed.

According to the resin layer 210 containing a photosensitive resin, a circuit and via formation process can be performed by a photolithography process, so fine pattern processing can be facilitated.

The thickness of the resin layer 210 can be smaller than the thickness of the insulating layer 110 . That is, the thickness of one of the plurality of resin layers 210 may be smaller than the thickness of one of the plurality of insulation layers 110 . Accordingly, when the depth of the cavity 120 is the same as the thickness of one insulating layer 110, a plurality of resin layers 210 may be formed in the cavity 120. FIG.

The top surface of the resin layer 210 , that is, the top surface of the second laminate 200 may be positioned on the same plane as the top surface of the first laminate 100 .

A circuit can be formed on the second laminate 200, and the circuit formed on the second laminate 200 will be referred to as a second circuit C2. The second circuit C2 can be made of metal, and the metal of the second circuit C2 can include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The second circuit C2 may be formed on one surface (upper surface) of each resin layer 210 . The outermost layer (uppermost layer) second circuit C2′ located closest to the element mounting surface is embedded in the outermost layer (uppermost layer) resin layer 210 and positioned closest to the element mounting surface. The top surface of C2' may be flush with the top surface of the outermost first circuit C1' located closest to the device mounting surface.

The second circuits C2 located in different layers can be connected to each other through vias (second vias V2). Meanwhile, connection vias 400 may be formed in the second laminate 200 to penetrate the lowermost resin layer 211 and contact the connection pads 300 . That is, the connection via 400 can electrically connect the connection pad 300 and the second circuit C2.

The present invention is characterized in that the resin layer 210 is directly formed in the cavity 120 of the first laminate 100 . That is, since the second laminate 200 is formed by sequentially stacking the plurality of resin layers 210 in the cavity 120 of the first laminate 100, the cavity 120 is formed after the second laminate 200 is separately manufactured. It is distinguished from the structure that is inserted into and attached to the first stack 100 .

Also, a connection via 400 is formed on the bottom surface of the cavity 120 to contact the connection pad 300 , and the connection via 400 may electrically connect the first stack 100 and the second stack 200 . This eliminates the need for soldering work for connecting the first laminate 100 and the second laminate 200 and the use of an adhesive.

The circuit width of the first circuit C1 can be greater than the circuit width of the second circuit C2. The circuit thickness of the first circuit C1 can be greater than the circuit thickness of the second circuit C2. The second circuit C2 may have a finer pitch than the first circuit C1. The circuit density of the second circuits C2 can be greater than the circuit density of the first circuits C1.

The first circuit C1 and the second circuit C2 may be formed by a substrate process such as a SAP process (semi-additive process), an M-SAP process (modified semi-additive process), or a tenting process. Here, the second circuit C2 may be formed by a SAP process, and the first circuit C1 may be formed by a tenting process or the like, but the invention is not limited thereto.

The size of the first vias V1 may be larger than the size of the second vias V2, and the pitch of the first vias V1 may be larger than the pitch of the second vias V2. Also, the connection via 400 may have the same size as the second via V2.

The second circuit C2 may include multiple circuit lines. A pad may be provided at the end of each circuit line. This pad can be connected to the second via V2. On the other hand, among the second circuits C2, the outermost second circuit C2' positioned closest to the device mounting surface can provide a device mounting part including mounting pads for mounting the electronic device.

Each of the plurality of element mounting portions is formed over both the first laminate 100 and the second laminate 200 . That is, the first element mounting portion M1 is provided on the first layered body 100 and the second layered body 200, and the second element mounting portion M2 is also provided on the first layered body 100 and the second layered body 200. FIG. The top surface of the second stack 200 can be divided into a plurality of sections to provide a plurality of device mounting portions.

Referring to FIG. 2A, the first electronic element E1 is mounted on the first element mounting portion M1, and the second electronic element E2 is mounted on the second element mounting portion M2.

The first electronic element E1 is positioned across both the first laminate 100 and the second laminate 200, and the second electronic element E2 is also positioned across both the first laminate 100 and the second laminate 200. FIG.

The first electronic element E1 includes an electrode terminal T1, and the electrode terminal T1 can be coupled to a mounting pad of the first element mounting portion M1 of the printed circuit board by a low melting point metal member LM. An underfill material F may be filled between the first electronic element E1 and the printed circuit board.

The second electronic element E2 includes an electrode terminal T2, and the electrode terminal T2 can be coupled to a mounting pad of the second element mounting portion M2 of the printed circuit board by a low melting point metal member LM. An underfill material F may be filled between the second electronic element E2 and the printed circuit board.

As noted above, the second circuit C2 may include multiple circuit lines. The second circuit C2 may include circuit lines electrically connecting to the connecting vias 400 . Also, the second circuit C2 may include circuit lines that are electrically insulated from the connection vias 400 and electrically connect the plurality of element mounting portions. In this case, the second circuit C2 can provide various signal transmission paths (see arrows in FIG. 2(a)).

FIG. 2(b) shows a circuit line providing a transmission path for a specific signal of the second circuit C2. Referring to FIG. 2B, the second circuit C2 includes: i) a circuit line (not shown) connecting the first element mounting portion M1 and the first circuit C1; iii) circuit lines C21 and C22 connecting the first element mounting portion M1 and the second element mounting portion M2; The circuit line can be electrically connected to the connecting via 400 in cases i) and ii) and electrically isolated from the connecting via 400 in case iii).

Here, the circuit lines C21 and C22 that connect the first element mounting portion M1 and the second element mounting portion M2 are bridge circuits that connect the first electronic element E1 and the second electronic element E2. physical connections (which can be referred to as die to die interconnections). A plurality of bridge circuits can be formed, and two electronic elements E1 and E2 can be connected via the second via V2.

That is, a part of the second circuit C2 can electrically connect at least two of the plurality of element mounting parts, and another part of the second circuit C2 can connect any one element mounting part. and the connection via 400 can be electrically connected.

A solder resist layer 500 may be laminated on the upper surface of the first laminate 100 and the upper surface of the second laminate 200 . Openings are formed in the solder resist layer 500, and the outermost circuits C1' and C2' can be exposed through the openings. In particular, the pads of the outermost circuits C1' and C2' are exposed through the openings, and the exposed pads can function as mounting pads.

Meanwhile, the solder resist layer 500 may be laminated on the lower surface of the first laminate 100 as well.

[Second embodiment]
FIG. 3 shows a printed circuit board according to a second embodiment of the present invention.

Referring to FIG. 3, the second circuit C2' located in the outermost layer (uppermost layer) of the printed circuit board according to the second embodiment protrudes from the resin layer 210. As shown in FIG. Here, the second circuit C2′ located in the outermost layer (uppermost layer) protrudes from the first laminate 100. As shown in FIG. This is distinguished from the fact that the second circuit C2' located in the outermost layer (uppermost layer) is embedded in the resin layer 210 and does not protrude beyond the first laminate 100 in the first embodiment.

[Third embodiment]
FIG. 4 is a diagram showing a printed circuit board according to a third embodiment of the invention.

Referring to FIG. 4, in the printed circuit board according to the third embodiment, the top surface of the second stack 200 is positioned lower than the top surface of the first stack 100 . Thereby, the resin layer 210 does not fill the entire cavity 120 , and the solder resist layer 500 can fill a part of the cavity 120 . This embodiment is distinguished from the first embodiment in which the cavity 120 is completely filled with the second stack 200 .

On the other hand, the second circuit C<b>2 ′ located in the outermost layer (uppermost layer) protrudes from the resin layer 210 but does not protrude from the first laminate 100 .

[Fourth embodiment]
FIG. 5 is a diagram showing a printed circuit board according to a fourth embodiment of the invention.

Referring to FIG. 5 , the printed circuit board according to the fourth embodiment includes a first laminate 100 , a cavity 120 , a second laminate 200 , and may further include a second resin layer 220 .

The second resin layer 220 may fill the cavity 120 and extend to the top surface of the first laminate 100 so as to be stacked on the second laminate 200 . The second resin layer 220 can be made of the same material as the resin layer 210 of the second laminate 200, and the second resin layer 220 can contain a photosensitive resin.

Referring to FIG. 5A, a via (third via V3) penetrating the second resin layer 220 is formed on the outermost second circuit C2' of the second laminate 200, and the second resin A third circuit C3 is formed on layer 220 . Here, the pads of the third circuit C3 can function as mounting pads. The third circuit C3 may have the same spec as the second circuit C2.

5A, the solder resist layer 500 is laminated on the second resin layer 220, and the openings of the solder resist layer 500 can penetrate the second resin layer 220. As shown in FIG. When both the solder resist layer 500 and the second resin layer 220 contain a photosensitive resin, the openings in the solder resist layer 500 can be formed by a photolithography process.

Referring to FIG. 5B, a first via V1' may be formed in the via hole VH located in the outermost insulating layer 110 of the first stack 100. Referring to FIG. That is, the first via V1' is formed under the outermost first circuit C1'. Here, the second resin layer 220 can fill the inside of the via hole VH so as to surround the first via V1'.

The outermost first circuit C1' is formed on the second resin layer 220 and can provide mounting pads.

A via (third via V3) penetrating the second resin layer 220 is formed on the second circuit C2′ of the outermost layer of the second laminate 200, and a third circuit C2′ is formed on the second resin layer 220. C3 is formed. Here, the pads of the third circuit C3 can function as mounting pads.

As shown in FIG. 5, the use of the second resin layer 220 can enhance the adhesion between the first laminate 100 and the second laminate 200 .

[Fifth embodiment]
FIG. 6 is a diagram showing a printed circuit board according to a fifth embodiment of the present invention. 7 is a diagram showing a package using the printed circuit board of FIG.

Referring to FIG. 6 , the printed circuit board according to the fifth embodiment includes a first laminate 100 , a cavity 120 , a second laminate 200 , and may further include a metal post 600 .

Metal posts 600 may be formed through the solder resist layer 500 and may provide mounting pads. Since the metal post 600 protrudes from the solder resist layer 500, the distance between the printed circuit board and the electronic element is narrowed, and the height of the low melting point metal member LM for mounting the electronic element can be reduced (see FIG. 7). ).

Metal posts 600 may include post vias 610 and post pads 620 . The post via 610 penetrates the solder resist layer 500 and can be formed on the outermost first circuit C1', the outermost second circuit C2' or the third circuit C3. The post pads 620 protrude beyond the solder resist layer 500 to provide mounting pads.

On the other hand, FIG. 6(a) shows the printed circuit board described with reference to FIG. 3 with metal posts 600 added thereto, and FIG. 6(b) shows the printed circuit board described with reference to FIG. A metal post 600 is added. Also, FIG. 6(c) is obtained by adding a metal post 600 to the printed circuit board described with reference to FIG. 5(b). On the other hand, FIG. 7 shows a package using the printed circuit board of FIG. 6(a).

[Sixth embodiment]
FIG. 8 is a diagram showing a printed circuit board according to a sixth embodiment of the present invention.

Referring to FIG. 8, the printed circuit board according to the sixth embodiment of the present invention may include a first laminate 100, a cavity 120 and a second laminate 200. As shown in FIG.

The first stacked body 100 is formed by vertically stacking a plurality of insulating layers 110 . The insulating layer 110 is a layer formed of an organic or inorganic insulating material, and may include resin. Examples of the resin of the insulating layer 110 include thermosetting and thermoplastic resins, and specific examples include epoxy resin, imidazole resin, polyimide resin, BT (bismaleimide triazine) resin, and fluorine-based resin. It can include, but is not limited to, at least one of resins.

The insulation layer 110 may include a fiber reinforcing material such as a glass fiber inside, and a specific insulation layer 110 may use prepreg. Also, the insulating layer 110 may contain fillers such as organic fillers or inorganic fillers. Silica is an example of the inorganic filler contained in the insulating layer 110 .

A plurality of insulating layers 110 made of the same or different materials may be laminated layer by layer to form the first laminate 100 . Although two insulating layers 110 are shown in FIG. 1, the number of insulating layers 110 can be changed by design or the like.

A circuit can be formed on the first laminate 100, and the circuit formed on the first laminate 100 is referred to as a first circuit C1. The first circuit C1 can be made of metal, and the metal of the first circuit C1 can include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The first circuit C1 may be formed on one surface of each insulating layer 110 . The first circuits C1 located in different layers can be electrically connected through vias (first vias V1). Referring to FIG. 8, among the first circuits C1, the first circuit C1′ in the uppermost layer located closest to the element mounting surface protrudes from the insulating layer 110 in the uppermost layer and is located farthest from the element mounting surface. The lower first circuit C1″ is embedded in the lower surface of the lowermost insulating layer 110, and the remaining surface of the lowermost first circuit C1″ except for the lower surface can be covered with the lowermost insulating layer 110.

The first circuit C1 may include multiple circuit lines. A pad may be provided at the end of each circuit line. This pad can be connected to a via, such as the first via V1.

On the other hand, among the first circuits C1, the outermost first circuit C1' positioned closest to the device mounting surface may provide a device mounting portion including mounting pads for mounting an electronic device.

A cavity 120 may be formed in the first stack 100 . A cavity 120 is formed in the first stack 100 and opened upward. However, since the lower portion of the cavity 120 is not open, the cavity 120 penetrates only part of the thickness of the first laminate 100 . As shown in FIG. 1, the depth of the cavity 120 can be greater than or equal to N thicknesses of the insulating layers 110 of the first stack 100, and the bottom surface of the cavity 120 is two insulating layers 110 may not be coplanar with the interface between them.

A portion of the first circuit C1 can be exposed by the cavity 120. FIG. The first circuit C1 located in the insulating layer 110 in contact with the cavity 120 among the plurality of insulating layers 110 can be exposed by the cavity 120, and the pads provided at the ends of the first circuit C1 are exposed. be able to. The pads of the first circuit C<b>1 exposed by the cavity 120 are called connection pads 300 . In other words, the cavity 120 exposes the connection pads 300 of the first circuit C 1 , and the connection pads 300 are the pads of the first circuit C 1 located below the cavity 120 .

The second laminate 200 is formed in the cavity 120 and may be formed by vertically stacking a plurality of resin layers 210 . A plurality of resin layers 210 may be sequentially stacked within the cavity 120 .

The resin layer 210 includes a resin, specifically, an epoxy resin, an imidazole resin, a polyimide resin, a liquid crystal polymer (LCP), a BT (bismaleimide triazine) resin, or a fluorine-based resin. and is not limited thereto.

The resin layer 210 may contain a photosensitive resin. In this case, the resin layer 210 may react to light and may be processed through a photolithography process. The resin layer 210 containing photosensitive resin may be a PID (photo imageable dielectric). Also, the photosensitive resin may be of a positive type or a negative type.

In the case of the positive resin layer 210, the photopolymer bond in the portion exposed to light is cut during the exposure process. After that, when a developing process is performed, the part where the photopolymer polymer bond is cut by exposure to light is removed.

In the case of the negative type resin layer 210, the portion exposed to light in the exposure process undergoes a photopolymerization reaction to change from a single structure to a chain structure three-dimensional network structure. is removed.

According to the resin layer 210 containing a photosensitive resin, it is possible to form circuits and vias in a photolithography process, so fine pattern processing can be facilitated.

The thickness of the resin layer 210 can be smaller than the thickness of the insulating layer 110 . That is, the thickness of one of the plurality of resin layers 210 may be smaller than the thickness of one of the plurality of insulation layers 110 .

The top surface of the resin layer 210 , that is, the top surface of the second laminate 200 may be positioned on the same plane as the top surface of the first laminate 100 .

A circuit can be formed in the second laminate 200, and the circuit formed in the second laminate 200 is referred to as a second circuit C2. The second circuit C2 can be made of metal, and the metal of the second circuit C2 can include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The second circuit C2 can be formed on one surface (upper surface) of each resin layer 210 . The outermost layer (uppermost layer) second circuit C2′ located closest to the element mounting surface protrudes from the outermost layer (uppermost layer) resin layer 210 and is located closest to the element mounting surface. The top surface of C2' may be flush with the top surface of the outermost first circuit C1' located closest to the device mounting surface. However, unlike FIG. 8, the thickness of the outermost second circuit C2' may be smaller than the thickness of the outermost first circuit C1'. In this case, the top surfaces of the two outermost circuits C1' and C2' are not coplanar.

The second circuits C2 located in different layers can be connected to each other through vias (second vias V2).

On the other hand, in the second laminate 200 , connection vias 400 can be formed that penetrate the lowermost resin layer 211 and contact the connection pads 300 . That is, the connection via 400 can electrically connect the connection pad 300 and the second circuit C2.

The circuit width of the first circuit C1 can be greater than the circuit width of the second circuit C2. The circuit thickness of the first circuit C1 can be greater than the circuit thickness of the second circuit C2. The second circuit C2 may have a finer pitch than the first circuit C1. The circuit density of the second circuits C2 can be greater than the circuit density of the first circuits C1.

The size of the first vias V1 may be larger than the size of the second vias V2, and the pitch of the first vias V1 may be larger than the pitch of the second vias V2. Also, the connection via 400 may have the same size as the second via V2.

The second circuit C2 may include multiple circuit lines. A pad may be provided at the end of each circuit line. This pad can be connected to the second via V2. On the other hand, the outermost second circuit C2' located closest to the device mounting surface of the second circuits C2 may provide a device mounting portion including mounting pads for mounting the electronic device.

Each of the plurality of element mounting portions is formed over both the first laminate 100 and the second laminate 200 . That is, the first element mounting portion M1 is provided on the first layered body 100 and the second layered body 200, and the second element mounting portion M2 is also provided on the first layered body 100 and the second layered body 200. FIG. The top surface of the second stack 200 can be divided into a plurality of sections to provide a plurality of device mounting portions.

The first electronic element E1 is mounted on the first element mounting portion M1, and the second electronic element E2 is mounted on the second element mounting portion M2. The first electronic element E1 is positioned over both the first stacked body 100 and the second stacked body 200, and the second electronic element E2 is also positioned over both the first stacked body 100 and the second stacked body 200. FIG.

The first electronic element E1 includes an electrode terminal T1, and the electrode terminal T1 can be coupled to a mounting pad of the first element mounting portion M1 of the printed circuit board by a low melting point metal member LM. An underfill material F may be filled between the first electronic element E1 and the printed circuit board. The second electronic element E2 includes an electrode terminal T2, and the electrode terminal T2 can be coupled to the mounting pad of the second element mounting portion M2 of the printed circuit board by the low melting point metal member LM. An underfill material F may be filled between the second electronic element E2 and the printed circuit board.

As noted above, the second circuit C2 may include multiple circuit lines. The second circuit C2 may include circuit lines electrically connecting to the connecting vias 400 . Also, the second circuit C2 can include a circuit line that is electrically insulated from the connection via 400 and electrically connects the plurality of element mounting portions. In this case, the second circuit C2 can provide various signal transmission paths.

The second circuit C2 includes: i) a circuit line connecting the first element mounting portion M1 and the first circuit C1; ii) a circuit line connecting the second element mounting portion M2 and the second circuit C2; A circuit line connecting the element mounting portion M1 and the second element mounting portion M2 can be included. The circuit line can be electrically connected to the connecting via 400 in cases i) and ii) and electrically isolated from the connecting via 400 in case iii).

That is, a part of the second circuit C2 can electrically connect at least two of the plurality of element mounting parts, and another part of the second circuit C2 can connect any one element mounting part. and the connection via 400 can be electrically connected.

A solder resist layer 500 can be laminated on the upper surface of the first laminate 100 and the upper surface of the second laminate 200 . Openings are formed in the solder resist layer 500, and the outermost circuits C1' and C2' can be exposed through the openings. In particular, the pads of the outermost circuits C1' and C2' are exposed through the openings, and the exposed pads can function as mounting pads. Meanwhile, the solder resist layer 500 is also laminated on the lower surface of the first laminate 100 to cover the lowermost first circuit C1″.

[Seventh embodiment]
FIG. 9 is a diagram showing a printed circuit board according to a seventh embodiment of the invention.

Referring to FIG. 9, the printed circuit board according to the seventh embodiment includes a first laminate 100, a cavity 120, a second laminate 200, and further includes a second resin layer 220 and/or metal posts 600. can be done.

The second resin layer 220 may be stacked on the second laminate 200 to fill the cavity 120 and extend to the top surface of the first laminate 100 . The second resin layer 220 can be made of the same material as the resin layer 210 of the second laminate 200, and the second resin layer 220 can contain a photosensitive resin.

A first via V1′ may be formed in the via hole VH located in the outermost insulating layer 110 of the first stack 100 . That is, the first via V1' is formed under the outermost first circuit C1'. Here, the second resin layer 220 can fill the inside of the via hole VH so as to surround the first via V1'.

The outermost first circuit C 1 ′ may be formed on the second resin layer 220 . A via (third via V3) penetrating the second resin layer 220 is formed on the second circuit C2′ of the outermost layer of the second laminate 200, and the third circuit C3 is formed on the second resin layer 220. be done.

The solder resist layer 500 is laminated on the second resin layer 220 and may also be laminated on the lower surface of the first laminate 100 .

Metal posts 600 may be formed through the solder resist layer 500 and may provide mounting pads. Since the metal post 600 protrudes from the solder resist layer 500, the distance between the printed circuit board and the electronic element is narrowed, and the height of the low melting point metal member LM for mounting the electronic element can be reduced.

Metal posts 600 may include post vias 610 and post pads 620 . The post via 610 penetrates the solder resist layer 500 and can be formed on the outermost first circuit C1', the outermost second circuit C2' or the third circuit C3. The post pads 620 protrude beyond the solder resist layer 500 to provide mounting pads.

<Method for manufacturing printed circuit board>
10 and 11 are diagrams illustrating a method of manufacturing a printed circuit board and a package including the printed circuit board according to an embodiment of the present invention.

10 and 11 illustrate a method of manufacturing the printed circuit board shown in FIG. 3, the manufacturing method described above is also applicable to methods of manufacturing other printed circuit boards.

Referring to FIG. 10(a), a plurality of insulating layers 110 are vertically laminated to form a first circuit C1 to form a first laminate 100. As shown in FIG.

Although not shown, a carrier can be used to form the first stack 100 . That is, the first laminate 100 can be formed by sequentially stacking a plurality of insulating layers 110 on a carrier, forming the first circuit C1 on each side of each layer, and then removing the carrier. Here, the a-plane is the carrier adhesion surface, and the first circuit C1 on the carrier adhesion surface side can be an embedded circuit. Here, the a-plane is the device mounting surface.

Referring to FIG. 10( b ), a cavity 120 is formed in the first laminate 100 . Cavity 120 can be formed by laser processing. A part of the first circuit C1 can be exposed by the cavity 120, and in particular, a pad of the first circuit C1 can be exposed, and the exposed pad becomes the connection pad 300. FIG.

Referring to FIGS. 10(c) and 10(d), a second laminate 200 is formed by vertically stacking a plurality of resin layers 210 in a cavity 120 to form a second circuit C2.

First, as shown in FIG. 10C, the bottom resin layer 211 is formed on the bottom surface of the cavity 120 . The resin layer 210 can be formed by a spray method. As shown in FIG. 10D, the lowermost resin layer 211 is processed to form via holes, and the via holes are plated to form connection vias 400 and second circuits C2. If the resin layer 210 contains a photosensitive resin, the via holes may be formed by photolithography. Connection vias 400 are formed in direct contact with connection pads 300 exposed by cavities 120 .

Referring to FIG. 11(a), the second laminate 200 can be formed by repeating the steps of FIGS. 10(c) and 10(d). Here, the formed first laminate 100 and second laminate 200 are in the same form as the printed circuit board shown in FIG. 3, but all printed circuit boards shown in FIGS. can be substituted for

Referring to FIG. 11B, a solder resist layer 500 is formed and openings are formed in the solder resist layer 500 to expose the pads of the outermost circuits C1' and C2'. The exposed pads can function as mounting pads.

Referring to FIG. 11(c), a low melting point metal member LM is positioned on the exposed mounting pad, and the electrode terminal T1 of the first electronic element E1 and the electrode of the second electronic element E2 are attached to the low melting point metal member LM. Terminal T2 can be coupled. An underfill material F may be filled under the first electronic element E1 and the second electronic element E2.

The first electronic element E1 is electrically connected to the first circuit C1 of the first laminate 100 and also electrically connected to the second circuit C2 of the second laminate 200 . Similarly, the second electronic element E2 is electrically connected to the first circuit C1 of the first laminate 100 and electrically connected to the second circuit C2 of the second laminate 200 as well. In particular, the bridge circuit connecting the first element mounting portion M1 and the second element mounting portion M2 of the second circuit C2 connects the first electronic element E1 and the second electronic element E2.

12 and 13 are diagrams showing a method of manufacturing a package according to another embodiment of the present invention. 12 and 13 illustrate a method of manufacturing the printed circuit board shown in FIG.

Referring to FIGS. 12(a) and 12(b), a plurality of insulating layers 110 are vertically laminated to form a first circuit C1 to form a first laminate 100. As shown in FIG. Although not shown, a carrier can be used to form the first stack 100 . That is, the first laminate 100 is formed by sequentially stacking a plurality of insulating layers 110 on a carrier, forming the first circuit C1 on each side of each layer, and then removing the carrier. Here, the b surface is a carrier adhesion surface, and the first circuit C1 on the carrier adhesion surface side can be an embedded circuit. Also, here, the surface b is the surface opposite to the element mounting surface.

Referring to FIG. 12( c ), a cavity 120 is formed in the first laminate 100 . Cavity 120 can be formed by laser processing. A part of the first circuit C1 can be exposed by the cavity 120, and in particular, a pad of the first circuit C1 can be exposed, and the exposed pad becomes the connection pad 300. FIG.

On the other hand, via holes VH are formed in the outermost insulating layer 110 . The via hole VH can be formed by laser processing.

Referring to FIG. 12(d), the second stack 200 is formed in the cavity 120. The method of forming the second stack 200 is shown in FIGS. 10(c) and 10(d). Same as explained.

Referring to FIG. 12( e ), a second resin layer 220 is formed on the second laminate 200 . The second resin layer 220 is also formed on the upper surface of the first laminate 100 and fills the inside of the via hole VH.

Referring to FIG. 13( a ), via holes VH′ are formed in the second resin layer 220 . A via hole VH' of the second resin layer 220 is formed inside the via hole VH of the insulating layer 110 to expose the pad of the first circuit C1. Also, the via holes VH' of the second resin layer 220 can expose the pads of the outermost second circuit C2'.

Referring to FIG. 13(b), a first via V1' located on the outermost layer and a first circuit C1' on the outermost layer are formed, and a third via V3 and a third circuit C3 are formed. All of these can be formed by plating.

Referring to FIG. 13( c ), a solder resist layer 500 is laminated on the second resin layer 220 and laminated on the lower surface of the first laminate 100 . A metal post 600 is also formed. Here, after forming openings in the solder resist layer 500 , the openings can be plated to form post vias 610 , and the openings can be overplated to form post pads 620 . The post pads 620 protrude from the solder resist layer 500 and function as mounting pads.

Referring to FIG. 13D, a low melting point metal member LM is positioned on the metal post 600, and the electrode terminal T1 of the first electronic element E1 and the electrode terminal T2 of the second electronic element E2 are connected to the low melting point metal member LM. can be combined. An underfill material F may be filled under the first electronic element E1 and the second electronic element E2.

The first electronic element E1 is electrically connected to the first circuit C1 of the first laminate 100 and also electrically connected to the second circuit C2 of the second laminate 200 . Similarly, the second electronic element E2 is electrically connected to the first circuit C1 of the first laminate 100 and electrically connected to the second circuit C2 of the second laminate 200 as well. In particular, the bridge circuit connecting the first element mounting portion M1 and the second element mounting portion M2 in the second circuit C2 connects the first electronic element E1 and the second electronic element E2.

An embodiment of the present invention has been described above. However, those skilled in the art will be able to add components without departing from the spirit of the present invention described in the scope of claims. , alterations, deletions, additions, etc., can be variously modified and changed, which are also included in the scope of the invention.

100 first laminate 110 insulating layer 120 cavity 200 second laminate 210 resin layer 220 second resin layer 300 connection pad 400 connection via C1 first circuit C2 second circuit 500 solder resist layer 600 metal post 610 post via 620 post pad M1 First element mounting part M2 Second element mounting part

Claims (14)

A printed circuit board comprising a plurality of element mounting parts,
a first laminate including a plurality of insulating layers and a first circuit;
a cavity formed in the first laminate and open to the upper surface of the first laminate;
a second laminate including a plurality of resin layers laminated in the cavity and a second circuit;
a second resin layer formed on the upper surfaces of the first laminate and the second laminate;
including
the first circuit includes connection pads exposed by the cavity;
the second laminate includes a connection via that penetrates the resin layer located at the bottom and contacts the connection pad;
the second circuit is electrically connected to the plurality of element mounting portions;
A via hole is formed in the insulating layer positioned as the outermost layer of the first laminate,
a via is formed in the via hole,
The printed circuit board , wherein the second resin layer surrounds the via and fills the inside of the via hole . the top surface of the second laminate is positioned below the height of the top surface of the first laminate;
2. The printed circuit board according to claim 1, wherein the second resin layer is laminated on the second laminate so as to fill the inside of the cavity. 3. The printed circuit board according to claim 1 , wherein a portion of said second circuit electrically connects said plurality of element mounting portions to each other. 4. The printed circuit board according to claim 1, wherein a part of said second circuit electrically connects one of said element mounting portions and said connection via. The printed circuit board according to any one of claims 1 to 4 , wherein the resin layer contains a photosensitive resin. The printed circuit board according to any one of claims 1 to 5 , wherein the thickness of the resin layer is smaller than the thickness of the insulating layer. The printed circuit board according to any one of claims 1 to 6 , wherein the circuit width of the first circuit is larger than the circuit width of the second circuit. The printed circuit board according to any one of claims 1 to 7 , wherein the first circuit located on the uppermost layer of the first laminate is embedded in the upper surface of the insulating layer located on the uppermost layer. The printed circuit board according to any one of claims 1 to 7, wherein the first circuit positioned on the uppermost layer of the first laminate protrudes from the insulating layer positioned on the uppermost layer. 10. The printed circuit board according to claim 1, further comprising a solder resist layer laminated on said second resin layer. The printed circuit board according to any one of claims 1 to 9 , further comprising a third circuit formed on said second resin layer and electrically connected to said second circuit. The printed circuit board according to any one of claims 1 to 11 , further comprising a solder resist layer laminated on the first laminate and the second laminate. 13. The printed circuit board of claim 12 , further comprising a metal post penetrating the solder resist layer to provide the device mounting portion. The metal post is
a post via penetrating through the solder resist layer;
14. The printed circuit board of claim 13 , further comprising a post pad formed on the post via projecting from the solder resist layer.

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