KR102628149B1 - Printed circuit board with bridge pattern and method of manufacturing the same - Google Patents

Abstract

A printed circuit board according to one embodiment includes a first substrate having a cavity and a circuit pattern layer having a first minimum line width; a second substrate disposed inside the cavity and including a circuit pattern layer having a second minimum line width smaller than the first minimum line width; a passivation layer that fills the cavity and covers the first and second substrates, the passivation layer selectively exposing the circuit pattern layers of the first and second substrates, respectively; and a conductive bridge pattern disposed on the passivation layer to electrically connect the partially exposed circuit pattern layers of the first and second substrates to each other.

Description

Printed circuit board with bridge pattern and method of manufacturing the same}

This application relates to printed circuit boards (PCBs) and methods for manufacturing the same.

As electronic devices become smaller, electronic components are becoming more highly functional and smaller. Due to the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers are becoming more high-performance and highly functional, and various functions are being integrated into a single device and becoming complex.

In this way, as electronic devices become smaller and more functional, there is a demand for printed circuit boards placed inside the electronic devices to also be miniaturized. As an example, as the line width and pitch size of the device chip that performs computation and control operations in the electronic device decreases, it is requested that the line width and pitch size of the circuit pattern of the printed circuit board on which the device chip is mounted also decrease. there is. That is, the demand for printed circuit boards having a circuit pattern layer with a smaller minimum line width that can effectively exchange electrical signals with miniaturized device chips is increasing.

The problem that this application seeks to solve is to provide a printed circuit board having a micropattern with a smaller minimum line width that can effectively exchange electric signals with a miniaturized device chip, and a method for manufacturing the same.

A printed circuit board according to one aspect includes a first substrate having a cavity and a circuit pattern layer having a first minimum line width; a second substrate disposed inside the cavity and including a circuit pattern layer having a second minimum line width smaller than the first minimum line width; a passivation layer that fills the cavity and covers the first and second substrates, the passivation layer selectively exposing the circuit pattern layers of the first and second substrates, respectively; and a conductive bridge pattern disposed on the passivation layer to electrically connect the partially exposed circuit pattern layers of the first and second substrates to each other.

In one embodiment, the device may further include a device chip electrically connected to the second substrate and electrically connected to the first substrate through the conductive bridge pattern.

In one embodiment, the first substrate includes a core insulating layer; an upper inner layer circuit pattern and a lower inner layer circuit pattern respectively disposed on the upper and lower surfaces of the core insulating layer; an upper interlayer insulating layer and a lower interlayer insulating layer covering the upper inner layer circuit pattern and the lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer, respectively; and an upper outer layer circuit pattern and a lower outer layer circuit pattern disposed on the upper interlayer insulating layer and the lower interlayer insulating layer, respectively. At this time, the cavity penetrates the upper interlayer insulating layer and the core insulating layer to expose the lower interlayer insulating layer, and the upper outer layer circuit pattern is provided with a first bridge connection pad configured to connect to the conductive bridge pattern. can do.

In one embodiment, the second substrate includes a substrate body made of an inorganic material, and the substrate body made of an inorganic material is at least one of glass, quartz, silicon, silicon oxide, germanium, and III-V compound semiconductor. may include.

In one embodiment, the circuit pattern layer of the second substrate includes a chip connection pad configured to connect to a device chip and disposed at a central portion of the upper surface of the second substrate; a second bridge connection pad configured to connect to the conductive bridge pattern and disposed on an edge portion of the upper surface of the second substrate; and a second substrate wiring connecting the chip connection pad and the second bridge connection pad. At this time, the height of the chip connection pad on the upper surface of the second substrate may be lower than the height of the second bridge connection pad.

In one embodiment, the chip connection pad may have a smaller surface area than the second bridge connection pad on the top surface of the second substrate.

In one embodiment, the conductive bridge pattern may include at least one selected from the group consisting of a plating material, a solder material, and a conductive paste material.

In one embodiment, the passivation layer may include epoxy or a photosensitive material.

In one embodiment, the first minimum line width of the first substrate may be 10 μm or more, and the second minimum line width of the second substrate may be 5 μm or less.

A method of manufacturing a printed circuit board according to another aspect of the present application is disclosed. The manufacturing method includes preparing a first substrate having a cavity and a circuit pattern layer having a first minimum line width; Preparing a second substrate having a circuit pattern layer having a second minimum line width smaller than the first minimum line width; Placing the second substrate inside the cavity of the first substrate; forming a passivation layer that fills the cavity and simultaneously covers the first and second substrates; Patterning the passivation layer to selectively expose the circuit pattern layers of the first and second substrates, respectively; and forming a conductive bridge pattern on the passivation layer to electrically connect the partially exposed circuit pattern layers of the first and second substrates to each other.

In one embodiment, the method may further include preparing a device chip and bonding the device chip to the circuit pattern layer of the second substrate using a connection structure.

In one embodiment, preparing the first substrate includes forming an upper inner layer circuit pattern and a lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer, respectively; forming an upper interlayer insulating layer and a lower interlayer insulating layer respectively covering the upper inner layer circuit pattern and the lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer; forming an upper outer layer circuit pattern and a lower outer layer circuit pattern on the upper interlayer insulating layer and the lower interlayer insulating layer, respectively; and forming a cavity that penetrates the upper interlayer insulating layer and the core insulating layer to expose the lower interlayer insulating layer. At this time, the upper outer layer circuit pattern may be provided with a bridge connection pad configured to connect to the conductive bridge pattern.

In one embodiment, preparing the second substrate includes providing a substrate body made of an inorganic material; and forming a conductive layer on the upper surface of the substrate body. The step of forming the conductive layer may apply at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and plating.

In one embodiment, forming the conductive layer includes forming a first connection pad for connection with a device chip at the center of the upper surface of the substrate body; forming a second connection pad for connection to the conductive bridge pattern on an upper edge portion of the substrate body; and forming a substrate wiring connecting the first connection pad and the second connection pad on the upper surface of the substrate body. At this time, the height of the first connection pad on the upper surface of the substrate body may be formed to be lower than the height of the second connection pad. Additionally, the first connection pad may have a smaller surface area than the second connection pad on the substrate body.

In one embodiment, forming the passivation layer may include filling the second substrate with an epoxy material and covering the upper and lower surfaces of the first substrate with the epoxy material.

In one embodiment, forming the passivation layer may include burying the second substrate with a photosensitive material and covering the upper and lower surfaces of the first substrate with the photosensitive material.

In one embodiment, the step of selectively exposing the circuit pattern layers of the first and second substrates includes at least a portion of the upper surface of the connection pad connected to the conductive bridge pattern among the circuit pattern layers of the first substrate. exposing; exposing at least a portion of an upper surface of a connection pad connected to the conductive bridge pattern among the circuit pattern layers of the second substrate; and exposing the top and side surfaces of the connection pad disposed on the second substrate and connected to the device chip.

In one embodiment, forming the conductive bridge pattern may include forming a plating pattern layer connecting the connection pads of the first and second substrates to each other by applying a plating method.

In one embodiment, the step of forming the conductive bridge pattern includes forming a conductive pattern layer connecting the connection pads of the first and second substrates to each other by applying a coating method using a solder material or a conductive paste material. May include steps.

According to one embodiment of the present invention, a first substrate including a cavity and a circuit pattern layer having a first minimum line width is provided. Additionally, a second substrate including a circuit pattern layer having a second minimum line width smaller than the first minimum line width is provided. The second substrate is placed in the cavity of the first substrate, and the circuit pattern layers of the first and second substrates are electrically connected to each other using a conductive bridge pattern. As a result, a printed circuit board including first and second substrates having different minimum line widths can be provided.

When a device chip having a circuit pattern layer of a fine line width is mounted on the above-described printed circuit board, the device chip is arranged to be connected to the second substrate having a circuit pattern layer of the second minimum line width. The device chip may be electrically connected to the first substrate via the conductive bridge pattern. Through this, the device chip having the circuit pattern layer with a fine line width can be stably connected to the first substrate having the circuit pattern layer with a relatively large line width.

1 is a cross-sectional view schematically showing a printed circuit board according to an embodiment of the present invention.
Figure 2 is a cross-sectional view schematically showing a printed circuit board according to another embodiment of the present application.
FIG. 3 is a schematic diagram schematically showing the arrangement of the first substrate, second substrate, and device chip of the printed circuit board shown in FIG. 2.
4 to 10 are cross-sectional views schematically explaining a method of manufacturing a printed circuit board according to embodiments of the present application.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. In order to clearly express the components of each device in the drawing, the sizes of the components, such as width and thickness, are shown somewhat enlarged.

When an element is referred to as being located on top of another element, this includes both the meaning that the one element may be located directly on top of the other element or that additional elements may be interposed between those elements.

In a plurality of drawings, like symbols refer to substantially the same elements. In addition, singular expressions should be understood to include plural expressions, unless the context clearly indicates otherwise, and terms such as 'include' or 'have' refer to the features, numbers, steps, operations, components, or parts being described. It is intended to specify the existence of a combination of these, but it should be understood that it does not exclude in advance the possibility of the existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

As used herein, the terms 'upper surface' or 'lower surface' of a substrate or device chip are relative concepts observed from an observer's perspective. Accordingly, one of the two surfaces excluding the side of the substrate or device chip can be referred to as the 'top surface' or 'bottom surface', and correspondingly, the remaining surface can be referred to as the 'bottom surface' or 'top surface'. Likewise, in this specification, the concepts 'upper', 'above' or 'lower' and 'below' may also be used as relative concepts.

1 is a cross-sectional view schematically showing a printed circuit board according to an embodiment of the present invention. Referring to FIG. 1, the printed circuit board 1 includes a first substrate 10 having a cavity 10h, a second substrate 20 disposed inside the cavity 10h, and a first substrate 10 and a second substrate 10. 2 It includes a conductive bridge pattern 160 that electrically connects the circuit pattern layers of the substrate 20 to each other.

In one embodiment, the first substrate 10 has the configuration of a printed circuit board including a copper plating layer and an insulating layer made of an organic material, and the second substrate 20 has a substrate body made of an inorganic material. It may have a substrate configuration including a conductive layer formed through a semiconductor integration process. The inorganic material may be a ceramic material or a semiconductor material. As an example, the substrate body may include at least one of glass, quartz, silicon, silicon oxide, germanium, and group III-V compound semiconductor. For example, the group III-V compound semiconductor may include gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or gallium nitride (GaN). The semiconductor integration process may include, for example, a deposition method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or plating. In addition, the semiconductor integration process includes, as an example, a method of forming a photosensitive resist thin film, a method of forming a mask pattern layer through exposure and development of the photosensitive resist thin film, and a conductive layer or insulating layer using the mask pattern layer. It may include an etching method.

Using the semiconductor integration process, the second substrate 20 can be provided with a circuit pattern layer with a minimum line width smaller than that of the circuit pattern layer of the first substrate 10. As an example, the second substrate 20 may be provided with a circuit pattern layer having a minimum line width of 5 μm or less. More specifically, the second substrate 20 may be provided with a circuit pattern layer having a minimum line width of 1 μm or less. On the other hand, as an example, the first substrate 10 may be provided with a circuit pattern layer having a minimum line width of 10 μm or more.

Referring to Figure 1, a first substrate 10 is provided. The first substrate 10 may include a core insulating layer 110 and an upper inner layer circuit pattern 120a and a lower inner layer circuit pattern 120b disposed on the upper and lower surfaces of the core insulating layer 110, respectively. The core insulating layer 110 may include, for example, epoxy or prepreg (PPG). As an example, the upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b may be a copper pattern layer.

The first substrate 10 includes an upper interlayer insulating layer 130a and a lower interlayer insulating layer covering the upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b on the upper and lower surfaces of the core insulating layer 110, respectively. It may include (130b). The upper interlayer insulating layer 130a and the lower interlayer insulating layer 130b may include, for example, epoxy or prepreg (PPG). As an example, the upper interlayer insulating layer 130a and the lower interlayer insulating layer 130b may include an insulating film. As an example, the insulating film may be Ajimoto Build-up Film (ABF).

The first substrate 10 may include an upper outer layer circuit pattern 140a and a lower outer layer circuit pattern 140b disposed on the upper interlayer insulating layer 130a and the lower interlayer insulating layer 130b, respectively.

As an example, the upper outer layer circuit pattern 140a may include a first upper connection pad 140a-P1, a second upper connection pad 140a-P2, and an upper outer layer wiring 140a-P3.

The first upper connection pad 140a-P1 may be a part of the upper outer layer circuit pattern 140a exposed by the upper passivation layer 150a on the upper interlayer insulating layer 130a. The first upper connection pad 140a-P1 may function as a pad for electrically connecting an external device chip, external package, or external system to the first substrate 10. The first upper connection pad 140a-P1 is connected to the upper inner layer circuit pattern 120a, the lower inner layer circuit pattern 120b, and the lower outer layer circuit pattern 140b through the first via 180a or the second via 180b. ) can be electrically connected to. Additionally, the first upper connection pad 140a-P1 may be electrically connected to the upper outer layer wiring 140a-P3.

The second upper connection pad 140a-P2 may be provided for electrical connection with the second substrate 20. As will be described in detail below, the second upper connection pad 140a-P2 may function as a first bridge connection pad connected to the conductive bridge pattern 160. The second upper connection pad 140a-P2 may be electrically connected to the first upper connection pad 140a-P1 through the upper outer layer wiring 140a-P3.

The upper outer layer wiring 140a-P3 may be a circuit wiring disposed on the upper interlayer insulating layer 130a. As an example, the upper outer layer wiring 140a-P3 may electrically connect the first upper connection pad 140a-P1 and the second upper connection pad 140a-P2.

Referring again to FIG. 1 , the lower outer layer circuit pattern 140b disposed on the lower interlayer insulating layer 130b may include a lower connection pad 140b-P1 and a lower outer layer wiring 140-P2. The lower connection pad 140b-P1 may be a part of the lower outer layer circuit pattern 140a exposed by the lower passivation layer 150b on the lower interlayer insulating layer 130b. The lower connection pad 140b-P1 may function as a pad for electrical connection with an external system. Additionally, the lower connection pad 140b-P1 may be electrically connected to the lower inner layer circuit pattern 120b, the upper inner layer circuit pattern 120a, and the upper outer layer circuit pattern 140a through the first via 180a. .

Referring again to FIG. 1 , a plurality of vias 180a, 180b, and 180c may be disposed inside the first substrate 10. Among the plurality of vias 180a, 180b, and 180c, the first via 180a may be a through via. The first via 180a may electrically connect the first upper connection pad 140a-P1, the upper inner layer circuit pattern 120a, the lower inner layer circuit pattern 120b, and the lower connection pad 140b-P1. Among the plurality of vias 180a, 180b, and 180c, the second via 180b electrically connects the first upper connection pad 140a-P1, the upper inner layer circuit pattern 120a, and the lower inner layer circuit pattern 120b. You can. The upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b of the third via 180c among the plurality of vias 180a, 180b, and 180c may be electrically connected.

Referring again to FIG. 1, the first substrate 10 may include a cavity 10h. The cavity 10h may be formed from the surface of the upper interlayer insulating layer 130a to penetrate the upper interlayer insulating layer 130a and the core insulating layer 110 to expose the lower interlayer insulating layer 130b. A second substrate 20 may be disposed within the cavity 10h. The second substrate 20 may be adhered to the lower interlayer insulating layer 130b by the adhesive layer 230.

The second substrate 20 may include a substrate body 210 and a circuit pattern layer 220 disposed on the upper surface 210S of the substrate body 210.

The substrate body 210 may be made of an inorganic material. As an example, the substrate body 210 may be made of ceramic or semiconductor material. The substrate body 210 may include glass, quartz, silicon (Si), germanium (Ge), group III-V compound semiconductor, or a combination of two or more thereof. For example, the group III-V compound semiconductor may include gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or gallium nitride (GaN).

The circuit pattern layer 220 may include a conductive material. The circuit pattern layer 220 may include metal such as copper, aluminum, nickel, or chromium. The circuit pattern layer 220 may include a first connection pad 220P1, a second connection pad 220P2, and a substrate wiring 220P1.

The first connection pad 220P1 may function as a chip connection pad for connection to a device chip. The first connection pad 220P1 may be disposed to be exposed to the outside. The first connection pad 220P1 may be disposed in the central portion of the upper surface 210S of the substrate body 210. The first connection pad 220P1 may include a conductive material. The first connection pad 220P1 may include metal such as copper, aluminum, nickel, or chromium.

The second connection pad 220P2 may be disposed on an edge portion of the upper surface 210S of the substrate body 210. The second connection pad 220P2 may be configured to connect to the conductive bridge pattern 160. The second connection pad 220P2 may function as a second bridge connection pad corresponding to the first bridge connection pad (i.e., second upper connection pad) 140a-P2 of the first substrate 10. The second connection pad 220P2 may include a conductive material. The second connection pad 220P2 may include metal such as copper, aluminum, nickel, or chromium.

The board wiring 220P3 may be a circuit wiring disposed on the top surface 210S of the board body 210. As an example, the board wiring 220P3 may electrically connect the first connection pad 220P1 and the second connection pad 220P2. As an example, the substrate wiring 220P3 may have a minimum line width of 5 μm or less.

In one embodiment, the height h1 of the first connection pad 220P1, which functions as a chip connection pad, on the upper surface 210S of the substrate body 210 is equal to the height h1 of the second connection pad 220P2, which functions as a second bridge connection pad. ) may be lower than the height (h2). Additionally, the first connection pad 220P1 may have a smaller surface area than the second connection pad 220P2 on the top surface 210S of the substrate body 210.

In one embodiment, the height h2 of the second connection pad 220P2 on the upper surface 210S of the substrate body 210 is greater than the height h2 of the second upper connection pad 220P2 on the upper interlayer insulating layer 130a of the first substrate 10. It may correspond to the height (h3) of (140a-P2). As an example, the top surface of the second connection pad 220P2 and the top surface of the second upper connection pad 140a-P2 may be located at the same level. Additionally, the surface area of the second connection pad 220P2 may correspond to the surface area of the second upper connection pad 140a-P2. As an example, the surface area of the second connection pad 220P2 may be substantially the same as the surface area of the second upper connection pad 140a-P2.

In some not-illustrated embodiments, at least one circuit pattern layer may be disposed inside the substrate body 210 of the second substrate 20 . The at least one circuit pattern layer may be electrically connected to the circuit pattern layer 220 through a conductive via.

Referring again to FIG. 1, after the second substrate 20 is disposed in the cavity 10h of the first substrate 10, the inside of the cavity 10h may be filled with the first upper passivation layer 150a. At the same time, the first upper passivation layer 150a may be disposed to cover the upper portions of the first substrate 10 and the second substrate 20 . That is, the first upper passivation layer 150a that fills the inside of the cavity 10h and the first upper passivation layer 150a that covers the top of the first and second substrates 10 and 20 may be the same material layer. The first upper passivation layer 150a may include, for example, epoxy or a photosensitive material.

At this time, the first upper passivation layer 150a may selectively expose the upper outer circuit pattern layer 140a of the first substrate 10 and the circuit pattern layer 220 of the second substrate 20, respectively. As an example, the first upper passivation layer 150a may expose at least a portion of the upper surface of the first and second upper connection pads 140a-P1 and 140a-P2 of the first substrate 10. In addition, the first upper passivation layer 150a exposes the top and side surfaces of the first connection pad 220P1 and the substrate wiring 220P3 of the second substrate 20, respectively, and forms the second connection of the second substrate 20. At least a portion of the upper surface of the pad 220P2 may be exposed.

Meanwhile, the first lower passivation layer 150b may be disposed to cover the lower portion of the first substrate 10. The first lower passivation layer 150b may include, for example, epoxy or a photosensitive material. The first lower passivation layer 150b may selectively expose the lower outer circuit pattern layer 140b of the first substrate 10. As an example, the first lower passivation layer 150b may expose at least a portion of the upper surface of the lower connection pad 140b-P1 of the first substrate 10.

Referring again to FIG. 1, a conductive bridge pattern 160 may be disposed on the first upper passivation layer 150a. The conductive bridge pattern 160 is formed on the exposed second upper connection pad (i.e., first bridge connection pad) 140a-P2 of the first substrate 10 and the exposed second upper connection pad (i.e., first bridge connection pad) 140a-P2 of the first substrate 10. The connection pads (i.e., second bridge connection pads) 220P2 may be electrically connected to each other. As an example, the conductive bridge pattern 160 may include at least one selected from the group consisting of a plating material, a solder material, and a conductive paste material.

Additionally, a second passivation layer 170 covering the conductive bridge pattern 160 may be disposed on the first upper passivation layer 150a. The second passivation layer 170 prevents the conductive bridge pattern 160 from being exposed to the outside, thereby protecting the conductive bridge pattern 160 from the external environment. The second passivation layer 170 may include, for example, a solder resist material or an epoxy material.

Figure 2 is a cross-sectional view schematically showing a printed circuit board according to another embodiment of the present application. Referring to FIG. 2, compared to the printed circuit board 1 of FIG. 1, the printed circuit board 2 further includes a device chip 30 mounted on the second board 20. The remaining configuration of the printed circuit board 2 except for the device chip 30 is substantially the same as the printed circuit board 1 of FIG. 1.

The device chip 30 includes a chip body 310 and a chip pad 320P disposed on one surface 310S of the chip body 310. The chip pad 320P of the device chip 30 is connected to the first connection pad 220P2 of the second substrate 20 through the connection structure 330, so that the device chip 30 is connected to the second substrate 20. It can be mounted on . The connection structure 330 may be, for example, a bump or solder material. As an example, the device chip 30 may be an active device.

The device chip 30 may be connected to the first connection pad 220P1 of the second substrate 20 and then electrically connected to the second connection pad 220P2 through the substrate wiring 220P3. Subsequently, the device chip 30 may be electrically connected to the second upper connection pad 140a-P2 of the first substrate 10 via the conductive bridge pattern 160. That is, the device chip 30 may be electrically connected to the first substrate 10 via the second substrate 20, rather than directly connected to the first substrate 10. As an example, the device chip 30 may include a circuit pattern layer having a minimum line width of 5 μm or less. The line width of the circuit pattern layer 220 of the second substrate 20 may have a size corresponding to the line width of the circuit pattern layer of the device chip 30.

FIG. 3 is a schematic diagram schematically showing the arrangement of the first substrate, second substrate, and device chip of the printed circuit board shown in FIG. 2. In FIG. 3 , the first upper passivation layer 150a and the second passivation layer 170 shown in FIG. 2 are omitted for convenience of explanation. In addition, in FIG. 3, a first bridge connection pad (i.e., a second upper connection pad) 140a-P2 and a second bridge connection pad (i.e., a second upper connection pad) 140a-P2 for electrical connection between the first substrate 10 and the second substrate 20 are shown. 2 connection pad) (220P2) and a conductive bridge pattern (160) are shown. At this time, the first upper connection pad 140a-P1 and the upper outer layer wiring 140a-P3 of the first substrate 10 and the substrate wiring 220P3 of the second substrate 20 are not shown.

Referring to FIG. 3 , a plurality of conductive bridge patterns 160 may be disposed along both edge portions of the second substrate 20 . For this purpose, the first bridge connection pad (i.e., second upper connection pad) 140a-P2 of the first substrate 10 and the second bridge connection pad (i.e., second connection pad) 220P2 of the second substrate 20 ) may be arranged in plural numbers to correspond to each other.

As described above, in the printed circuit boards 1 and 2 according to the embodiments described above with reference to FIGS. 1 to 3, a circuit pattern layer having a cavity 10h and having a first minimum line width is provided. A first substrate 10 is provided. Additionally, a second substrate 20 including a circuit pattern layer having a second minimum line width smaller than the first minimum line width is disposed within the cavity 10h of the first substrate 10. The first substrate 10 and the second substrate 20 may be electrically connected to each other by a conductive bridge pattern 160. As a result, when the device chip 30 having a circuit pattern layer of a fine line width is mounted on the printed circuit board (1, 2), the device chip 30 has a second circuit pattern layer having the second minimum line width. It can be connected to the substrate 20 first. At this time, the second minimum line width of the second substrate 20 may have a size corresponding to the fine line width of the device chip 30. Subsequently, the second substrate 20 may be electrically connected to the first substrate 10 having the circuit pattern layer of the first minimum line width through the conductive bridge pattern 160. As a result, the device chip 30 having the circuit pattern layer of the fine line width can be stably connected to the first substrate 10 having the circuit pattern layer of the relatively large first minimum line width.

4 to 10 are cross-sectional views schematically explaining a method of manufacturing a printed circuit board according to embodiments of the present application.

Referring to FIG. 4, a first substrate 10 having a cavity 10h and a circuit pattern layer having a first minimum line width is prepared. As an example, the first minimum line width may be 10 μm or more.

Specifically, the step of preparing the first substrate 10 of FIG. 4 may proceed as follows. First, prepare the core insulating layer 110. An upper inner layer circuit pattern 120a and a lower inner layer circuit pattern 120b are formed on the upper and lower surfaces of the core insulating layer 110, respectively, by applying a plating method. Specifically, as a method of forming the upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b, a semi-additive process (SAP) or modified semi-additive process (MSAP) method may be applied, as an example. .

Subsequently, an upper interlayer insulating layer 130a and a lower interlayer insulating layer 130b are formed on the upper and lower surfaces of the core insulating layer 110, respectively, to cover the upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b. do. Next, an upper outer layer circuit pattern 140a and a lower outer layer circuit pattern 140b are formed on the upper interlayer insulating layer 130a and the lower interlayer insulating layer 130b, respectively. Next, a cavity 10h is formed that penetrates the upper interlayer insulating layer 130a and the core insulating layer 110 to expose the lower interlayer insulating layer 130b.

Meanwhile, when forming the upper outer layer circuit pattern 140a and the lower outer layer circuit pattern 140b, a via hole is formed through the upper interlayer insulating layer 130a, the core insulating layer 110, and the lower interlayer insulating layer 130b. A first via 180a can be formed inside the via hole. In addition, when forming the upper outer layer circuit pattern 140a and the lower outer layer circuit pattern 140b, the upper interlayer insulating layer 130a and the core insulating layer ( 110) and form a second via 180b inside the via hole. In addition, when forming the upper inner layer circuit pattern 120a and the lower inner layer circuit pattern 120b, the core insulating layer A via hole passing through 110 may be formed, and a third via 180c may be formed inside the via hole.

Referring to FIG. 5, a second substrate 20 having a circuit pattern layer 220 having a second minimum line width smaller than the first minimum line width is prepared. As an example, the second minimum line width may be 5 μm or less.

Specifically, the step of preparing the second substrate 20 of FIG. 5 may proceed as follows. First, a substrate body 210 made of an inorganic material is provided. For example, the inorganic material may be a ceramic material or a semiconductor material. As an example, the substrate body 210 may include at least one of glass, quartz, silicon, silicon oxide, germanium, and group III-V compound semiconductors. For example, the group III-V compound semiconductor may include gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or gallium nitride (GaN).

Next, a conductive layer is formed as a circuit pattern layer 220 on the upper surface 210S of the substrate body 210. The step of forming the conductive layer may use a semiconductor integration process. As an example, the conductive layer may be deposited as a thin film by applying chemical vapor deposition, physical vapor deposition, atomic layer deposition, or plating. In addition, the conductive layer may be patterned by, as an example, a method of forming a photosensitive resist thin film, a method of forming a mask pattern layer through exposure and development of the photosensitive resist thin film, and an etching method using the mask pattern layer. You can.

The step of forming the conductive layer may be specifically carried out as follows. A first connection pad 220P1 is formed at the center of the upper surface 210S of the substrate body 210 as a chip connection pad for connection with the device chip. A second connection pad 220P2 is formed on the edge of the upper surface 210S of the substrate body 210 as a bridge connection pad for connection with the conductive bridge pattern. A substrate wiring 220P3 connecting the first connection pad 220P1 and the second connection pad 220P2 is formed on the upper surface 210S of the substrate body 210.

At this time, the height h1 of the first connection pad 220P1 on the upper surface 210S of the substrate body 210 may be lower than the height h2 of the second connection pad 220P2. Additionally, the first connection pad 220P1 may have a smaller surface area than the second connection pad 220P2 on the top surface 210S of the substrate body 210.

Although not shown in FIG. 5 , in some embodiments, at least one circuit pattern layer may be formed inside the substrate body 210 of the second substrate 20 . The at least one circuit pattern layer may be electrically connected to the conductive layer by a conductive via. That is, at least one circuit pattern layer may be an inner circuit pattern.

Referring to FIG. 6, the second substrate 20 is placed inside the cavity 10h of the first substrate 10. As an example, the second substrate 20 may be bonded to the lower interlayer insulating layer 130b inside the cavity 10h using an adhesive layer 230.

Referring to FIG. 7, the second substrate 20 inside the cavity 10h is filled with an epoxy material 150a, and the upper surface of the first substrate 10 is covered with an epoxy material 150a. Additionally, the lower surface of the first substrate 10 is covered with an epoxy material 150b. Accordingly, passivation layers 150a and 150b made of the applied epoxy materials 150a and 150b may be formed.

In some other embodiments, the passivation layers 150a and 150b may be formed using a photosensitive material instead of the epoxy material 150a. That is, the second substrate 20 inside the cavity 10h is filled with the photosensitive material, and the upper surface of the first substrate 10 is covered with the photosensitive material. Additionally, the lower surface of the first substrate 10 is covered with the photosensitive material. Accordingly, passivation layers 150a and 150b made of the applied photosensitive material can be formed.

Referring to FIG. 8, the passivation layers 150a and 150b are patterned. In one embodiment, when the passivation layers 150a and 150b are made of an epoxy material, a wet etching method using an etching solution may be applied to the patterning. In another embodiment, when the passivation layers 150a and 150b are made of a photosensitive material, the patterning may be performed using a selective exposure and development process for the photosensitive material. Accordingly, the upper outer layer circuit pattern 140a and lower outer layer circuit pattern 140b of the first and second substrates 10 and 20 may be selectively exposed.

Specifically, at least a portion of the upper surface of the first upper connection pad 140a-P1 and the second upper connection pad 140a-P2 is exposed on the first substrate 10. The passivation layer 150a may expose the upper surfaces of the first and second upper connection pads 140a-P1 and 140a-P2 in the form of a contact pattern. In the second substrate 20, the top and side surfaces of a portion of the first connection pad 220P1 and the substrate wiring 220P3 are exposed. Additionally, at least a portion of the upper surface of the second connection pad 220P2 is exposed on the second substrate 20. The passivation layer 150a may expose the upper surface of the second connection pad 220P2 in the form of a contact pattern.

Likewise, at least a portion of the surface of the lower connection pad 140b-P1 may be exposed on the first substrate 10. The passivation layer 150a may expose the surface of the lower connection pad 140b-P1 in the form of a contact pattern.

Referring to FIG. 9, a conductive bridge pattern connecting the second upper connection pad 140a-P2 of the first substrate 10 and the second connection pad 220P2 of the second substrate 20 on the passivation layer 150a. It forms (160).

In one embodiment, the process of forming the conductive bridge pattern 160 is performed by applying a plating method to connect the second upper connection pad 140a-P2 and the second connection pad 220P2 of the second substrate 20. This can be done through the process of forming a pattern layer.

In another embodiment, the process of forming the conductive bridge pattern 160 applies a coating method using a solder material or a conductive paste material to connect the second upper connection pad 140a-P2 and the second substrate 20. The process may proceed to form a conductive pattern layer connecting the connection pad 220P2.

Referring to FIG. 9, after forming the conductive bridge pattern 160, an upper passivation layer 170 may be formed to protect the conductive bridge pattern 160 from the external environment. The upper passivation layer 170 may be formed to selectively cover the conductive bridge pattern 160. The upper passivation layer 170 may include, for example, a solder resist material or an epoxy material. Through the above-described process, a printed circuit board according to an embodiment of the present application can be manufactured.

Meanwhile, according to some embodiments, a device chip 30 having a fine line width may be prepared, and the device chip 30 may be mounted on a printed circuit board. Referring to FIG. 10 , the device chip 30 can be bonded to the first connection pad 220P1 of the second substrate 20 using the connection structure 330 . Accordingly, a printed circuit board according to another embodiment of the present application can be manufactured.

Although the above has been described with reference to the drawings and examples, those skilled in the art may modify and change the embodiments disclosed in the present application in various ways without departing from the technical spirit of the present application as set forth in the claims below. You will understand that you can do it.

1 2: printed circuit board,
10: first substrate, 10h: cavity, 20: second substrate, 30: device chip,
110: core insulating layer, 120a: upper inner layer circuit pattern, 120b: lower inner layer circuit pattern,
130a: upper interlayer insulating layer, 130b: lower interlayer insulating layer,
140a: upper outer layer circuit pattern, 140a-P1: first upper connection pad, 140a-P2: second upper connection pad, 140a-P3: upper outer layer wiring,
140b: lower outer layer circuit pattern, 140b-P1: lower connection pad, 140-P2: lower outer layer wiring,
150a: first upper passivation layer, 150b: first lower passivation layer, 160: conductive bridge pattern, 170: second passivation layer, 180a: first via, 180b: second via, 180c: third via,
210: substrate body, 220: circuit pattern layer, 220P1: first connection pad, 220P2: second connection pad, 220P3: substrate wiring, 230: adhesive layer,
310: chip body, 320P: chip pad, 330: connection structure.

Claims (21)

A first substrate having a cavity and a circuit pattern layer having a first minimum line width;
a second substrate disposed inside the cavity and including a circuit pattern layer having a second minimum line width smaller than the first minimum line width;
a passivation layer that fills the cavity and covers the first and second substrates, the passivation layer selectively exposing the circuit pattern layers of the first and second substrates, respectively; and
A conductive bridge pattern disposed on the passivation layer and electrically connecting the exposed circuit pattern layers of the first and second substrates to each other,
The second substrate includes a substrate body made of an inorganic material,
The circuit pattern layer of the second substrate is
a first connection pad configured to connect to a device chip and disposed at a central portion on the upper surface of the second substrate;
a second connection pad configured to connect to the conductive bridge pattern and disposed on an edge portion of the upper surface of the second substrate; and
Provided with a substrate wiring connecting the first connection pad and the second connection pad,
The height of the first connection pad on the upper surface of the second substrate is lower than the height of the second connection pad.
Printed circuit board.
According to claim 1,
Further comprising a device chip electrically connected to the second substrate and electrically connected to the first substrate through the conductive bridge pattern.
Printed circuit board.
According to claim 1,
The first substrate is
core insulation layer;
an upper inner layer circuit pattern and a lower inner layer circuit pattern respectively disposed on the upper and lower surfaces of the core insulating layer;
an upper interlayer insulating layer and a lower interlayer insulating layer covering the upper inner layer circuit pattern and the lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer, respectively; and
An upper outer layer circuit pattern and a lower outer layer circuit pattern respectively disposed on the upper interlayer insulating layer and the lower interlayer insulating layer,
The cavity penetrates the upper interlayer insulating layer and the core insulating layer to expose the lower interlayer insulating layer,
The upper outer layer circuit pattern includes a first bridge connection pad configured to connect with the conductive bridge pattern.
Printed circuit board.
According to claim 1,
The substrate body made of the inorganic material is
Containing at least one of glass, quartz, silicon, silicon oxide, germanium, and group III-V compound semiconductors
Printed circuit board.
delete According to claim 1,
The first connection pad has a smaller surface area than the second connection pad on the upper surface of the second substrate.
Printed circuit board.
According to claim 1,
The conductive bridge pattern is
comprising at least one selected from the group consisting of a plating material, a solder material, and a conductive paste material.
Printed circuit board.
According to claim 1,
The passivation layer is
Containing epoxy or photosensitive materials
Printed circuit board.
According to claim 1,
The first minimum line width of the first substrate is 10 μm or more,
The second minimum line width of the second substrate is 5 μm or less.
Printed circuit board.
Preparing a first substrate having a cavity and a circuit pattern layer having a first minimum line width;
Preparing a second substrate having a circuit pattern layer having a second minimum line width smaller than the first minimum line width;
Placing the second substrate inside the cavity of the first substrate;
forming a passivation layer that fills the cavity and simultaneously covers the first and second substrates;
Patterning the passivation layer to selectively expose the circuit pattern layers of the first and second substrates, respectively; and
Forming a conductive bridge pattern on the passivation layer to electrically connect the partially exposed circuit pattern layers of the first and second substrates to each other,
The step of preparing the second substrate is
Providing a substrate body made of an inorganic material; and
Including forming a conductive layer on the upper surface of the substrate body,
The step of forming the conductive layer applies at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and plating,
The step of forming the conductive layer is
forming a first connection pad for connection with a device chip on the central portion of the upper surface of the substrate body;
forming a second connection pad for connection to the conductive bridge pattern on an upper edge portion of the substrate body; and
Comprising the step of forming a substrate wiring connecting the first connection pad and the second connection pad on the upper surface of the substrate body,
The height of the first connection pad on the upper surface of the substrate body is formed to be lower than the height of the second connection pad.
Manufacturing method of printed circuit boards.
According to claim 10,
Preparing a device chip;
Further comprising bonding the device chip to the circuit pattern layer of the second substrate using a connection structure.
Manufacturing method of printed circuit boards.
According to claim 10,
The step of preparing the first substrate is
forming an upper inner layer circuit pattern and a lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer, respectively;
forming an upper interlayer insulating layer and a lower interlayer insulating layer respectively covering the upper inner layer circuit pattern and the lower inner layer circuit pattern on the upper and lower surfaces of the core insulating layer;
forming an upper outer layer circuit pattern and a lower outer layer circuit pattern on the upper interlayer insulating layer and the lower interlayer insulating layer, respectively; and
Comprising the step of forming a cavity penetrating the upper interlayer insulating layer and the core insulating layer to expose the lower interlayer insulating layer,
The upper outer layer circuit pattern includes a bridge connection pad configured to connect with the conductive bridge pattern.
Manufacturing method of printed circuit boards.
delete According to claim 10,
The substrate body made of the inorganic material is
Containing at least one of glass, quartz, silicon, silicon oxide, germanium, and group III-V compound semiconductors
Manufacturing method of printed circuit boards.
delete According to claim 10,
The first connection pad has a smaller surface area than the second connection pad on the substrate body.
Manufacturing method of printed circuit boards.
According to claim 10,
The step of forming the passivation layer is
Embedding the second substrate with an epoxy material and covering the upper and lower surfaces of the first substrate with the epoxy material.
Manufacturing method of printed circuit boards.
According to claim 10,
The step of forming the passivation layer is
Burying the second substrate with a photosensitive material and covering the upper and lower surfaces of the first substrate with the photosensitive material.
Manufacturing method of printed circuit boards.
According to claim 10,
The step of selectively exposing the circuit pattern layers of the first and second substrates, respectively,
exposing at least a portion of an upper surface of a connection pad connected to the conductive bridge pattern of the circuit pattern layer of the first substrate;
exposing at least a portion of an upper surface of a connection pad connected to the conductive bridge pattern among the circuit pattern layers of the second substrate; and
Comprising the step of exposing the top and side surfaces of the connection pad disposed on the second substrate and connected to the device chip.
Manufacturing method of printed circuit boards.
According to clause 19,
The step of forming the conductive bridge pattern is
Comprising the step of applying a plating method to form a plating pattern layer connecting the connection pads of the first and second substrates to each other.
Manufacturing method of printed circuit boards.
According to clause 19,
The step of forming the conductive bridge pattern is
Applying a coating method using a solder material or a conductive paste material to form a conductive pattern layer connecting the connection pads of the first and second substrates to each other.
Manufacturing method of printed circuit boards.

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