KR20140025824A - Manufacturing method of electronic chip embedded circuit board - Google Patents

Abstract

A method for manufacturing a circuit board with an embedded chip includes the steps of: preparing a first multilayer substrate; forming a first pattern on the first multilayer substrate; forming an insulation layer to cover the first pattern and a bump hole in a position corresponding to a connection contact of the first pattern; forming a bump in the connection contact; mounting an electronic chip on the first multilayer substrate; preparing a second multilayer substrate; forming a second pattern on the second multilayer substrate; attaching the first multilayer substrate to the second multilayer substrate; forming a via hole in the position of the second multilayer substrate corresponding to the bump; and plating the via hole. [Reference numerals] (AA) Start; (BB) End; (S100) Prepare a first multilayer substrate; (S110) Form a first pattern; (S120) Form a bump hole; (S130) Form a bump; (S140) Mount a chip; (S150) Prepare a second multilayer substrate; (S160) Form a second pattern; (S170) Attach the first multilayer substrate and the second multilayer substrate; (S180) Form a via hole; (S190) Plate the via hole; (S200) Form a third pattern and a fourth pattern

Description

Manufacturing method of electronic chip embedded circuit board {Manufacturing method of electronic chip embedded circuit board}

Embodiments relate to a method of manufacturing a circuit board, and more particularly, to a method of manufacturing a circuit board having an electronic chip capable of forming a fine diameter via hole to implement a circuit pattern having a fine pitch.

In recent years, the size of electronic components has become smaller, and the number of components has increased due to the desire of consumers to prefer one product to have various functions. As the number of components to be mounted on the surface increases while the surface area of the circuit board decreases, components mounted on the surface of the circuit board are often embedded in the substrate.

In particular, when the active element is embedded in the circuit board, the distance between the passive element and the active element is shortened, so that the circuit board can be applied to a package requiring excellent electrical performance. In addition, when the electronic chip is embedded in the circuit board, it is possible to reduce the thickness of the entire circuit board, and to reduce the number of assembly operations required to mount various components on the surface of the circuit board in a small area, and increase the margin for the arrangement of the components. There are advantages such as improved design freedom.

In general, when fabricating a circuit board incorporating an electronic chip, a build-up technique in which a plurality of circuit boards are stacked to form a multilayer circuit board is used. Specifically, the process of laminating a circuit board includes preparing a core layer to which an electronic chip is attached and then attaching the lamination substrate to both surfaces of the core layer. The substrate for lamination is attached to both surfaces of the core layer using an adhesive.

When manufacturing a circuit board incorporating an electronic chip, in addition to forming a laminate by heating and pressing the substrate after laminating the substrate, the wiring of the different layers may be electrically connected or the terminals and wiring of the electronic element embedded in the circuit board may be disconnected. There is a need for electrical connection. The interconnection work, which electrically connects the layers, is a complex process with several steps.

The quality and characteristics of circuit boards incorporating electronic chips are affected by via holes which are processed in the interconnection operation. In the interconnection operation, for example, a drill is used to process via holes, and the via holes are plated to electrically connect the layers.

In a circuit board in which an electronic chip is embedded, the height of the insulating layer is increased to embed the electronic device, and thus, it is difficult to process fine via holes when the layers are electrically connected. As shown in FIG. 4C of US Patent Application Publication No. 2007/0254455, in order to connect a chip embedded in a circuit board with a circuit pattern of another layer, a via hole must be formed by processing a thick insulating layer, so that the size of the via hole is proportional to the size of the insulating layer. It should also increase in size.

Increasing the size of the via hole also causes poor plating properties, making it difficult to form a wiring having a fine pitch. In addition, as the size of the via hole increases, voids (cavities between different materials and materials) are generated inside the via holes, or undercuts (grooves or recesses generated on one side of the conductor pattern by etching) are formed. As a result, the quality of the circuit board is degraded.

United States Patent Application Publication No. 2007/0254455 (2007.11.01)

An object of the embodiments is to provide a method for manufacturing a circuit board containing an electronic device having a fine pitch circuit pattern.

Another object of the embodiments is to provide a method of manufacturing a circuit board incorporating an electronic device having reduced via hole defects and improved product characteristics by enabling a fine sized via hole processing in an interconnection operation for connecting layers.

According to one or more exemplary embodiments, a method of manufacturing a circuit board including an electronic chip includes preparing a first laminated substrate having conductive layers on both sides thereof, forming a first pattern on one surface of the first laminated substrate, and Forming an insulating layer to cover the first pattern and removing the insulating layer at a position corresponding to the connecting contact of the first pattern to form a bump hole, and plating the connecting contact exposed through the bump hole to form a bump. Mounting an electronic chip on one side of the first laminated substrate, preparing a second laminated substrate having a conductive layer on both sides thereof, forming a second pattern on one surface of the second laminated substrate, Attaching the first laminated substrate and the second laminated substrate to face the first pattern and the second pattern; forming a via hole at a position of the second laminated substrate corresponding to the bump; and plating the via hole. do.

The method of manufacturing a circuit board in which an electronic chip is embedded may further include forming a third pattern on the other surface of the second laminated substrate and forming a fourth pattern on the other surface of the first laminated substrate.

The method of manufacturing a circuit board in which an electronic chip is embedded may further include plating a bonding pad to which the electronic chip is connected in the first pattern between forming the first pattern and forming the bump hole. .

The plating of the bonding pad may include forming a first resist on one surface of the first laminated substrate to cover the first pattern except for the bonding pad, and electroless nickel immersion (ENIG) on the surface of the bonding pad. It may include the step of forming a plating layer by gold plating).

In the mounting of the electronic chip, the electronic chip and the plating layer may be connected through the conductive adhesive between the electronic chip and the plating layer of the bonding pad.

The method of manufacturing a circuit board in which an electronic chip is embedded may further include cleaning the surface of the connection contact exposed through the hole for the bump prior to forming the bump.

The forming of the bumps may plate the surface of the connecting contact by electrolytic copper plating.

In the attaching of the first laminated substrate and the second laminated substrate, an adhesive layer may be disposed between the first laminated substrate and the second laminated substrate to attach the first laminated substrate and the second laminated substrate.

The thickness of the bumps may be 80% to 90% of the thickness of the adhesive layer.

In the method of manufacturing a circuit board incorporating an electronic chip according to the above-described embodiments, bumps are formed in a connection connection for interconnecting the layers of the circuit board in advance, so that via holes having a small diameter are formed to form a fine pitch circuit. You can implement patterns.

In addition, even if the thickness of the adhesive layer is increased to accommodate the electronic chip inside the circuit board, bumps are formed in advance, thereby minimizing the thickness to be drilled for the via hole processing in the adhesive layer, thereby improving the quality of the via hole processing and the plating quality of the via holes. have.

1 is a cross-sectional view illustrating a step of preparing a first laminated substrate in a method of manufacturing a circuit board having an electronic chip according to an embodiment.
FIG. 2 is a cross-sectional view illustrating a step of forming a first pattern on one surface of the first laminated substrate of FIG. 1.
3 is a cross-sectional view illustrating a step of forming a first resist on the first pattern of FIG. 2.
4 is a cross-sectional view illustrating a step of plating the bonding pad of FIG. 2.
5 is a cross-sectional view illustrating a state in which a first resist is removed from a first laminated substrate of FIG. 2.
6 is a cross-sectional view illustrating a state in which an insulating layer is formed on one surface of the first laminated substrate of FIG. 5.
7 is a cross-sectional view illustrating an exposure step for forming bump holes in the first laminated substrate of FIG. 6.
8 is a cross-sectional view illustrating a state where a bump hole is completed by the exposure step of FIG. 7.
9 is a cross-sectional view illustrating a step of soft etching the connection contact exposed from the bump hole of FIG. 8.
FIG. 10 is a cross-sectional view illustrating an acid treatment of the connecting contact of FIG. 9.
FIG. 11 is a cross-sectional view illustrating a process of forming a bump in the bump hole of FIG. 9.
12 is a cross-sectional view illustrating a state in which bumps of FIG. 11 are completed.
FIG. 13 is a cross-sectional view illustrating a state in which an insulation layer is removed from FIG. 12.
FIG. 14 is a cross-sectional view illustrating a process of mounting an electronic chip on the first stacked substrate of FIG. 13.
15A is a cross-sectional view illustrating a step of preparing a second laminated substrate.
FIG. 15B is a cross-sectional view illustrating a step of forming a second pattern on the second laminated substrate of FIG. 15A.
15C is a cross-sectional view illustrating a step of attaching the first laminated substrate of FIG. 14 and the second laminated substrate of FIG. 15B.
16 is a cross-sectional view illustrating a step of forming a via hole in the second laminated substrate of FIG. 15C.
17 is a cross-sectional view illustrating a step of plating the via hole of FIG. 16.
FIG. 18 is a cross-sectional view illustrating a step of forming a third pattern on the second laminated substrate of FIG. 17 and forming a fourth pattern on the first laminated substrate.
FIG. 19 is a cross-sectional view illustrating a process of forming a protective layer on a circuit board of FIG. 18.
20 is a flowchart illustrating steps of a method of manufacturing a circuit board incorporating an electronic chip according to the embodiment shown in FIGS. 1 to 19.

Hereinafter, with reference to the embodiments of the accompanying drawings, the configuration and operation of the manufacturing method of the circuit board with the electronic chip according to the embodiments will be described in detail.

1 to 19 are cross-sectional views schematically illustrating a process of each step of a method of manufacturing a circuit board having an electronic chip according to an embodiment, and FIG. 20 is a cross-sectional view of the embodiment shown in FIGS. 1 to 19. It is a flow chart showing the steps of a method of manufacturing a circuit board incorporating an electronic chip.

The method of manufacturing a circuit board in which an electronic chip is embedded according to the embodiment illustrated in FIGS. 1 to 20 includes preparing a first laminated substrate 100 having conductive layers 10 and 30 on both surfaces (S100); Forming a first pattern 31 on one surface of the first laminated substrate 100 (S110), forming a first resist 40 to cover the first pattern 31, and forming a first pattern 31. Removing the insulating layer 60 at positions corresponding to the connection contacts 34 and 35 to form the bump holes 61 and 62 (S120), and the connection contacts exposed by the bump holes 61 and 62. Plating bumps (34, 35) to form bumps (71, 72) (S130), mounting the electronic chip (80) on one surface of the first laminated substrate (100) (S140), and conducting both surfaces. Preparing a second laminated substrate 200 having layers 210 and 230 (S150), forming a second pattern 211 on one surface of the second laminated substrate 200 (S160), and The first laminated substrate 100 and the second red substrate face each other with the first pattern 31 and the second pattern 211 facing each other. Attaching the layer substrate 200 (S170), forming the via holes 238 and 239 at the positions of the second laminated substrates 200 corresponding to the bumps 71 and 72 (S180), and the via holes ( 238 and 239 plating (S190).

1 to 20, in the method of manufacturing a circuit board in which an electronic chip is embedded, the third pattern 231 is formed on the other surface of the second laminated substrate 200, and the first laminated substrate 100 is formed. The method may further include forming a fourth pattern 11 on the other surface of the surface (S200).

1 is a cross-sectional view illustrating a step of preparing a first laminated substrate in a method of manufacturing a circuit board having an electronic chip according to an embodiment.

The first laminated substrate 100 includes a first insulating substrate 20 made of an insulating material and conductive layers 10 and 30 formed on both surfaces of the first insulating substrate 20. In order to fabricate a flexible circuit board, the first insulating substrate 20 may include a material having flexibility such as polyimide resin.

Since the conductive layers 10 and 30 formed on both surfaces of the first insulating substrate 20 form portions of wirings for transmitting electrical signals on the circuit board, the conductive layers 10 and 30 are made of a material having electrical conductivity. For example, the conductive layers 10 and 30 may include copper.

FIG. 2 is a cross-sectional view illustrating a step of forming a first pattern on one surface of the first laminated substrate of FIG. 1.

When the first laminated substrate 100 is prepared, the first pattern 31 is formed on one surface of the first laminated substrate 100. The first pattern 31 performs a function of transmitting a signal from one surface of the first laminated substrate 100.

The first pattern 31 may be formed by a process of removing the conductive layer 30 by etching. That is, after forming a photosensitive resist layer (not shown) on the conductive layer 30, placing a mask (not shown) on it, exposing, developing is performed, and a part of the conductive layer 30 is removed with an etching solution. Through the steps described above, the first pattern 31 may be formed on the first laminated substrate 100.

In forming the first pattern 31 on the first laminated substrate 100, the embodiment is not limited to photolithography as described above. The first pattern 31 may be formed using various methods, such as a plating method and a printing method, since the first pattern 31 may transmit an electrical signal from the completed circuit board.

3 is a cross-sectional view illustrating a step of forming a first resist on the first pattern of FIG. 2, FIG. 4 is a cross-sectional view illustrating a step of plating the bonding pad of FIG. 2, and FIG. 5 is a first laminated substrate of FIG. 2. Is a cross-sectional view showing a state in which the first resist is removed.

Between the step of forming the first pattern 31 and the step of forming the bump holes 61 and 62 to be described below, the bonding pads 32 and 33 are plated as shown in FIGS. 3 to 5. The step may be executed further.

The plating of the bonding pads 32 and 33 may include a first surface on one surface of the first laminated substrate 100 to cover the first pattern 31 except for the bonding pads 32 and 33, as shown in FIG. 3. Forming the resist 40 and plating layers 51 and 52 on the surfaces of the bonding pads 32 and 33 by electroless nickel immersion gold plating (ENIG) as shown in FIG. It may comprise the step of forming. The electroless nickel gold plating method is a method of replacing the Ni layer by electroless plating with Au.

Forming the plating layers 51, 52 on the surfaces of the bonding pads 32, 33 by plating the bonding pads 32, 33 is performed when the bonding pads 32, 33 and the electronic chip 80 are connected (see FIG. 14). ), To achieve good electrical connection performance and mechanical connection performance.

After the plating layers 51 and 52 are formed on the surfaces of the bonding pads 32 and 33, the step of removing all of the first resist 40 from one surface of the first laminated substrate 100 as shown in FIG. 5 is performed. Can be executed.

6 is a cross-sectional view illustrating a state in which an insulating layer is formed on one surface of the first laminated substrate of FIG. 5, and FIG. 7 is a cross-sectional view illustrating an exposure step for forming a bump hole in the first laminated substrate of FIG. 6. 8 is a cross-sectional view illustrating a state where a bump hole is completed by the exposure step of FIG. 7.

Forming the bump hole may include forming an insulating layer 60 on one surface of the first laminated substrate 100 to cover the first pattern 31, as shown in FIG. 6, and FIGS. 7 and FIG. As shown in FIG. 8, the insulating layer 60 is removed at a position corresponding to the connection contacts 34 and 35 of the first pattern 31.

The insulating layer 60 formed on one surface of the first laminated substrate 100 may include a dry film resist (DFR) that is photosensitive. As shown in FIG. 7, a mask 90 having holes 91 and 92 corresponding to the connection contacts 34 and 35 is disposed on the first laminated substrate 100 and exposed using the light source 400. Is carried out. When the exposure is completed, when the exposed portion is removed from the insulating layer 60 by flowing the developer, bump holes 61 and 62 are formed to expose the connection contacts 34 and 35 as shown in FIG. 8.

FIG. 9 is a cross-sectional view illustrating a step of soft etching the connection contact exposed from the bump hole of FIG. 8, and FIG. 10 is a cross-sectional view illustrating an acid treatment of the connection contact of FIG. 9.

After the bump holes 61 and 62 are formed, the surfaces of the connecting contacts 34 and 35 are applied to apply the semi-additive electro Cu plating to the connecting contacts 34 and 35. A cleaning step can be performed. That is, applying soft etching of the connection contacts 34 and 35 as shown in FIG. 9 and acid treating the surfaces of the connection contacts 34 and 35 with 5 to 10% sulfuric acid as shown in FIG. 10. The steps may be executed.

FIG. 11 is a cross-sectional view illustrating a process of forming bumps in the bump hole of FIG. 9, FIG. 12 is a cross-sectional view illustrating a state in which bumps are formed in FIG. 11, and FIG. It is a cross section.

In the step of forming the bumps 71 and 72, the surfaces of the connection contacts 34 and 35 are plated by the electrolytic copper plating method. The electrolytic copper plating method is a method of plating a copper (Cu) particle on the surface of a circuit by flowing an electric current. 11 shows a state in which plating layers 71a and 72a grow on the surfaces of the connection contacts 34 and 35.

When bumps 71 and 72 are formed on the surfaces of the connection contacts 34 and 35 as illustrated in FIG. 12, an insulating layer attached to one surface of the first laminated substrate 100 as illustrated in FIG. 13 ( 60) is executed.

FIG. 14 is a cross-sectional view illustrating a process of mounting an electronic chip on the first stacked substrate of FIG. 13.

After the formation of the bumps 71 and 72 and the removal of the insulating layer 60 are completed, as shown in FIG. 14, the step of mounting the electronic chip 80 to the first stacked substrate 100 is performed. The mounting of the electronic chip 80 can be carried out using, for example, flip chip bonding. An electrically conductive adhesive such as, for example, an anisotropic conductive film (ACF) is disposed between the electrode pads 81 and 82 of the electronic chip 80 and the plating layers 51 and 52 of the bonding pads 32 and 33. By arranging 91 and 92, the electronic chip 80 can be connected to the bonding pads 32 and 33.

An anisotropic conductive film is an adhesive produced in the form of a thin film having a conductive adhesive layer formed by mixing conductive particles in the form of fine particles such as metal coated plastic particles or metal particles, an adhesive, an additive (dispersant) and the like.

15A is a cross-sectional view illustrating a step of preparing a second laminated substrate, and FIG. 15B is a cross-sectional view illustrating a step of forming a second pattern on the second laminated substrate of FIG. 15A.

Like the first laminated substrate 100, the second laminated substrate 200 includes a second insulating substrate 220 made of an insulating material, and conductive layers 210 and 230 formed on both surfaces of the second insulating substrate 220. do. In order to manufacture a flexible circuit board, the second insulating substrate 220 may include a material having flexibility such as polyimide resin.

When the second laminated substrate 200 is prepared, a second pattern 211 is formed on one surface of the second laminated substrate 200. The second pattern 211 performs a function of transmitting a signal from one surface of the second laminated substrate 200. For example, the second pattern 211 may be formed using various methods such as photolithography, plating, or printing.

15C is a cross-sectional view illustrating a step of attaching the first laminated substrate of FIG. 14 and the second laminated substrate of FIG. 15B.

When the second laminated substrate 200 having the second pattern 211 is prepared on one surface, attaching the first laminated substrate 100 and the second laminated substrate 200 is performed.

In the attaching of the first laminated substrate 100 and the second laminated substrate 200, an adhesive layer 240 is disposed between the first laminated substrate 100 and the second laminated substrate 200 to form a first laminated substrate ( 100) and the adhesive layer 240 and the second laminated substrate 200 may be bonded to each other, and the step of applying heat and pressure.

The adhesive layer 240 may use a sheet made of a form in which an adhesive is applied to both sides of an insulating material substrate including a flexible material such as polyimide in order to make the circuit board flexible.

In the attaching of the first laminated substrate 100 and the second laminated substrate 200, a vacuum lamination method or a vacuum hot press method of applying heat in a vacuum state may be used. In the vacuum lamination method or the vacuum hot press method, when the first laminated substrate 100, the adhesive layer 240, and the second laminated substrate 200 are bonded together, the pressure in the space where the bonding is performed is lower than the atmospheric pressure (vacuum pressure). In this way, the air existing between the first laminated substrate 100 and the second laminated substrate 200 is removed and bonded. Using such a vacuum lamination method can reduce the time required for heating and pressurization.

Attaching the first laminated substrate 100 and the second laminated substrate 200 may be performed using, for example, a roll lamination method. That is, each of the first laminated substrate 100, the second laminated substrate 200, and the adhesive layer 240 is supplied to the rolled state, and the first laminated substrate 100 and the second laminated substrate 200 The step of attaching the first laminated substrate 100, the second laminated substrate 200, and the adhesive layer 240 may be performed while continuously supplying the adhesive layer 240.

The thickness t2 of the bumps 71 and 72 may be set to about 80% to 90% of the thickness t1 of the adhesive layer 240. For example, when the thickness t1 of the adhesive layer 240 is 50 μm, the thickness t2 of the bumps 71 and 72 may be 40 to 45 μm.

As such, by adjusting the thickness t2 of the bumps 71 and 72 and the thickness t1 of the adhesive layer 240, the thickness t1 of the adhesive layer 240 is embedded to embed the electronic chip 80 inside the circuit board. Even in the case of increasing the number of via holes, the via holes 238 and 239 to be formed for the interconnection operation (see FIG. 16) may be processed to a fine size.

16 is a cross-sectional view illustrating a step of forming a via hole in the second laminated substrate of FIG. 15C.

The forming of the via holes 238 and 239 may be performed by drilling at the position of the second laminated substrate 200 corresponding to the bumps 71 and 72 to form holes in the second laminated substrate 200 and the adhesive layer 240. Through holes are formed to form via holes 238 and 239. The via holes 238 and 239 are parts for making an electrical connection between the layers of the circuit board or an electrical connection between the terminal and the circuit pattern.

The via holes 238 and 239 may be processed using an ultraviolet laser drill 500 capable of processing holes of minute size. The embodiment is not limited by the processing method of the via holes 238 and 239, and the via holes 238 and 239 may be processed using, for example, a CO ₂ laser drill.

The via holes 238 and 239 do not need to be processed to the entire thickness t1 of the adhesive layer 240, and only the thickness t1 to t2 from the adhesive layer 240 to the top surfaces of the bumps 71 and 72. You can remove it. Therefore, in the present embodiment, via holes 238 and 239 having a fine size may be processed in comparison with the conventional method of forming the via holes by processing the entire thickness t1 of the adhesive layer 240.

17 is a cross-sectional view illustrating a step of plating the via hole of FIG. 16.

After the via holes 238 and 239 are formed, a step of plating the surfaces of the via holes 238 and 239 with a conductive material such as copper is performed. When plating is completed, plating layers 236 and 237 are formed on the surfaces of the via holes 238 and 239.

Since the plating layers 236 and 237 of the via holes 238 and 239 are electrically connected to the connecting contacts 34 and 35 and the bumps 71 and 72 of the first pattern 31 of the first laminated substrate 100, The plating layers 236 and 237 electrically connect the first pattern 31 of the first laminated substrate 100 and the conductive layer 230 on the other surface of the second laminated substrate 200.

FIG. 18 is a cross-sectional view illustrating a process of forming a third pattern on the second stacked substrate of FIG. 17 and forming a fourth pattern on the first stacked substrate, and FIG. 19 illustrates forming a protective layer on the circuit board of FIG. 18. It is sectional drawing shown.

When the plating of the via holes 238 and 239 is completed, the third pattern 231 is formed on the other surface of the second laminated substrate 200, and the fourth pattern 11 is formed on the other surface of the first laminated substrate 100. The steps may be executed.

In the forming of the third pattern 231 on the second laminated substrate 200, the lands 239a and 239b connecting the third pattern 231 and the plating layers 236 and 237 of the via holes 238 and 239 are together. Can be formed. As a result, the first pattern 31 of the first laminated substrate 100 may be stacked on the connecting contacts 34 and 35 via the bumps 71 and 72, the plating layers 236 and 237, and the lands 239a and 239b. It may be electrically connected to the third pattern 231 of the substrate 200.

After the third pattern 231 and the fourth pattern 11 are formed, the protective layers 251 and 252 which cover and protect the surfaces of the third pattern 231 and the fourth pattern 11 are formed on the first laminated substrate ( 100) and the second laminated substrate 200 may be formed.

Process diagram for forming the protective layers 251 and 252 After the dry film resist (DFR) is laminated on the other surface of the first laminated substrate 100 and the other surface of the second laminated substrate 200, exposure, development, etching, Steps such as peeling, auto optical inspection, and the like.

As described above, the thickness t2 of the bumps 71 and 72 is set to about 80% to 90% of the thickness t1 of the adhesive layer 240 to thereby embed the electronic chip 80 inside the circuit board. Even when the thickness t1 of the adhesive layer 240 is increased, the via holes 238 and 239 to be formed for the interconnection operation may be processed to a fine size.

A general via hole land for a circuit board has a width of 350 mu m, but in a fine pitch circuit wiring, the width of the via hole land should be 200 mu m or less. In this embodiment, since the via holes 238 and 239 are processed to a fine size, the sizes of the lands 239a and 239b connected to the third pattern 231 of the second laminated substrate 200 may also be processed to a fine size. It can correspond to the circuit wiring of minute pitch.

In addition, the quality ratio of copper plating of the via hole is that the aspect ratio (AR) is determined by the height of the insulating layer / the size of the via hole.In general, when AR> 1, the probability of defects such as voids or undercuts in the via hole is generated. Is higher.

However, as described above, in the present embodiment, bumps 71 and 72 are formed in advance in the connection contacts 34 and 35 for interconnecting the layers of the circuit board, so that the adhesive layers 240 are formed to form the via holes 238 and 239. Since the thickness of the perforations can be minimized, the occurrence of defects in the via holes 238 and 239 can be reduced, and the via holes 238 and 239 having the fine diameter can be formed to correspond to the circuit pattern having a fine pitch.

The use of all examples or exemplary language (e.g., etc.) in this invention is for the purpose of describing the invention in detail and is not to be construed as a limitation on the scope of the invention, It is not. It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the invention.

10, 30: conductive layer 91, 92: hole
11: fourth pattern 100: first laminated substrate
20: first insulating substrate 200: second laminated substrate
30: conductive layer 210, 230: conductive layer
31: first pattern 211: second pattern
32 and 33: bonding pads 220: second insulating substrate
34, 35: connection contact 230: conductive layer
40: first resist 236, 237: plating layer
51, 52: plating layer 238, 239: via hole
61, 62: bump hole 231: third pattern
71, 72: bumps 239a, 239b: land
71a, 72a: plating layer 240: adhesive layer
60: insulating layer 251, 252: protective layer
80: electronic chip 400: light source
81, 82: electrode pad 500: drill
90: mask

Claims (9)

Preparing a first laminated substrate having conductive layers on both sides;
Forming a first pattern on one surface of the first laminated substrate;
Forming an insulating layer covering the first pattern and removing the insulating layer at a position corresponding to the connection contact of the first pattern to form a bump hole;
Plating the connection contacts exposed by the bump holes to form bumps;
Mounting an electronic chip on the one surface of the first laminated substrate;
Preparing a second laminated substrate having conductive layers on both sides;
Forming a second pattern on one surface of the second laminated substrate;
Attaching the first laminated substrate and the second laminated substrate to face the first pattern and the second pattern;
Forming a via hole at a position of the second laminated substrate corresponding to the bump; And
Plating the via hole; a method for manufacturing a circuit board having an electronic chip embedded therein. The method of claim 1,
Forming a third pattern on the other surface of the second laminated substrate, and forming a fourth pattern on the other surface of the first laminated substrate, the manufacturing method of a circuit board with an electronic chip embedded. The method of claim 1,
Between the forming of the first pattern and the forming of the bump hole, plating a bonding pad to which the electronic chip is to be connected in the first pattern. Manufacturing method. The method of claim 3,
The plating of the bonding pad may include forming a first resist on the surface of the first laminated substrate to cover the first pattern except for the bonding pad, and electroless nickel gold plating on the surface of the bonding pad. (ENIG; electroless nickel immersion gold plating) comprising the step of forming a plating layer, a method for manufacturing a circuit board with an embedded electronic chip. 5. The method of claim 4,
The mounting of the electronic chip may include connecting the electronic chip and the plating layer through a conductive adhesive between the electronic chip and the plating layer of the bonding pad. The method of claim 1,
And cleaning the surface of the connection contact exposed to the holes for the bumps prior to forming the bumps. The method of claim 1,
The forming of the bumps may include plating the surface of the connection contact by an electrolytic copper plating method. The method of claim 1,
The attaching the first laminated substrate and the second laminated substrate may include attaching the first laminated substrate and the second laminated substrate by disposing an adhesive layer between the first laminated substrate and the second laminated substrate. Method for manufacturing a circuit board in which a chip is embedded. 9. The method of claim 8,
The thickness of the bump is 80% to 90% of the thickness of the adhesive layer, a method of manufacturing a circuit board with an embedded electronic chip.

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