CN108242434B - Substrate structure and manufacturing method thereof - Google Patents
Substrate structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN108242434B CN108242434B CN201611203493.4A CN201611203493A CN108242434B CN 108242434 B CN108242434 B CN 108242434B CN 201611203493 A CN201611203493 A CN 201611203493A CN 108242434 B CN108242434 B CN 108242434B
- Authority
- CN
- China
- Prior art keywords
- metal carrier
- carrier plate
- substrate structure
- groove
- dielectric material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a substrate structure and a manufacturing method thereof, wherein the substrate structure comprises: a metal carrier, a dielectric material and a patterned conductive layer. The metal carrier has a first surface, a second surface opposite to the first surface, and a plurality of through grooves communicating the first surface and the second surface. The dielectric material fills the through groove and forms a layer-adding part on the first surface of the metal carrier plate, and the layer-adding part is provided with a plurality of through holes. The patterned conductor layer is positioned on the surface of the reinforced part and partially extends into the through hole to form a line wiring. The invention also discloses a manufacturing method of the substrate structure.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to a substrate structure used in a quad flat no-lead (QFN) package structure and a method for manufacturing the same.
Background
With the rapid expansion of various electronic products in accordance with the demand for convenience of life, the Integrated circuit packaging technology, which is the most important part in the electronic product assembly technology, is also eagerly developed in various aspects such as high-speed processing, multi-functionalization, integration (Integrated), and miniaturization and high-density in response to the demand. In the current semiconductor package technology, on the package with low or medium pin count, the QFN package structure has a plurality of advantages such as reduced pin inductance (inductance), small pin (footprint), thinner profile and faster signal transmission speed, because the QFN package structure does not have the pin shape (QFN) extending to the outside of the encapsulant.
However, in the case of the QFN package structure, the chip pad and the contact terminals (pin pads) surrounding the chip pad are formed by a sheet-shaped lead frame structure, and the number of input/output (I/O) terminals is small, and the I/O connections of the same network between chips need to be additionally connected by a lead frame or metal wires. Therefore, another quad flat no-lead (a-QFN) structure is derived, as shown in fig. 1, the a-QFN structure 10 is fabricated by first etching the upper surface of the metal carrier 12 to form a plurality of grooves 14 to define a die pad 16 and a plurality of inner leads 18. Then, the chip 20 is placed and a metal wire bonding process between the chip 20 and the inner leads 18 is performed. Then, the chip 20 and the metal wire bonding package are packaged by using the encapsulant 22, and the encapsulant 22 is filled into the groove 14. Then, the lower surface of the metal carrier 12 is etched for the second time to form a plurality of grooves 15, so as to define outer leads 24 exposed outside the encapsulant 22. However, since the encapsulant 22 and the metal carrier 12 are made of heterogeneous materials, a small gap exists between the encapsulant 22 and the metal carrier due to repulsion. Therefore, when the second etching process is performed, during the process of forming the recess 15, the etching solution may contact the gap (or the connection portion) between the metal carrier 12 and the filling recess 14, which results in an increased gap, so that the pin pads or the contact terminals 26 are easily loosened or even dropped due to insufficient bonding force with the encapsulant 22.
Therefore, the present invention provides a novel substrate structure and a method for manufacturing the same.
Disclosure of Invention
The present invention is directed to a substrate structure and a method for manufacturing the same, in which a contact terminal and a dielectric material have a strong bonding force therebetween and are not easily released or dropped.
Another objective of the present invention is to provide a substrate structure and a method for manufacturing the same, wherein a double-sided synchronous etching method is adopted to form a through-groove with double-arc sidewalls on a metal carrier, and the double-arc sidewalls are further utilized to increase the adhesion between a dielectric material filled in the through-groove and the metal carrier while eliminating re-erosion of the etching solution.
Another objective of the present invention is to provide a substrate structure and a method for manufacturing the same, which can redistribute the lines, increase the wiring area, and further allow the I/O to be directly connected to each other without an external lead frame or gold wire, and achieve the requirement of double-sided or 3D-sided conduction by the contact terminal.
Another object of the present invention is to provide a substrate structure and a method for manufacturing the same, which has high heat dissipation, high rigidity and electromagnetic shielding properties and can directly transmit signals through a metal carrier.
It is another objective of the present invention to provide a substrate structure and a method for manufacturing the same, which can design and control circuits such as resistors and impedances according to electrical requirements of products.
To achieve the above object, the present invention provides a substrate structure, which mainly comprises: a metal carrier, a dielectric material and a patterned conductive layer. The metal carrier plate is provided with a first surface, a second surface opposite to the first surface and a plurality of through grooves communicated with the first surface and the second surface, and one side wall surface of each through groove is nonlinear. The dielectric material fills the through groove and forms a build-up part on the first surface of the metal carrier, and the build-up part is provided with a plurality of through holes. The patterned conductor layer is located on one surface of the enhanced part and partially extends into the through hole to form a line wiring.
Wherein, the material of the metal carrier plate is a composite material.
Wherein, at least one chip is arranged on part of the patterned conductor layer.
Wherein, a bonding material is arranged between the chip and the dielectric material and the patterned conductor layer.
Wherein the dielectric material is a molding material.
Wherein, the side wall surface of the through grooves is in a double arc shape or a wave shape.
In addition, to achieve the above object, the present invention provides a method for manufacturing a substrate structure, which includes providing a metal carrier having a first surface and a second surface opposite to the first surface; etching the metal carrier plate from the first surface and the second surface to form a plurality of through grooves communicating the first surface and the second surface, wherein the surface of one side wall of each through groove is nonlinear; then, arranging a temporary carrier plate on the second surface of the metal carrier plate; then, a dielectric material is arranged to fill the through groove and coat the first surface of the metal carrier plate, and a reinforced part is formed on the first surface; forming at least one through hole on the reinforced part to expose part of the first surface; then, forming a patterned conductor layer on a surface of the layer-adding part, which is far away from the first surface of the metal carrier plate, wherein part of the patterned conductor layer is filled in the through hole; and removing the temporary carrier plate.
Wherein, the metal carrier plate is made of a composite material.
Wherein the step of providing the dielectric material further comprises:
providing a molding material;
heating the molding material to a fluid state;
injecting the die casting material in a fluid state to fill the through groove and coat the first surface of the metal carrier plate; and
curing the molding material in a fluid state.
Wherein, the side wall surface of the through grooves is in a double arc shape or a wave shape.
The invention has the beneficial effects that: the substrate structure of the invention forms a plurality of contact terminals on the metal carrier plate under the condition of keeping the rigidity of the metal carrier plate, so that the substrate has better flatness and heat dissipation performance, and can be provided with circuit wiring through the layer increasing part, for example, the circuit wiring is arranged right below a chip, thereby achieving the purpose of fully utilizing the area of a product. Moreover, the signal can be transmitted to the back surface (the second surface side) or the side surface of the substrate structure through the contact terminal made of the metal material, so that the requirement of double-sided or 3D side surface conduction is met.
Drawings
Fig. 1 is a schematic structural diagram of a conventional metal substrate;
FIG. 2 is a schematic diagram of a substrate structure according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of an application of the substrate structure according to the preferred embodiment of the invention;
fig. 4 a-4 f are schematic views illustrating steps of the method for manufacturing the substrate structure shown in fig. 2.
Description of the reference numerals
(Prior Art)
10 a-QFN structure
12 metal carrier plate
14 groove
15 groove
16 chip holder
18 inner pin
20 chip
22 packaging adhesive
24 outer pin
26 contact terminal
(present invention)
30 substrate structure
32 metal carrier plate
322 first surface
324 second surface
326 through groove
3261 sidewall surface
328 contact terminal
329a center layer
329b cladding layer
34 dielectric material
342 layer-adding part
344 through the hole
36 patterned conductor layer
38 bump
39 bonding material
40 first chip
42 second chip
44 temporary carrier plate
W1 peak
W2 trough.
Detailed Description
This summary is explained below by way of examples, which are not intended to limit the invention to any particular environment, application, or particular manner in which the invention may be practiced as described in the examples. Therefore, the description of the embodiments is for the purpose of illustration only, and not for the purpose of limitation. It should be noted that, in the following embodiments and the accompanying drawings, components which are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the various elements in the drawings are for ease of understanding only and are not intended to be limiting in nature. In the following embodiments, the same components will be described with the same reference numerals.
The present invention relates to a substrate structure and a method for manufacturing the same, and more particularly, to a substrate structure and a method for manufacturing the same, in which contact terminals as inner and outer leads are manufactured by using a metal carrier, and a build-up portion is formed on the metal carrier by using a dielectric material to perform circuit wiring again. The line width and line distance can be reduced by performing photolithography and etching during the wiring process, thereby greatly increasing the I/O number of the product. In addition, the network I/O can be directly connected by the integrated design of line wiring without conducting by a metal wire or a lead frame additionally.
Fig. 2 is a schematic view of a substrate structure 30 according to a first embodiment of the present invention based on the above-described architecture. As shown, the substrate structure 30 includes: a metal carrier 32, a dielectric material 34 and a patterned conductive layer 36.
The metal carrier 32 has a first surface 322, a second surface 324 and a plurality of through grooves 326. The first surface 322 and the second surface 324 are disposed on two opposite sides of the metal carrier 32. The through grooves 326 are connected between the first surface 322 and the second surface 324, in other words, the through grooves 326 are through holes of the metal carrier 32, which can divide the metal carrier 32 into a plurality of contact terminals (inner and outer leads) 328. A sidewall surface 3261 of the through groove 326 is non-linear, e.g., double curved or wavy, or irregular. For example, as shown in fig. 2, the sidewall surface 3261 of the through groove 326 has at least one peak W1 and two valleys W2 to form a double arc shape, which will be described later in the specification.
The metal carrier 32 may be made of a single metal material, and the material thereof may be selected from stainless steel, aluminum or copper. Alternatively, as shown in the present embodiment, the metal carrier 32 is made of a composite material. The composite material may be an alloy made of mixed or melted metals or a material stacked in a metal lamination manner, so as to optimize the conductive characteristics of the metal carrier 32 or protect the metal carrier 32 from corrosion. In the embodiment, taking a metal lamination manner as an example, the metal carrier 32 may be made of a central layer 329a and covering layers 329b on two sides of the central layer 329 a. The material of the central layer 329a is stainless steel, for example, and the material of the covering layer 329b is copper, for example, however, the material is only for illustration and is not intended to limit the present invention.
The dielectric material 34 fills the through-groove 326 and forms a reinforced portion 342 on the first surface 322 of the metal carrier 32. The build-up portion 342 has a plurality of perforations 344 to expose a portion of the first surface 322. The dielectric material 34 may be a Molding material, for example, a Molding Compound (Molding Compound) for chip packaging such as, but not limited to, a phenolic-Based Resin (Novolac-Based Resin), an Epoxy-Based Resin (Epoxy-Based Resin), a silicon-Based Resin (Silicone-Based Resin), or other suitable Molding Compound, and the Molding Compound may also contain a suitable filler such as powdered silica.
In the present embodiment, since the sidewall surface 3261 of the through groove 326 of the metal carrier 32 is shaped like a double arc, the adhesion between the dielectric material 34 filled in the through groove 326 and the metal carrier 32 can be improved, i.e. the adhesion between the contact terminal 328 and the dielectric material 34 can be increased.
The patterned conductive layer 36 is disposed on a surface of the enhanced portion 342 away from the first surface 322 of the metal carrier 32 and partially extends into the through hole 344 to form a Circuit layout (Circuit layout) or an electrical connection pad. In the present embodiment, the material of the patterned conductive layer 36 is a metal, such as but not limited to copper, iron, silver, nickel, and a combination thereof.
The substrate structure 30 may be applied to dispose at least one chip (chip) or die on the metal carrier 32. For example, as shown in fig. 3, at least one bump 38 may be disposed on a portion of the patterned conductive layer 36 serving as an electrical connection pad. The patterned conductive layer 36 is electrically connected to a first chip 40 via bumps 38. In the present embodiment, a bonding material 39 may be further disposed between the first chip 40 and the dielectric material 34 and the patterned conductive layer 36, which can enhance the bonding stability between the first chip 40 and the patterned conductive layer 36 and the dielectric material 34, and prevent conductive foreign matters from entering the position to cause short circuit. In addition, a second chip 42 can be disposed on the first chip 40 and electrically connected to a portion of the patterned conductive layer 36 serving as an electrical connection pad by metal wire bonding. Finally, a packaging material (not shown) may be further disposed to encapsulate the first chip 40 and the second chip 42, so as to form a package structure.
In view of the above, the substrate structure of the present invention forms a plurality of contact terminals on the metal carrier while maintaining the rigidity of the metal carrier, so that the substrate has good flatness and heat dissipation, and can be provided with circuit wiring by the build-up portion, for example, the circuit wiring is disposed right under the chip, so as to achieve the purpose of fully utilizing the product area. Moreover, the signal can be transmitted to the back surface (the second surface side) or the side surface of the substrate structure through the contact terminal made of the metal material, so that the requirement of double-sided or 3D side surface conduction is met.
Please refer to fig. 4a to 4f, which are schematic views illustrating steps of a method for fabricating a substrate structure according to the present invention. First, as shown in fig. 4a, a metal carrier 32 is provided, wherein the metal carrier 32 has a first surface 322 and a second surface 324 corresponding to the first surface 322. Next, the metal carrier 32 is etched from the first surface 322 and the second surface 324 at the same time to form a plurality of through grooves 326 connecting the first surface 322 and the second surface 324, so as to define a plurality of contact terminals 328 on the metal carrier 32. At this time, because the two-sided etching is performed synchronously, the adverse effect of re-etching between the filling material filled in the through groove (groove) and the groove wall when the etching solution is used again for groove etching in the prior art can be effectively eliminated. Moreover, the synchronous double-sided etching method used in the present invention can form a non-linear surface, such as a double arc or a wave, on the sidewall surface 3261 of the through-groove 326, so as to increase the adhesion between the dielectric material 34 and the metal carrier 32 filled in the through-groove 326, that is, the adhesion between the contact terminal 26 and the dielectric material 34.
Next, as shown in fig. 4b, a temporary carrier 44 is disposed on the second surface 324 of the metal carrier 32. Then, as shown in fig. 4c, a dielectric material 34 is disposed on the first surface 322 of the metal carrier 32, for example, the dielectric material 34 is disposed on the first surface 322 of the metal carrier 32 by a die casting method, the through groove 326 is filled with the dielectric material 34, and a reinforced portion 342 is formed on the first surface 322 of the metal carrier 32. Among them, the molding manner is exemplified as follows: firstly, providing a die casting material; then, heating the molding material to a fluid state; then, injecting a molding material in a fluid state to fill the through-grooves 326 and cover the first surface 322 of the metal carrier 32 at high temperature and high pressure; finally, the molding material in a fluid state is cured to form the dielectric material 34 having the thickened portion 342. The term "filled" means that the dielectric material 34 substantially filled in the through-grooves 326 is almost flush with the second surface 324 of the metal carrier 32 at the end of the second surface 324 of the metal carrier 32, and also at the end of the first surface 322 of the metal carrier 32.
Then, as shown in fig. 4d, at least one through hole 344 is formed on the build-up portion 342, and the through hole 344 exposes the metal carrier 32. As shown in fig. 4e, a patterned conductive layer 36 is formed on the surface of the build-up portion 342 to serve as a wiring. In the present embodiment, a portion of the patterned conductor layer 36 is filled in the through hole 344, a portion of the patterned conductor layer 36 is used as a conductive trace, and a portion of the patterned conductor layer 36 is used as an electrical connection pad. Finally, the metal carrier 32 is Singulated (Singulated) or as shown in fig. 4f, the temporary carrier 44 is removed, so as to obtain the substrate structure 30 of the present invention. After removing the temporary carrier 44, the second surface 324 of the metal carrier 32 is exposed for subsequent electrical connection.
The through holes 344 and the patterned conductive layer 36 may be formed by photolithography to reduce the line-to-line spacing and increase the I/O number of the product network. The network I/O can be directly connected through the patterned conductive layer 36 (e.g., copper wire) without additional conduction with gold wire or lead frame. Furthermore, the patterned conductive layer 36 can be designed and controlled for circuit layout such as resistance and impedance according to the electrical requirements of the product.
In summary, the present invention provides a novel substrate structure and a method for manufacturing the same, which not only has the advantages of rigidity of a metal carrier, but also utilizes a double-sided synchronous etching method to avoid bad structural stability of a contact terminal caused by multiple etching, and utilizes a build-up portion to provide a circuit wiring for directly connecting to a network I/O, without additional metal or lead frame, and can effectively utilize the position under a chip to fully utilize the product area.
The invention accords with the application elements of the invention patent, and the patent application is proposed by the particular law. However, the above description is only a preferred embodiment of the present invention, and the claimed invention should not be limited thereby. All equivalent modifications or changes which may be made by those skilled in the art according to the spirit of the present invention are intended to be within the scope of the appended claims.
Claims (4)
1. A method for manufacturing a substrate structure, comprising the steps of:
providing a metal carrier plate, wherein the metal carrier plate is provided with a first surface and a second surface which are oppositely arranged;
etching the metal carrier plate from the first surface and the second surface to form a plurality of through grooves communicating the first surface and the second surface, wherein a side wall surface of each through groove is nonlinear;
arranging a temporary carrier plate on the second surface of the metal carrier plate;
arranging a dielectric material to fill the through groove and coat the first surface of the metal carrier plate, and forming a reinforced part on the first surface;
forming at least one through hole on the reinforced part to expose part of the first surface;
forming a patterned conductor layer on a surface of the build-up portion away from the first surface of the metal carrier, wherein a portion of the patterned conductor layer is filled in the through hole; and
removing the temporary carrier.
2. The method of claim 1, wherein the metal carrier is made of a composite material.
3. The method of claim 1, wherein disposing the dielectric material further comprises:
providing a molding material;
heating the molding material to a fluid state;
injecting the die casting material in a fluid state to fill the through groove and coat the first surface of the metal carrier plate; and
curing the molding material in a fluid state.
4. The method of claim 1, wherein the sidewall surfaces of the through-grooves are in a double arc shape or a wave shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611203493.4A CN108242434B (en) | 2016-12-23 | 2016-12-23 | Substrate structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611203493.4A CN108242434B (en) | 2016-12-23 | 2016-12-23 | Substrate structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108242434A CN108242434A (en) | 2018-07-03 |
| CN108242434B true CN108242434B (en) | 2021-04-02 |
Family
ID=62703305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611203493.4A Active CN108242434B (en) | 2016-12-23 | 2016-12-23 | Substrate structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108242434B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729252B (en) * | 2019-10-31 | 2021-12-24 | 中国电子科技集团公司第十三研究所 | 0.4mm pitch ceramic quad flat package |
| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104039070A (en) * | 2013-03-07 | 2014-09-10 | 钰桥半导体股份有限公司 | Thermally enhanced wiring board with built-in heat sink and build-up circuitry |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101204092B1 (en) * | 2008-05-16 | 2012-11-22 | 삼성테크윈 주식회사 | Lead frame and semiconductor package and the manufacturing method for the same |
| US9576873B2 (en) * | 2011-12-14 | 2017-02-21 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with routable trace and method of manufacture thereof |
-
2016
- 2016-12-23 CN CN201611203493.4A patent/CN108242434B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104039070A (en) * | 2013-03-07 | 2014-09-10 | 钰桥半导体股份有限公司 | Thermally enhanced wiring board with built-in heat sink and build-up circuitry |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108242434A (en) | 2018-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9130064B2 (en) | Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier | |
| US8420452B2 (en) | Fabrication method of leadframe-based semiconductor package | |
| CN105826209B (en) | Packaging structure and manufacturing method thereof | |
| CN211150513U (en) | Package body | |
| KR101809521B1 (en) | Semiconductor package and method of manufacturing the same | |
| US6242797B1 (en) | Semiconductor device having pellet mounted on radiating plate thereof | |
| CN108242434B (en) | Substrate structure and manufacturing method thereof | |
| US20100295160A1 (en) | Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof | |
| US20090206459A1 (en) | Quad flat non-leaded package structure | |
| KR101474189B1 (en) | Integrated circuit package | |
| CN113540056A (en) | Semiconductor module and method for manufacturing the same | |
| EP2068361A1 (en) | Packaging substrate having chip embedded therein and manufacturing method thereof | |
| US10978374B2 (en) | Semiconductor package for discharging heat generated by semiconductor chip | |
| KR101685068B1 (en) | System in package and method for manufacturing the same | |
| TWI757133B (en) | Quad flat no-lead package structure | |
| CN106847778B (en) | Semiconductor package carrier and manufacturing method thereof | |
| CN210575932U (en) | Lead frame and packaging structure | |
| CN113257688A (en) | Chip packaging method and chip packaging structure | |
| JP6210533B2 (en) | Printed circuit board and manufacturing method thereof | |
| TWI604585B (en) | Manufacturing method of ic carrier | |
| KR0127737B1 (en) | Semiconductor package | |
| JP2011176263A (en) | Chip-scale semiconductor device package and method of manufacturing the same | |
| TW201036113A (en) | Substrateless chip package and fabricating method | |
| WO2007143730A2 (en) | Semiconductor device with high current performance packaging | |
| CN103824820A (en) | Leadframe area array packaging technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |