CN106548947A - 封装结构及其形成方法 - Google Patents
封装结构及其形成方法 Download PDFInfo
- Publication number
- CN106548947A CN106548947A CN201610677405.8A CN201610677405A CN106548947A CN 106548947 A CN106548947 A CN 106548947A CN 201610677405 A CN201610677405 A CN 201610677405A CN 106548947 A CN106548947 A CN 106548947A
- Authority
- CN
- China
- Prior art keywords
- substrate
- packaging part
- sensor
- recess
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 154
- 238000004806 packaging method and process Methods 0.000 claims abstract description 143
- 239000000565 sealant Substances 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 239000008280 blood Substances 0.000 claims description 6
- 210000004369 blood Anatomy 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 3
- 238000012806 monitoring device Methods 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 58
- 229920002120 photoresistant polymer Polymers 0.000 description 47
- 239000011162 core material Substances 0.000 description 44
- 238000001465 metallisation Methods 0.000 description 44
- 239000004020 conductor Substances 0.000 description 35
- 239000000463 material Substances 0.000 description 30
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 238000007747 plating Methods 0.000 description 21
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 19
- 239000010936 titanium Substances 0.000 description 19
- 229910052719 titanium Inorganic materials 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 18
- 238000000059 patterning Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000004528 spin coating Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 239000004411 aluminium Substances 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 8
- 239000005388 borosilicate glass Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 239000005360 phosphosilicate glass Substances 0.000 description 8
- 229920002577 polybenzoxazole Polymers 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000004380 ashing Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- -1 silicon nitride) Chemical class 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000006386 neutralization reaction Methods 0.000 description 5
- WQZGKKKJIJFFOK-GASJEMHNSA-N Glucose Natural products OC[C@H]1OC(O)[C@H](O)[C@@H](O)[C@@H]1O WQZGKKKJIJFFOK-GASJEMHNSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000008103 glucose Substances 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000002305 electric material Substances 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 239000000206 moulding compound Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000005619 thermoelectricity Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1437—Static random-access memory [SRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明描述了封装结构和形成封装结构的方法。一种方法包括在第一衬底的凹部中放置第一封装件。第一封装件包括第一管芯。该方法还包括将第一传感器附接至第一封装件和第一衬底。第一传感器电耦合至第一封装件和第一衬底。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及封装结构及其形成方法。
背景技术
半导体器件被用于各种电子应用,诸如个人计算机、蜂窝电话、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件:在半导体衬底上方顺序沉积绝缘层或介电层、导电层和半导体材料层,并且使用光刻图案化各个材料层以在其上形成电路部件和元件。通常在单个半导体晶圆上制造几十个或几百个集成电路。通过沿着划线锯切集成电路来分割各个管芯。然后,例如在多芯片模块中或者在其他类型的封装中单独地封装各个管芯。
半导体工业持续通过最小部件尺寸的连续缩小而提高各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这允许更多的部件被集成到给定区域中。在一些应用中,这些更小的电子部件(诸如集成电路管芯)也可要求更小的封装件,其使用比过去的封装件更小的面积。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种方法,包括:将第一封装件放置在第一衬底的凹部内,所述第一封装件包括第一管芯;以及将第一传感器附接至所述第一封装件和所述第一衬底,所述第一传感器电耦合至所述第一封装件和所述第一衬底。
在该方法中,所述第一传感器包括心率监控器、环境光传感器、紫外光传感器、室温传感器、加速计、陀螺仪、磁力计、大气压力传感器、血氧传感器、全球定位系统(GPS)传感器、皮肤传导传感器、皮肤温度传感器、血糖监控器等或它们的组合。
该方法还包括:在所述第一衬底的凹部中形成第一接合焊盘,所述第一封装件通过第一导电连接件电耦合至所述第一衬底的所述第一接合焊盘。
该方法还包括:在所述第一衬底的第一表面上形成第二接合焊盘,所述第一表面位于所述第一衬底的凹部之外,所述第一封装件通过第二导电连接件电耦合至所述第一衬底的所述第二接合焊盘。
该方法还包括:将第二传感器附接至所述第一封装件,所述第二传感器电耦合至所述第一封装件。
该方法还包括:将第三传感器附接至所述第一封装件和所述第一衬底,所述第三传感器电耦合至所述第一封装件和所述第一衬底。
该方法还包括:形成所述第一封装件,形成所述第一封装件包括:利用密封剂至少横向地密封所述第一管芯;以及在所述第一管芯和所述密封剂上方形成第一再分布结构,所述第一传感器电耦合至所述第一再分布结构。
该方法还包括:在所述第一衬底的凹部中形成第三接合焊盘;以及形成所述第一封装件还包括:形成从所述第一再分布结构延伸穿过所述密封剂到达所述第一管芯的背侧的通孔,所述第一管芯的有源侧耦合至所述第一再分布结构,所述有源侧与所述背侧相对,所述第一封装件的所述通孔利用第一导电连接件电耦合至所述第一衬底的第三接合焊盘。
该方法还包括:将热电发电机附接至所述第一封装件和所述第一衬底,所述热电发电机电耦合至所述第一封装件。
该方法还包括:形成所述第一封装件,形成所述第一封装件包括:利用密封剂至少横向密封所述第一管芯和第二管芯;以及在所述第一管芯、所述第二管芯和所述密封剂上方形成第一再分布结构,所述第一传感器电耦合至所述第一再分布结构。
根据本发明的另一方,提供了一种方法,包括:形成第一封装件,形成所述第一封装件包括:利用密封剂至少横向地密封第一管芯,所述第一管芯具有有源侧和背侧,所述有源侧和所述背侧相对;和在所述第一管芯和所述密封剂上方形成第一再分布结构,所述第一再分布结构耦合至所述第一管芯的有源侧;将所述第一封装件耦合至第一衬底,所述第一封装件的至少一部分在所述第一衬底的凹部内延伸;以及将第一传感器接合至所述第一封装件和所述第一衬底,所述第一传感器电耦合至所述第一封装件和所述第一衬底。
在该方法中,所述第一传感器包括心率监控器、环境光传感器、紫外光传感器、室温传感器、加速计、陀螺仪、磁力计、大气压力传感器、血氧传感器、全球定位系统(GPS)传感器、皮肤传导传感器、皮肤温度传感器、血糖监控器等或它们的组合。
在该方法中,形成所述第一封装件还包括:形成从所述第一再分布结构延伸穿过所述密封剂到达所述第一管芯的背侧的层级的通孔。
该方法还包括:在所述第一衬底的所述凹部中形成第一接合焊盘,所述第一封装件的所述通孔利用第一导电连接件电耦合至所述第一衬底的所述第一接合焊盘。
该方法还包括:将第二传感器接合至所述第一封装件,所述第二传感器电耦合至所述第一封装件。
在该方法中,所述第一传感器包括直接位于所述第一衬底的所述凹部上方的第一部分以及直接位于所述第一衬底的所述凹部之外的部分上方的第二部分,并且所述第二传感器仅直接位于所述第一衬底的所述凹部上方。
该方法还包括:将第三传感器接合至所述第一封装件,所述第三传感器电耦合至所述第一封装件;以及将第四传感器接合至所述第一封装件,所述第四传感器电耦合至所述第一封装件。
根据本发明的又一方面,提供了一种器件,包括:第一封装件,位于第一衬底的凹部中,所述第一封装件包括第一管芯;以及第一传感器,电耦合至所述第一封装件和所述第一衬底,所述第一传感器具有直接位于所述第一衬底的所述凹部上方的第一部分以及直接位于所述第一衬底的所述凹部之外的部分上方的第二部分。
在该器件中,所述第一传感器包括心率监控器、环境光传感器、紫外光传感器、室温传感器、加速计、陀螺仪、磁力计、大气压力传感器、血氧传感器、全球定位系统(GPS)传感器、皮肤传导传感器、皮肤温度传感器、血糖监控器等或它们的组合。
该器件还包括:第二传感器,电耦合至所述第一封装件,所述第二传感器仅直接位于所述第一衬底的所述凹部上方。
附图说明
当阅读附图时,根据以下详细的描述来更好地理解本发明的各个方面。注意,根据工业的标准实践,各个部件没有按比例绘制。实际上,为了讨论的清楚,可以任意地增加或减小各个部件的尺寸。
图1至图3、图4A和图4B、图5至图24以及图25A和图25B是根据一些实施例的在形成封装结构的工艺期间的中间步骤的示图。
图26、图27A和图27B、图28至图32以及图33A和图33B是根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的示图。
图34是根据另一实施例的封装结构的截面图。
具体实施方式
以下公开内容提供了许多不同的用于实施本发明主题的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然,这些仅仅是实例而不用于限制。例如,在以下的描述中,在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例,并且也可以包括可以在第一部件和第二部件形成附加部件使得第一部件和第二部件没有直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚,其本身并不表示所讨论的各个实施例和/或结构之间的关系。
此外,为了易于描述,可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“上方”、“上部”等)以描述图中所示的一个元件或部件与另一个元件或部件的关系。类似地,本文中使用诸如“前侧”和“背侧”的术语,以更容易地识别各个部件,并且可以识别例如这些部件在另一部件的相对面上。除图中所示的定向之外,空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向),本文所使用的空间相对描述符可因此进行类似的解释。
可以在特定上下文,即用于可佩戴器件或结构的封装结构中讨论本文所讨论的实施例。封装结构可包括扇出或扇入型封装件。具体地,封装结构可以包括在诸如电子织物(有时称为智能服装)、可佩戴计算机、运动追踪器、智能手表、智能眼镜、GPS(全球定位系统)设备、医疗设备、增强现实设备、虚拟实境体验机、智能连接产品等的可佩戴设备中。此外,本发明的技术教导可应用于任何封装结构,包括具有一个或多个传感器的一个或多个集成电路管芯。其他实施例预期其他应用,诸如本领域技术人员在阅读本发明的基础上可以容易理解不同封装类型或不同结构。应该注意,本文所讨论的实施例不是必须示出可在结构中存在的每个部件或特征。例如,诸如当一个部件的讨论足以覆盖实施例的多方面时,可以从图中省略多个部件。此外,可以以特定的顺序执行本文所讨论的方法实施例;然而可以以任何逻辑顺序执行其他方法实施例。
图1至图3、图4A和图4B、图5至图24和图25A和图25B示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的示图。图至图3、图4A、图5至图24和图25A是截面图,而图4B和图25B是顶视图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。示出了分别用于形成第一封装件和第二封装件的第一封装区域300和第二封装区域302。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,使得多个封装件可以同时形成在载体衬底100上。释放层102可以由基于聚合物的材料形成,其可以与载体衬底100一起从将在后续步骤中形成的上覆结构被去除。在一些实施例中,释放层102是环氧基热释放材料,其在被加热时失去其粘性,诸如光热转换(LTHC)释放涂层。在其他实施例中,释放层102可以是紫外(UV)凝胶,其在暴露给UV光时失去其粘性。释放层102可以以液体形式分布并固化,其可以是层压在载体衬底100上的层压膜等。释放层102的顶面可以是平整的并且可以具有高度的共面性。
在图2中,形成金属化图案106。如图2所示,介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由聚合物形成,诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中,介电层104由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG))等形成。介电层104可以通过任何可接受的沉积工艺形成,诸如旋涂、化学气相沉积(CVD)、层压等或它们的组合。
金属化图案106形成在介电层104上。作为形成金属化图案106的实例,晶种层(未示出)形成在介电层104上方。在一些实施例中,晶种层是金属层,其可以是单层或者包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等来形成晶种层。然后,在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中和晶种层的露出部分上。可以通过镀(诸如电镀或化学镀)等形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶和晶种层的其上没有形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦光刻胶被去除,诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻和干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中,介电层108形成在金属化图案106和介电层104上。在一些实施例中,介电层108由聚合物形成,其可以是诸如PBO、聚酰亚胺、BCB等的光敏材料,其可以使用光刻掩模进行图案化。在其他实施例中,介电层108由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG等)或等形成。可以通过旋涂、层压、CVD等或它们的组合来形成介电层108。然后,介电层108被图案化以形成露出部分金属化图案106的开口。图案化可以通过可接受的工艺,例如,当介电层是光敏材料时通过将介电层108暴露给光或者通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以被称为背侧再分布结构。如图所示,背侧再分布结构包括两个介电层104和108以及一个金属化图案106。在其他实施例中,背侧再分布结构可以包括任何数量的介电层、金属化图案和通孔。可以通过重复用于形成金属化图案106和介电层108的工艺,在背侧再分布结构中形成一个或多个附加的金属化图案和介电层。通过在下面的介电层的开口中形成晶种层和金属化图案的导电材料,可以在形成金属化图案期间形成通孔。因此,通孔可以互连和电耦合各个金属化图案。
此外,在图3中,形成通孔112。作为形成通孔112的实例,晶种层形成在背侧再分布结构上方,例如所示的介电层108和金属化图案106的暴露部分。在一些实施例中,晶种层是金属层,其可以是单层或者包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以例如使用PVD等形成晶种层。在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中和晶种层的露出部分上。可以通过镀(诸如电镀或化学镀)等形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。光刻胶和晶种层的其上没有形成导电材料的部分被去除。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)来去除光刻胶。一旦光刻胶被去除,可以诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成通孔112。
在图4A和图4B中,集成电路管芯114通过粘合剂116粘合至介电层108。图4B是图4A中的结构的顶视图,其中图4A中的结构是沿着图4B中的线A-A所截取的。如图4B所示,在第一封装区域300和第二封装区域302的每一个中粘合四个集成电路管芯114(114-1、114-2、114-3和114-4),并且在其他实施例中,可以在每个区域中粘合更多或更少的集成电路管芯。此外,如图4B所示,集成电路管芯114可以具有不同的尺寸,并且在其他实施例中,集成电路管芯114可以具有相同尺寸。
在粘合至介电层108之前,集成电路管芯114可以根据可应用的制造工艺进行处理以在集成电路管芯114中形成集成电路。例如,集成电路管芯114均包括半导体衬底118,诸如掺杂或非掺杂硅或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料,诸如锗);化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟);合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。还可以使用诸如多层或梯度衬底的其他衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上,并且这些器件可以通过例如通过半导体衬底118上的一个或多个介电层中的金属化图案形成的互连结构120来互连以形成集成电路。
集成电路管芯114还包括焊盘122,诸如铝焊盘,通过其进行外部连接。焊盘122可以称为集成电路管芯114的对应有源侧。钝化膜124位于集成电路管芯114和部分焊盘122上。开口穿过钝化膜124到达焊盘122。管芯连接件126(诸如导电柱(例如,包括诸如铜的金属))位于穿过钝化膜124的开口中,并且机械和电耦合至对应的焊盘122。例如可以通过镀等形成管芯连接件126。管芯连接件126电耦合集成电路管芯114的对应集成电路。
介电材料128位于集成电路管芯114的有源侧上,诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126,并且介电材料128与对应的集成电路管芯114横向共端部。介电材料128可以是聚合物(诸如PBO、聚酰亚胺、BCB等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、PSG、BSG、BPSG等)等或它们的组合,并且例如可以通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上,并且将集成电路管芯114粘合至背侧再分布结构110,诸如所示介电层108。粘合剂116可以是任何适当的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂116可以被涂覆至集成电路管芯114的背侧,诸如对应半导体晶圆的背侧或者可以涂覆在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割而进行分割,并且例如使用拾放工具(pich-and-place tool,又称为拾取和放置工具)通过粘合剂116粘合至介电层108。
集成电路管芯114可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯)等或它们的组合。作为实例。AFE是模拟信号调节电路的集合,例如其使用运算放大器、滤波器和/或用于传感器和其他电路的专用集成电路以提供可配置和灵活的电子功能块,从而将各种传感器连接至模数转换器或者在一些情况下连接至微控制器。例如,在一个实施例中,集成电路管芯114-1是AFE管芯,集成电路管芯114-2是PMIC管芯,集成电路管芯114-3是信号处理管芯,以及集成电路管芯114-4是微控制器(MCU)管芯。
在图5中,密封剂130形成在各个部件上。密封剂130可以是模塑料、环氧树脂等,并且可以通过压缩模制、转移模制等来涂覆。在固化之后,密封剂130可以经受研磨工艺来露出通孔112和管芯连接件126。在研磨工艺之后,通孔112、管芯连接件126和密封剂130的顶面是共面的。在一些实施例中,例如如果通孔112和管芯连接件126已经被露出,则可以省略研磨。
在图6至图16中,形成前侧再分布结构160。如图16中将示出的,前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154。
在图6中,介电层132被沉积在密封剂130、通孔112和管芯连接件126上。在一些实施例中,介电层132由聚合物形成,其可以是诸如PBO、聚酰亚胺、BCB等的光敏材料,并且其可以使用光刻掩模进行图案化。在其他实施例中,介电层132由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG等)形成。可以通过旋涂、层压、CVD等或它们的组合来形成介电层132。
在图7中,然后图案化介电层132。图案化形成开口以露出通孔112和管芯连接件126的部分。可以通过可接受的工艺图案化,诸如通过在介电层132是光敏材料时将介电层132暴露给光或者通过使用各向异性蚀刻的蚀刻。如果介电层132是光敏材料,则介电层132可以在曝光之后显影。
在图8中,具有通孔的金属化图案138形成在介电层132上。作为形成金属化图案38的实例,晶种层(未示出)形成在介电层132上方以及穿过介电层132的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后,在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中和晶种层的露出部分上。可以通过镀(诸如电镀或化学镀等)形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上没有形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦光刻胶被去除,就诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。通孔形成在穿过介电层132的开口中,以例如到达通孔112和/或管芯连接件126。
在图9中,介电层140沉积在金属化图案化138和介电层132上。在一些实施例中,介电层140由聚合物形成,其可以是诸如PBO、聚酰亚胺、BCB等的光敏材料,其可以使用光刻掩模来图案化。在其他实施例中,介电层140由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG等)或它们的组合形成。可以通过旋涂、层压、CVD等或它们的组合来形成介电层140
在图10中,介电层140然后被图案化。图案化形成开口以露出金属化图案化138的部分。图案化可以通过可接受的工艺,诸如通过在介电层是光敏材料时将介电层140暴露给光或者通过例如使用各向异性蚀刻的蚀刻。如果介电层140是光敏材料,则介电层140可以在曝光之后显影。
在图11中,具有通孔的金属化图案146形成在介电层140上。作为形成金属化图案146的实例,晶种层(未示出)形成在介电层140上方和穿过介电层140的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以例如使用PVD等形成晶种层。然后,在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中和晶种层的露出部分上。可以通过镀(诸如电镀或化学镀等)形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上没有形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦光刻胶被去除,就诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成金属化图案146和通孔。通孔形成在穿过介电层140的开口中,例如以到达金属化图案138的部分。
在图12中,介电层148沉积在金属化图案化146和介电层140上。在一些实施例中,介电层148由聚合物形成,其可以是诸如PBO、聚酰亚胺、BCB等的光敏材料,其可以使用光刻掩模来图案化。在其他实施例中,介电层148由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG等)等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层148。
在图13中,介电层148然后被图案化。图案化形成开口以露出金属化图案化146的部分。可以通过可接受的工艺进行图案化,诸如通过在介电层是光敏材料时将介电层148暴露给光或者通过例如使用各向异性蚀刻的蚀刻。如果介电层148是光敏材料,则介电层148可以在曝光之后显影。
在图14中,具有通孔的金属化图案154形成在介电层148上。作为形成金属化图案154的实例,晶种层(未示出)形成在介电层148上方以及穿过介电层148的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后,在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中和晶种层的露出部分上。可以通过镀(诸如电镀或化学镀等)形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上没有形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦光刻胶被去除,就诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成金属化图案154和通孔。通孔形成在穿过介电层132的开口中,以例如到达金属化图案146的部分。
在图15中,介电层156沉积在金属化图案化154和介电层148上。在一些实施例中,介电层156由聚合物形成,其可以是诸如PBO、聚酰亚胺、BCB等的光敏材料,其可以使用光刻掩模来图案化。在其他实施例中,介电层156由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层156。
在图16中,介电层156然后被图案化。图案化形成开口以露出金属化图案化154的部分。图案化可以通过可接受的工艺,诸如通过在介电层是光敏材料时将介电层156暴露给光或者通过例如使用各向异性蚀刻的蚀刻。如果介电层156是光敏材料,则介电层156可以在曝光之后显影。
前侧再分布结构160被示为实例。更多或更少的介电层和金属化图案可以形成在前侧再分布结构160中。如果将形成较少的介电层和金属化图案化,则可以省略上述步骤和工艺。如果将形成更多的介电层和金属化图案,则可以重复上述步骤和工艺。本领域技术人员容易理解将省略或重复哪些步骤和工艺。
在图17中,焊盘162可以称为凸块下金属化件(UBM),形成在前侧再分布结构160的外侧上。在所示实施例中,焊盘162形成为穿过介电层156的开口到达金属化图案154。作为形成焊盘162的实例,晶种层(未示出)形成在介电层156上方。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以例如使用PVD等形成晶种层。然后,在晶种层上形成和图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露给用于图案化的光。光刻胶的图案对应于焊盘162。图案化形成穿过光刻胶的开口以露出晶种层。导电材料形成在光刻胶的开口中以及晶种层的露出部分上。可以通过镀(诸如电镀或化学镀等)形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上没有形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦光刻胶被去除,就诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的露出部分。晶种层的剩余部分和导电材料形成焊盘162。
在图18中,执行载体衬底分离以从背侧再分布结构(例如,介电层104)拆离(分离)载体衬底100。根据一些实施例,分离包括在释放层102上照射诸如激光或UV光的光,使得释放层102在光的热量下分解,并且可以去除载体衬底100。然后,翻转结构并放置在带170上。
在图19中,穿过介电层104形成开口以露出金属化图案106的部分。例如可以使用激光钻孔、蚀刻等形成开口。
在图20中,沿着划线区域(例如,位于相邻区域300和302之间)通过锯切184执行分割工艺。锯切184将第一封装区域300与第二封装区域302进行分割。图21示出了所得到的分割结构。分割使得封装件200被分割,该封装件可以来自第一封装区域300或第二封装区域302。封装件200还可以称为集成扇出(InFo)封装件200。
在图22中,衬底402被示出具有位于衬底402的至少一部分上方的凹部404。衬底402可以是半导体衬底,诸如掺杂或非掺杂硅或者SOI衬底的有源层。衬底402可以包括其他半导体材料(诸如砷)、化合物半导体(包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟)、合金半导体(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP)或它们的组合。还可以使用诸如多层或梯度衬底的其他衬底。在一些实施例中,衬底402基于诸如玻璃纤维强化树脂芯的绝缘芯(insulating core)。一种示例性芯材料是诸如FR4的玻璃纤维树脂。可选芯材料包括双马来酰亚胺三嗪(BT)树脂,或者可选地其他印刷电路板(PCB)材料或膜。诸如味之素累积膜(ABF)的累积膜或其他层压件可用于衬底402。衬底402可以称为封装衬底402。
衬底402可以包括有源和无源器件(在图22中未示出)。本领域技术人员应该意识到,诸如晶体管、电容器、电阻器、它们的组合等的各种器件可用于生成封装件的设计的结构和功能要求。可以使用任何适当的方法形成器件。
衬底402还可以包括金属化层和通孔(未示出)。金属化层和通孔可以形成在有源和无源器件上方,并且被设计为连接各个器件以形成功能电路。金属化层可由介电材料(例如,低k介电材料)和导电材料(例如,铜)的交替层形成,其中通孔互连导电材料层,并且通过任何适当的工艺(诸如沉积、镶嵌、双镶嵌等)形成该金属化层。在一些实施例中,衬底402基本不包括有源和无源器件。
可以通过图案化衬底402在衬底402上来形成凹部404。可以例如通过蚀刻工艺来执行图案化。在一些实施例中,衬底具有厚度H1,其中凹部具有小于厚度H1的深度H2。在一些实施例中,深度H2在厚度H1的大约10%至大约50%的范围内,诸如大约为厚度H1的30%,
在图23中,接触区域406形成在衬底402上的凹部404中。在所示实施例中,接触区域406形成在凹部404的底部上。在一些实施例中,接触区域406是接合焊盘。接合焊盘406可以形成在衬底402上方。在一些实施例中,在衬底402的凹部404中通过形成介电层(未示出)中的凹部(未示出)来形成接合焊盘406。凹部可以形成为允许接合焊盘406嵌入到介电层中。在其他实施例中,省略凹部,因为接合焊盘406可形成在介电层上方。接合焊盘406将衬底402(包括衬底402中的金属化层)电和/或物理耦合至随后接合的第二封装件200(参见图24)。在一些实施例中,接合焊盘406包括薄晶种层(未示出),该薄晶种层由铜、钛、镍、金、锡等或它们的组合制成。接合焊盘406的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在一个实施例中,接合焊盘406的导电材料是铜、钨、铝、银、金、锡等或它们的组合。
在图24中,封装件200被放置在衬底402的凹部404内,使得封装件200通过导电连接件408耦合至接合焊盘406。在一些实施例中,例如利用拾放工具,封装件200被放置在凹部404内。在一个实施例中,包括焊盘162的封装件200的表面可以与衬底402的表面平齐。在一些实施例中,包括焊盘162的封装件200的表面可以位于衬底402的表面上方或下方。
导电连接件408可以是焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镍-化学钯-浸金技术(ENEPIG)形成的凸块等。导电连接件408可以包括导电材料,诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在导电连接件408是焊料凸块的实施例中,通过首先利用这种常用方法(诸如蒸发、电镀、印刷、焊料转移、球置放等)形成焊料层来形成导电连接件408。一旦焊料层形成在结构上,就可以执行回流以将材料成形为期望的凸块形状。在另一实施例中,导电连接件408是金属柱(诸如铜柱),其通过溅射、印刷、电镀、化学镀、CVD等形成。金属柱可以无焊料,并且具有基本垂直的侧壁。在一些实施例中,金属覆盖层(未示出)形成在金属柱连接件408的顶部上。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合,并且可以通过镀工艺形成该金属覆盖层。
在一些实施例中,可以使导电连接件408回流以将封装件200附接至接合焊盘406。导电连接件408将衬底402(包括衬底402中的金属化层)电和/或物理耦合至第二封装件200。导电连接件408使得传感器420和封装件200与衬底402电耦合。
导电连接件408可以在它们被回流之前具有形成在其上的环氧助焊剂(未示出),在封装件200附接至衬底402之后剩余助焊剂的至少一些环氧部分。该剩余的环氧部分可用作底部填充物来减小应力并保护由回流导电连接件408所得到的接头(joint)。在一些实施例中,底部填充物(未示出)可以凹部404中形成在封装件200和衬底402之间并环绕导电连接件408。底部填充物可以在附接封装件200之后通过毛细管流动工艺形成或者可以在附接封装件200之前通过适当的沉积方法形成。
在图25A和图25B中,传感器420附接至衬底402和封装件200。图25B是图25A中的结构的顶视图,图25A中的结构是沿着图25B的线A-A截取的。如图25B所示,具有四个传感器420(420-1、420-2、420-3和420-4)附接至包括封装件200和衬底402的结构,并且在其他实施例中,更多或更少的传感器可以附接至包括封装件200和衬底402的结构。在一些实施例中,凹部404具有长度L1和宽度W1。在一些实施例中,长度L1在大约5毫米(mm)至大约10mm的范围内,诸如大约7.6mm。在一些实施例中,宽度W1在大约5mm至大约10mm的范围内,诸如大约8mm。
此外,如图25B所示,传感器420可以具有不同的尺寸,使得它们覆盖凹部404和衬底402上方的不同数量的面积,并且在其他实施例中,传感器420可以具有相同的尺寸。如图25A所示,传感器420可以具有不同的高度H3和H4,并且在其他实施例中,传感器420可以具有相同的高度。在一些实施例中,传感器420-2的高度H3在衬底的厚度H1的大约80%至大约120%之间,诸如厚度H1的大约90%。在一些实施例中,传感器420-4的高度H4在衬底的厚度H1的大约80%至大约120%的范围内,诸如大约厚度H1的110%。
此外,如图25B所示,至少一个传感器420可附接至封装件200和衬底402(参见图25B中的420-2和420-4以及图25A中的420-2)。这些传感器可以“桥接”封装件200和衬底402。在平行于集成电路管芯114的背侧的平面中,“桥接”封装件200和衬底402的传感器延伸到第一封装件200和凹部404的横向边界外(参见图25A和图25B)。此外,至少一个传感器420可以仅附接至封装件200(参见420-1和420-4),并且至少一个传感器可仅附接至衬底402。
传感器420可包括心率监控器、环境光传感器、紫外光传感器、室温传感器、加速计、陀螺仪、磁力计、气压感测器、血氧传感器、全球定位系统(GPS)传感器、皮肤传导传感器(有时称为皮肤电反应传感器)、皮肤温度传感器、血糖监控器等或它们的组合。
传感器420可以通过导电连接件424、接触区域422、接触区域410和焊盘162耦合至衬底402和封装件200。导电连接件424可以类似于上述导电连接件408,并且这里不再进行重复描述,尽管导电连接件408和424不需要相同。在一些实施例中,接触区域422和410是接合焊盘。接合焊盘410和422可类似于上述接合焊盘406,并且这里不再进行重复描述,但是接合焊盘406、410和422不需要相同。
通过在衬底402的凹部404内嵌入封装件200,可以增加传感器420的数量和传感器420的尺寸。这允许封装结构的结构和设计的更大灵活性。例如,该封装结构使得总传感器面积(例如,被传感器420覆盖的包括凹部404的衬底402的顶视图的总表面积)大于封装件200的面积(例如,被封装件200覆盖的包括凹部404的衬底402的顶视图中的总表面积)。
图26、图27A和图27B、图28至图32以及图33A和图33B是根据另一实施例的在形成封装结构的工艺期间的中间步骤的示图。图26、图27A、图28至图32和图33A是截面图,以及图27B和图33B是顶视图。除了在该实施例中,封装件200(例如,InFo封装件200)通过导电元件(参见图33A中的430)代替导电连接件(参见图25A中的408)电耦合至衬底402之外,该实施例类似于图1至图3、图4A和图4B、图5至图24以及图25A和图25B的前述实施例。此外,在该实施例中,可以省略封装件200中的通孔112。这里不再重复该实施例的与先前描述的实施例类似的细节。
在图26中,载体衬底100包括位于载体衬底上方的释放层102,以及位于释放层102上方的粘合剂103。载体衬底100和释放层102先前进行了描述,并且这里不再重复描述。粘合剂103形成在释放层102上方并且可以是任何适当的粘合剂、环氧、管芯附接膜(DAF)等。
在图27A和图27B中,集成电路管芯114被放置在粘合剂103上。图27B是图27A中的结构的顶视图,其中图27A中的结构是沿着图27B的线A-A截取的。在一些实施例中,另一粘合剂(未示出)可涂覆至集成电路管芯114的背侧,诸如对应半导体晶圆(参见图4A中的116)的背侧。集成电路管芯114可以诸如通过锯切或切割进行分割,并且例如使用拾放工具进行放置。
如图27B所示,四个集成电路管芯114(114-1、114-2、114-3和114-4)粘合在第一封装区域300和第二封装区域302的每一个中,并且在其他实施例中,更多或更少的集成电路管芯可以粘合在每个区域中。此外,如图27B所示,集成电路管芯114可以具有不同尺寸,在其他实施例中,集成电路管芯114可具有相同尺寸。集成电路管芯114先前进行了描述,这里不再进行重复描述。
在图28中,密封剂130形成在各个部件上。可以是模塑料、环氧等,并且可以通过压缩模制、转移模制等来涂覆密封剂130。在固化之后,密封剂130可以经受研磨工艺来露出管芯连接件126。管芯连接件126和密封剂130的顶面在研磨工艺之后共面。在一些实施例中,例如如果已经露出管芯连接件126,则可以省略研磨。
在图29中,前侧再分布结构160形成在集成电路管芯114和密封剂130上方。前侧再分布结构160的金属化图案138、146和154以及焊盘162通过管芯连接件126电耦合至集成电路管芯114。前侧再分布结构160的形成先前在图6至图16中进行了描述,这里不再重复描述。
在图30中,执行载体衬底分离以从集成电路管芯114结构的背侧(例如粘合剂103)拆离(分离)载体衬底100。根据一些实施例,分离包括在释放层102上照射诸如激光或UV光的光,使得释放层102在光的热量下分解并且可以去除载体衬底100。然后,翻转结构并放置在带170上。
在图31中,沿着划线区域(例如,位于相邻区域300和302之间)通过锯切184执行分割工艺。锯切184将第一封装区域300与第二封装区域302进行分割。图32示出了所得到的分割结构。分割使得封装件500被分割,该封装件可以是来自第一封装区域300或第二封装区域302中的一个。封装件500还可以称为InFo封装件500。
此外,在图32中,封装件500被放置在衬底402的凹部404内,使得封装件500利用粘合剂103粘合至衬底402。在一些实施例中,封装件500例如利用拾放工具被放置在凹部404内。在一个实施例中,包括焊盘162的封装件500的表面与衬底402的表面平齐。在一些实施例中,包括焊盘162的封装件500的表面可以位于衬底402的表面上方或下方。
在图33A和图33B中,传感器420附接至衬底402和封装件200。图33B是图33A中的结构的顶视图,其中图33A中的结构是沿着图33B的线A-A截取的。如图33B所示,具有四个传感器420(420-1、420-2、420-3和420-4)附接至包括封装件500和衬底402的结构,并且在其他实施例中,更多或更少的传感器可附接至包括封装件500和衬底402的结构。传感器420和衬底402先前进行了描述,并且这里不再重复描述。
在该实施例中,导电元件430通过焊盘162和接触区域410将封装件500耦合至衬底402。导电元件430使得传感器420和封装件200与衬底402电耦合。
如图33B所示,至少一个传感器420可附接至封装件500和衬底402(参见图33B中的420-2和420-4以及图33A中的420-2)。这些传感器可以“桥接”封装500和衬底402。此外,至少一个传感器420可以仅附接至封装件200(参见420-1和420-4),并且至少一个传感器可以仅附接至衬底402。
导电元件430可以是导线、柔性电路等,其中,其一端耦合至衬底402的接触区域410且另一端耦合至封装件500的一个焊盘162。在引线接合的实施例中,导电元件430可以通过以下步骤来形成:在接触区域410上形成球接合并在封装件500的焊盘162上形成针脚式接合。
图34是根据另一实施例的封装结构的截面图。除了在该实施例中包括耦合至封装件500且邻接衬底402的至少一部分的部件602之外,该实施例类似于图26、图27A和图27B、图28至图32以及图33A和图33B的实施例。这里将不再重复该实施例与先前描述的实施例类似的具体细节。
部件602利用接触区域622和导电连接件624耦合至封装件500。接触区域622和导电连接件624可以分别类似于上述接触区域422和导电连接件424,并且这里不再重复描述,但是接触区域422和622以及导电连接件424和624可以不同。
在一个实施例中,部件602是热电发电机(有时称为热电发电采集机)。在部件602是热电发电机的一个实施例中,表面604A和604B中的至少一个能够与佩戴该器件(例如,智能手表)的人的皮肤直接接触,其中该器件包括图34的封装结构,使得热电发电机602可以将来自人的热量转换为电能来辅助对器件供电。例如,在该实施例中,所转换的电能可以直接对器件进行供电,或者其可以存储在器件的电池(未示出)中。在部件602是电热发生器的另一实施例中,至少一个表面606接触衬底402,并且衬底402能够与佩戴该器件的人的皮肤接触,其中该器件包括图34的封装结构,使得人的热量可以通过衬底402传递给热电发电机602的表面606,其可以将传输的热量转换为电能以辅助对器件供电。
如图34所示,部件602具有在封装件500上方延伸的高度H5,并且可以通过深度H6嵌入到衬底402内。在一些实施例中,高度H5在衬底的厚度H1的大约10%至大约40%的范围内,诸如厚度H1的大约25%。在一些实施例中,深度H6在衬底的厚度H1的大约10%至大约40%的范围内,诸如厚度H1的大约25%。
通过将封装件200嵌入到衬底402的凹部404中,可以增加传感器420的数量和传感器420的尺寸。这允许封装结构的结构和设计的更大灵活性。例如,该封装结构允许总传感器面积(例如,被传感器420覆盖的包括凹部404的衬底402的顶视图中的总表面积)大于封装件500的面积(例如,被封装件500覆盖的包括凹部404的衬底402的顶视图中的总表面积)。
一个实施例是一种方法,包括:将第一封装件放置在第一衬底的凹部内。第一封装件包括第一管芯。该方法还包括将第一传感器附接至第一封装件和第一衬底。第一传感器电耦合至第一封装件和第一衬底。
另一实施例是一种方法,包括:形成第一封装件,形成第一封装件包括利用密封剂至少横向地密封第一管芯,第一管芯具有有源侧和背侧,背侧与有源侧相对;以及形成位于第一管芯和密封剂上方的第一再分布结构,第一再分布结构耦合至第一管芯的有源侧。该方法还包括:将第一封装件耦合至第一衬底,第一封装件的至少一部分延伸到第一衬底中的凹部内;以及将第一传感器接合至第一封装件和第一衬底,第一传感器电耦合至第一封装件和第一衬底。
又一实施例是一种器件,包括:第一封装件,位于第一衬底的凹部中,第一封装件包括第一管芯;以及第一传感器,电耦合至第一封装件和第一衬底,第一传感器具有直接位于第一衬底的凹部上方的第一部分和直接位于第一衬底的凹部外的部分上方的第二部分。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到,这些等效结构不背离本发明的精神和范围,并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。
Claims (10)
1.一种用于形成封装结构的方法,包括:
将第一封装件放置在第一衬底的凹部内,所述第一封装件包括第一管芯;以及
将第一传感器附接至所述第一封装件和所述第一衬底,所述第一传感器电耦合至所述第一封装件和所述第一衬底。
2.根据权利要求1所述的用于形成封装结构的方法,其中,所述第一传感器包括心率监控器、环境光传感器、紫外光传感器、室温传感器、加速计、陀螺仪、磁力计、大气压力传感器、血氧传感器、全球定位系统(GPS)传感器、皮肤传导传感器、皮肤温度传感器、血糖监控器等或它们的组合。
3.根据权利要求1所述的用于形成封装结构的方法,还包括:
在所述第一衬底的凹部中形成第一接合焊盘,所述第一封装件通过第一导电连接件电耦合至所述第一衬底的所述第一接合焊盘。
4.根据权利要求1所述的用于形成封装结构的方法,还包括:
在所述第一衬底的第一表面上形成第二接合焊盘,所述第一表面位于所述第一衬底的凹部之外,所述第一封装件通过第二导电连接件电耦合至所述第一衬底的所述第二接合焊盘。
5.根据权利要求1所述的用于形成封装结构的方法,还包括:
将第二传感器附接至所述第一封装件,所述第二传感器电耦合至所述第一封装件。
6.根据权利要求5所述的用于形成封装结构的方法,还包括:
将第三传感器附接至所述第一封装件和所述第一衬底,所述第三传感器电耦合至所述第一封装件和所述第一衬底。
7.根据权利要求1所述的用于形成封装结构的方法,还包括:
形成所述第一封装件,形成所述第一封装件包括:
利用密封剂至少横向地密封所述第一管芯;以及
在所述第一管芯和所述密封剂上方形成第一再分布结构,所述第一传感器电耦合至所述第一再分布结构。
8.根据权利要求7所述的用于形成封装结构的方法,还包括:
在所述第一衬底的凹部中形成第三接合焊盘;以及
形成所述第一封装件还包括:
形成从所述第一再分布结构延伸穿过所述密封剂到达所述第一管芯的背侧的通孔,所述第一管芯的有源侧耦合至所述第一再分布结构,所述有源侧与所述背侧相对,所述第一封装件的所述通孔利用第一导电连接件电耦合至所述第一衬底的第三接合焊盘。
9.一种用于形成封装结构的方法,包括:
形成第一封装件,形成所述第一封装件包括:
利用密封剂至少横向地密封第一管芯,所述第一管芯具有有源侧和背侧,所述有源侧和所述背侧相对;和
在所述第一管芯和所述密封剂上方形成第一再分布结构,所述第一再分布结构耦合至所述第一管芯的有源侧;
将所述第一封装件耦合至第一衬底,所述第一封装件的至少一部分在所述第一衬底的凹部内延伸;以及
将第一传感器接合至所述第一封装件和所述第一衬底,所述第一传感器电耦合至所述第一封装件和所述第一衬底。
10.一种封装结构器件,包括:
第一封装件,位于第一衬底的凹部中,所述第一封装件包括第一管芯;以及
第一传感器,电耦合至所述第一封装件和所述第一衬底,所述第一传感器具有直接位于所述第一衬底的所述凹部上方的第一部分以及直接位于所述第一衬底的所述凹部之外的部分上方的第二部分。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/858,955 | 2015-09-18 | ||
US14/858,955 US9881850B2 (en) | 2015-09-18 | 2015-09-18 | Package structures and method of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106548947A true CN106548947A (zh) | 2017-03-29 |
CN106548947B CN106548947B (zh) | 2020-01-14 |
Family
ID=58224468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610677405.8A Active CN106548947B (zh) | 2015-09-18 | 2016-08-17 | 封装结构及其形成方法 |
Country Status (5)
Country | Link |
---|---|
US (3) | US9881850B2 (zh) |
KR (1) | KR101843241B1 (zh) |
CN (1) | CN106548947B (zh) |
DE (1) | DE102015117881B4 (zh) |
TW (1) | TWI622105B (zh) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10291973B2 (en) * | 2015-05-14 | 2019-05-14 | Knowles Electronics, Llc | Sensor device with ingress protection |
US10665579B2 (en) * | 2016-02-16 | 2020-05-26 | Xilinx, Inc. | Chip package assembly with power management integrated circuit and integrated circuit die |
US9812381B1 (en) * | 2016-05-31 | 2017-11-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
KR101973431B1 (ko) * | 2016-09-29 | 2019-04-29 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
TW202404049A (zh) | 2016-12-14 | 2024-01-16 | 成真股份有限公司 | 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器 |
US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
WO2019132965A1 (en) * | 2017-12-29 | 2019-07-04 | Intel Corporation | Microelectronic assemblies |
US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10825696B2 (en) * | 2018-07-02 | 2020-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cross-wafer RDLs in constructed wafers |
US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10937762B2 (en) | 2018-10-04 | 2021-03-02 | iCometrue Company Ltd. | Logic drive based on multichip package using interconnection bridge |
US11616046B2 (en) | 2018-11-02 | 2023-03-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11004758B2 (en) | 2019-06-17 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
US10985154B2 (en) | 2019-07-02 | 2021-04-20 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits |
US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
US11715728B2 (en) * | 2019-09-19 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photonic semiconductor device and method of manufacture |
DE102020119103A1 (de) | 2019-09-19 | 2021-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photonische halbleitervorrichtung und herstellungsverfahren |
US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
TWI768294B (zh) * | 2019-12-31 | 2022-06-21 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
US11600526B2 (en) | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
CN113078149B (zh) * | 2021-03-12 | 2023-11-10 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN113078148B (zh) * | 2021-03-12 | 2024-03-26 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN113097201B (zh) * | 2021-04-01 | 2023-10-27 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101872757A (zh) * | 2009-04-24 | 2010-10-27 | 南茂科技股份有限公司 | 凹穴芯片封装结构及使用其的层叠封装结构 |
US20110158273A1 (en) * | 2009-12-28 | 2011-06-30 | Yoshio Okayama | Semiconductor laser device, optical pickup device and semiconductor device |
US20120017964A1 (en) * | 2010-07-23 | 2012-01-26 | Hussain Muhammad M | Apparatus, System, and Method for On-Chip Thermoelectricity Generation |
US20140103488A1 (en) * | 2012-10-11 | 2014-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP Structures and Methods of Forming the Same |
CN104766903A (zh) * | 2013-12-03 | 2015-07-08 | 光澄科技股份有限公司 | 集成模块及其形成方法 |
Family Cites Families (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150724A (en) | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
US20030059976A1 (en) * | 2001-09-24 | 2003-03-27 | Nathan Richard J. | Integrated package and methods for making same |
US7098542B1 (en) * | 2003-11-07 | 2006-08-29 | Xilinx, Inc. | Multi-chip configuration to connect flip-chips to flip-chips |
US7339275B2 (en) * | 2004-11-22 | 2008-03-04 | Freescale Semiconductor, Inc. | Multi-chips semiconductor device assemblies and methods for fabricating the same |
JP2006173279A (ja) | 2004-12-14 | 2006-06-29 | Denso Corp | 半導体センサ及び半導体センサの製造方法 |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
TWI332790B (en) | 2007-06-13 | 2010-11-01 | Ind Tech Res Inst | Image sensor module with a three-dimensional dies-stacking structure |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
US20090134481A1 (en) * | 2007-11-28 | 2009-05-28 | Analog Devices, Inc. | Molded Sensor Package and Assembly Method |
WO2010056359A1 (en) | 2008-11-14 | 2010-05-20 | Optoelectronic Systems Consulting, Inc. | Miniaturized implantable sensor platform having multiple devices and sub-chips |
US8390083B2 (en) * | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
KR20110041313A (ko) * | 2009-10-15 | 2011-04-21 | 에스티에스반도체통신 주식회사 | 적층형 고상 드라이브 및 그 제조 방법 |
US20110193235A1 (en) * | 2010-02-05 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC Architecture with Die Inside Interposer |
US8519537B2 (en) * | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
CN102859691B (zh) | 2010-04-07 | 2015-06-10 | 株式会社岛津制作所 | 放射线检测器及其制造方法 |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
KR101632249B1 (ko) * | 2011-10-31 | 2016-07-01 | 인텔 코포레이션 | 멀티 다이 패키지 구조들 |
US9263424B2 (en) | 2011-12-06 | 2016-02-16 | Intel Corporation | Semiconductor chip stacking assemblies |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
TWI462266B (zh) | 2012-03-20 | 2014-11-21 | Chipmos Technologies Inc | 晶片堆疊結構及其製造方法 |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9461025B2 (en) * | 2013-03-12 | 2016-10-04 | Taiwan Semiconductor Manfacturing Company, Ltd. | Electric magnetic shielding structure in packages |
KR20140113029A (ko) * | 2013-03-15 | 2014-09-24 | 삼성전자주식회사 | 열전소자가 배치된 히트 슬러그 및 이를 구비하는 반도체 패키지 |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US9150404B2 (en) | 2013-12-16 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with through molding vias |
US9935090B2 (en) * | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
DE102015207857A1 (de) * | 2015-04-29 | 2016-11-03 | Robert Bosch Gmbh | Thermoelektrische Vorrichtung sowie Herstellungsverfahren derselben |
-
2015
- 2015-09-18 US US14/858,955 patent/US9881850B2/en active Active
- 2015-10-21 DE DE102015117881.8A patent/DE102015117881B4/de active Active
-
2016
- 2016-01-04 KR KR1020160000606A patent/KR101843241B1/ko active IP Right Grant
- 2016-07-06 TW TW105121366A patent/TWI622105B/zh active
- 2016-08-17 CN CN201610677405.8A patent/CN106548947B/zh active Active
-
2018
- 2018-01-29 US US15/882,360 patent/US10937718B2/en active Active
-
2021
- 2021-03-01 US US17/188,707 patent/US11948862B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101872757A (zh) * | 2009-04-24 | 2010-10-27 | 南茂科技股份有限公司 | 凹穴芯片封装结构及使用其的层叠封装结构 |
US20110158273A1 (en) * | 2009-12-28 | 2011-06-30 | Yoshio Okayama | Semiconductor laser device, optical pickup device and semiconductor device |
US20120017964A1 (en) * | 2010-07-23 | 2012-01-26 | Hussain Muhammad M | Apparatus, System, and Method for On-Chip Thermoelectricity Generation |
US20140103488A1 (en) * | 2012-10-11 | 2014-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP Structures and Methods of Forming the Same |
CN104766903A (zh) * | 2013-12-03 | 2015-07-08 | 光澄科技股份有限公司 | 集成模块及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201721770A (zh) | 2017-06-16 |
US9881850B2 (en) | 2018-01-30 |
US20170084590A1 (en) | 2017-03-23 |
US10937718B2 (en) | 2021-03-02 |
CN106548947B (zh) | 2020-01-14 |
US11948862B2 (en) | 2024-04-02 |
DE102015117881A1 (de) | 2017-03-23 |
TWI622105B (zh) | 2018-04-21 |
US20210183745A1 (en) | 2021-06-17 |
DE102015117881B4 (de) | 2020-10-15 |
US20180166364A1 (en) | 2018-06-14 |
KR20170034289A (ko) | 2017-03-28 |
KR101843241B1 (ko) | 2018-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106548947A (zh) | 封装结构及其形成方法 | |
US10861830B2 (en) | Semiconductor device | |
US11990435B2 (en) | Fingerprint sensor and manufacturing method thereof | |
US20230386975A1 (en) | Package structure and method of forming the same | |
US11594520B2 (en) | Semiconductor package for thermal dissipation | |
CN106469661B (zh) | 封装结构及其形成方法 | |
US9293442B2 (en) | Semiconductor package and method | |
CN105428329B (zh) | 具有ubm的封装件和形成方法 | |
CN107026092A (zh) | 制造指纹扫描器的方法以及半导体装置 | |
US9911724B2 (en) | Multi-chip package system and methods of forming the same | |
CN108122784A (zh) | 封装单体化的方法 | |
CN109786274B (zh) | 半导体器件及其制造方法 | |
US8283780B2 (en) | Surface mount semiconductor device | |
US20170345746A1 (en) | Integrated circuit package with solder balls on two sides |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |