CN209626201U - 一种扇出型倒置封装结构 - Google Patents

一种扇出型倒置封装结构 Download PDF

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CN209626201U
CN209626201U CN201920159226.4U CN201920159226U CN209626201U CN 209626201 U CN209626201 U CN 209626201U CN 201920159226 U CN201920159226 U CN 201920159226U CN 209626201 U CN209626201 U CN 209626201U
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layer
chip
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plastic packaging
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王新
蒋振雷
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Hangzhou Jingtong Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本实用新型涉及一种扇出型倒置封装结构,包括重新布线层,在重新布线层的上表面设置芯片,再沿芯片自重新布线层凸起的形状涂覆一层有机物薄膜,有机物薄膜上为塑封层,在塑封层外露的一面设有均匀分布的沟槽。采用本实用新型的设计方案,在塑封芯片之前涂覆一层有机物树脂薄膜,可以起到帮助固定芯片位置的作用,可以减小在接下来的塑封以及重新布线层的制作过程中产生的芯片位置偏移;在塑封层上形成少量沟槽,这些沟槽可以释放和缓解整个塑封层在后续工艺步骤中产生的内应力并减小封装芯片的翘曲度。通过改善芯片偏移和翘曲度从而提到良率和可靠性。

Description

一种扇出型倒置封装结构
技术领域
本实用新型涉及半导体封装技术领域,具体涉及一种扇出型倒置封装结构。
背景技术
随着电子装置设备的集成度越来越高,对小型化高密度超薄封装提出了更高的要求,扇出型封装技术正得到业界越来越多的关注和应用。目前在晶圆级扇出型封装领域广泛采用的是基于英飞凌公司(Infineon)提出的嵌入式晶圆级球栅阵列eWLB技术(embeddedWafer Level BGA),其主要流程为:
(1)在临时承载片上贴附热剥离膜;
(2)将要封装的芯片倒装(face down)贴装在载片的热剥离膜上;
(3)对芯片进行塑封,并去除临时承载片和热剥离膜;
(4)在塑封层上裸露出的芯片正面制作重新布线层并焊接锡球;
(5)对封装好的芯片进行单元切割;
该eWLB封装的两个技术难点在于如何有效减小芯片在塑封以及制作重新布线层等过程中可能产生的位置偏移,以及整个封装体在各个工艺步骤的温度升降过程中产生的热应力形成的翘曲,这直接关系到封装工艺的总体精度良率和可靠性。
实用新型内容
实用新型目的:本实用新型的目的在于解决现有的eWLB封装无法有效减小芯片在塑封以及制作重新布线层等过程中可能产生的位置偏移,以及整个封装体在各个工艺步骤的温度升降过程中产生的热应力形成的翘曲的问题。
技术方案:本实用新型提供以下技术方案:
一种扇出型倒置封装结构,包括重新布线层,在重新布线层的上表面设置芯片,再沿芯片自重新布线层凸起的形状涂覆一层与凸起的形状适配的有机物薄膜,有机物薄膜上为塑封层。
此处重新布线层上采用的是设置,而非贴附,因为贴附是在临时载片上完成,而非在重新布线层上完成,重新布线层是在上部分完成后根据芯片的位置进行适应于芯片位置的重新布线层的制备。
进一步地,在塑封层外露的一面设有均匀分布的沟槽。
进一步地,在重新布线层的下表面金属触点位置涂覆有锡球。
进一步地,重新布线层由若干介电层和金属导电层构成。
进一步地,所述芯片的器件面朝向重新布线层。
进一步地,所述沟槽的宽度为0.5~5mm,沟槽的深度为50~500μm。
一种扇出型倒置封装结构的制备方法,包括以下步骤:
1)在临时载片表面粘附热剥离膜,该热剥离膜外露的表面为第一表面;
2)在步骤1)所得到的热剥离膜表面进行倒装芯片贴装,芯片的器件面朝向第一表面;
3)在芯片上面继续以旋涂方式涂覆一层有机树脂薄膜并固化;
4)将贴附在临时载片上的芯片和机树脂薄膜进行整体塑封,形成塑封层,该塑封层的表面为第二表面;
5)在塑封层的第二表面上制作沟槽;
6)采用热剥离的办法将临时载片与塑封层分离并去除热剥离膜,从而使塑封层的与第一表面所接触的面上裸露出来;
7)根据芯片的位置,用薄膜工艺在塑封层的裸露面制作重新布线层;
8)在重新布线层的下表面采用植球工艺完成锡球的焊接;
9)进行单元切割以得到单独的封装体。
进一步地,所述有机树脂薄膜为PI薄膜或PBO薄膜。
进一步地,所述临时载片为玻璃载片、石英载片、硅片载片和陶瓷载片中的任意一种。
有益效果:本实用新型与现有技术相比:
(1)在塑封芯片之前涂覆一层有机物树脂薄膜,可以起到帮助固定芯片位置的作用,可以减小在接下来的塑封以及重新布线层的制作过程中产生的芯片位置偏移;
(2)在塑封层上形成少量沟槽,这些沟槽可以释放和缓解整个塑封层在后续工艺步骤中产生的内应力并减小封装芯片的翘曲度;通过改善芯片偏移和翘曲度从而提到良率和可靠性。
附图说明
图1为本实用新型的结构示意图;
图2为本实用新型制备方法步骤2)的示意图;
图3为本实用新型制备方法步骤3)的示意图;
图4为本实用新型制备方法步骤4)的示意图;
图5为本实用新型制备方法步骤5)的示意图;
图6为本实用新型制备方法步骤6)的示意图;
图7为本实用新型制备方法步骤7)的示意图。
具体实施方式
下面结合具体实施案例和附图对本实用新型进一步描述。
实施例1
一种扇出型倒置封装结构,包括重新布线层150,在重新布线层150的上表面设置芯片120,再沿芯片120自重新布线层凸起的形状涂覆一层与凸起的形状适配的有机物薄膜130,有机物薄膜130上为塑封层140。
此处重新布线层上采用的是设置,而非贴附,因为贴附是在临时载片上完成,而非在重新布线层上完成,重新布线层是在上部分完成后根据芯片的位置进行适应于芯片位置的重新布线层的制备。
在塑封层140外露的一面设有均匀分布的沟槽10。
在重新布线层150的下表面金属触点位置涂覆有锡球160。
重新布线层150由若干介电层和金属导电层构成。
芯片120的器件面朝向重新布线层150。
沟槽10的宽度为0.5~5mm,沟槽10的深度为50~500μm。
实施例2
如附图2所示,一种扇出型倒置封装结构的制备方法,包括以下步骤:
1)在临时载片100表面粘附热剥离膜110,该热剥离膜外露的表面为第一表面;
2)在步骤1)所得到的热剥离膜110表面进行倒装芯片120贴装,芯片120的器件面朝向第一表面;
3)在芯片120上面继续以旋涂方式涂覆一层有机树脂薄膜130并固化;
4)将贴附在临时载片100上的芯片120和机树脂薄膜130进行整体塑封,形成塑封层140,该塑封层140的表面为第二表面;
5)在塑封层140的第二表面上制作沟槽10;
6)采用热剥离的办法将临时载片100与塑封层140分离并去除热剥离膜110,从而使塑封层140的与第一表面所接触的面上裸露出来;
7)根据芯片120的位置,用薄膜工艺在塑封层140的裸露面制作重新布线层150;
8)在重新布线层150的下表面采用植球工艺完成锡球160的焊接;
9)进行单元切割以得到单独的封装体。
有机树脂薄膜130为PI薄膜或PBO薄膜。
临时载片100为玻璃载片、石英载片、硅片载片和陶瓷载片中的任意一种。

Claims (5)

1.一种扇出型倒置封装结构,其特征在于:包括重新布线层,在重新布线层的上表面设置芯片,再沿芯片自重新布线层凸起的形状涂覆一层与凸起的形状适配的有机物薄膜,有机物薄膜上为塑封层;在塑封层外露的一面设有均匀分布的沟槽。
2.根据权利要求1所述的扇出型倒置封装结构,其特征在于:在重新布线层的下表面金属触点位置涂覆有锡球。
3.根据权利要求1所述的扇出型倒置封装结构,其特征在于:重新布线层由若干介电层和金属导电层构成。
4.根据权利要求1所述的扇出型倒置封装结构,其特征在于:所述芯片的器件面朝向重新布线层。
5.根据权利要求1所述的扇出型倒置封装结构,其特征在于:所述沟槽的宽度为0.5~5mm,沟槽的深度为50~500μm。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887890A (zh) * 2019-01-30 2019-06-14 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887890A (zh) * 2019-01-30 2019-06-14 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法
CN109887890B (zh) * 2019-01-30 2024-02-06 杭州晶通科技有限公司 一种扇出型倒置封装结构及其制备方法

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