CN101221936A - 具有晶粒置入通孔之晶圆级封装及其方法 - Google Patents

具有晶粒置入通孔之晶圆级封装及其方法 Download PDF

Info

Publication number
CN101221936A
CN101221936A CNA2008100001070A CN200810000107A CN101221936A CN 101221936 A CN101221936 A CN 101221936A CN A2008100001070 A CNA2008100001070 A CN A2008100001070A CN 200810000107 A CN200810000107 A CN 200810000107A CN 101221936 A CN101221936 A CN 101221936A
Authority
CN
China
Prior art keywords
layer
crystal grain
substrate
hole
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008100001070A
Other languages
English (en)
Other versions
CN101221936B (zh
Inventor
杨文焜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN101221936A publication Critical patent/CN101221936A/zh
Application granted granted Critical
Publication of CN101221936B publication Critical patent/CN101221936B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明系揭露一种封装结构，包含具有晶粒置入通孔之基底、连接穿孔结构及第一接触垫。晶粒系配置于上述晶粒置入通孔之内，环绕层充填于晶粒与晶粒置入通孔侧壁间之间隙，及/或形成于晶粒之下表面。介电层形成于晶粒与基底之上，重布层(RDL)形成于介电层之上且耦合至第一接触垫。保护层形成于重布层(RDL)之上，以及第二接触垫形成于基底之下表面及连接穿孔结构之下。

Description

具有晶粒置入通孔之晶圆级封装及其方法
技术领域
本发明系有关一种晶圆级封装(WLP)之结构，特别是关于一种扩散式晶圆级封装(WLP)之结构，具有晶粒置入通孔(die receiving through-hole)形成于基底之内，以增进可靠度(reliability)及缩小装置体积。
背景技术
在半导体装置领域中，装置之密度持续增加，且体积逐渐减小。高密度装置之封装或交互连接技术的需求亦日益增加，以符合上述情况。一般而雷，在覆晶接合方法(flip-chip attachment method)中，焊锡凸块阵列系形成于晶粒表面上。焊锡凸块之形成系利用焊锡合成材料通过防焊层(solder mask)，以产生所需焊锡凸块之图案。晶粒封装之功能包含电源分配(power distribution)、讯号分配(signal distribution)、散热(heat dissipation)、保护及支撑等。由于半导体结构趋向复杂化，而一般传统技术，例如导线封装(lead frame package)、软性封装(flex package)、刚性封装(rigid package)技术，已无法达成于晶粒上产生具有高密度组件之小型晶粒。
再者，由于一般封装技术必须先晶圆上之晶粒分割为个别晶粒，再晶粒分别封装，因此上述技术之制程十分费时。因为晶粒封装技术与集成电路之发展有密切关联，因此封装技术对于电子组件之尺寸要求越来越高。基于上述之理由，现今之封装技术已逐渐趋向采用球栅阵列封装(ball grid array，BGA)、覆晶球栅阵列封装(flip chip ball grid array，FC-BGA)、芯片尺寸封装(chip size package，CSP)、晶圆级封装(Wafer Level Package，WLP)之技术。应可理解「晶圆级封装(WLP)」指晶圆上所有封装及交互连接结构，如同其它制程步骤，系于切割(singulation)为个别晶粒之前进行。一般而雷，在完成所有配装制程(assembling processes)或封装制程(packagingprocesses)之后，由具有复数半导体晶粒之晶圆中个别半导体封装分离。上述晶圆级封装具有极小之尺寸及良好之电性。
晶圆级封装(WLP)技术系为进阶之封装技术，其中晶粒系于晶圆上制造及测试，并且晶圆系利用组装于表面黏着线(surface-mount line)而进行分割(dicing)成为个别晶粒(singulated)。由于晶圆级封装技术系利用整个晶圆为主体，而非利用单一芯片(chip)或晶粒(die)，因此进行分割制程之前，须先完成封装与测试。再者，晶圆级封装(WLP)系为进阶技术，因此可忽略导线连接、晶粒配置及底部塡充。利用晶圆级封装(WLP)技术，可降低成本及制造时间，并且晶圆级封装(WLP)之最终结构可与晶粒相当，因此上述技术可符合电子组件微型化(miniaturization)之需求。
根据上述晶圆级封装(WLP)技术之优点，仍存在一些可能影响(influencing)晶圆级封装(WLP)技术接受度(acceptance)之问题。例如，晶圆级封装(WLP)结构与母板(印刷电路板(PCB))材料间之热膨胀系数(CTE)差异(不相符(mismatching))成为结构之应力不稳定(mechanica linstability)之另一关键因素。美国专利号第6,271,469号所揭露之封装结构便遇到上述热膨胀系数(CTE)不相符(mismatching)之问题。由于习知技术系利用封装胶体(molding compound)所封装(encapsulated)之硅晶粒。如熟知该项技术者所熟知，硅材料之热膨胀系数(CTE)系为2.3，但封装胶体之热膨胀系数(CTE)系约为40-80。上述配置由于封料与介电层材料之烘烤温度较高且使交互连接垫移动而导致良率与效能问题，最后导致制程中之晶粒位置移动。在温度循环中更难以回到原先位置(如烘烤温度接近/超过玻璃转换温度点(Glass transitiontemperature，Tg)时，系由环氧树脂之特性所导致)。因此根据上述表示习知封装结构无法利用大尺寸制造，且成本较高。
再者，上述技术牵涉晶粒接形成于基底上表面之使用。如熟知该项技术者所已知，半导体晶粒之连接垫经由重布层(RDL)配置于区域阵列型(areaarray type)中复数金属垫之重布制程而重布。增层(build up layer)会增加封装之尺寸。因而增加封装之厚度。然而，上述与减小晶粒尺寸之需要相互矛盾。
习知技术须利用复杂之制程形成「面板」型封装(“Panel”type package)。另需封装之封膜工具(moldtool)及铸膜材料之注入。由于封料热烘烤后造成变形，使得晶粒与封料之表面无法控制于相同高度，并且还需利用化学研磨制程(Chemical MechanicalPolishing，CMP)来研磨不平坦之表面。因而增加成本。
因此，本发明提供一种扩散式晶圆级封装(fan-out WLP)结构，具有良好之热膨胀系数(CTE)且可减小尺寸，以克服前述之问题，并且亦提供一种温度循环之良好电路板层级之可靠度(board levelreliability)。
发明内容
本发明之一目的系在于提供一种扩散式晶圆级封装(fan-out WLP)，具有良好的热膨胀系数(CTE)且可缩小体积。
本发明之另一目的系在于提供一种扩散式晶圆级封装(fan-out WLP)，包含一基底具有晶粒置入通孔，以增进可靠度与缩小装置体积。
本发明揭露一种半导体结构，包含基底具有晶粒置入通孔、连接穿孔结构及第一接触垫；晶粒配置于晶粒置入通孔之内；环绕层充塡于晶粒与晶粒置入通孔侧壁间之间隙，及/或形成于晶粒之下表面；介电层形成于晶粒与基底之上；重布层形成于介电层之上且耦合至第一接触垫；保护层形成于重布层之上；以及第二接触垫形成于基底之下表面及连接穿孔结构之下。
基底之材料包含树脂FR5、FR4、BT、硅、印刷电路板(PCB)材料、玻璃或陶瓷。上述基底之材料可选择性包含金属或合金，并且基底之热膨胀系数(CTE)接近母板之热膨胀系数(CTE)约为16至20。介电层之材料包含弹性介电材料(elastic dielectric layer)、感光材料(photosensitive layer)、硅介电层、硅氧烷聚合物(SINR)层、聚亚酰胺(PI)层或硅树脂层。
附图说明
图1系为根据本发明之扩散式晶圆级封装(LGA型)结构之剖面示意图。
图2系为根据本发明之扩散式晶圆级封装(BGA型)结构之剖面示意图。
图3系为根据本发明之基底之剖面示意图。
图4系为根据本发明之基底与玻璃载体之结合剖面示意图。
图5系为根据本发明之基底之上视示意图。
图6系为根据本发明之半导体装置封装之电路板温度循环测试(board level temperaturecycling test)之示意图。
图中：
2基底
3接触金属垫
4晶粒置入通孔
6晶粒
10接触垫
12介电层
14重布层
18端点垫
20导电锡球
21环绕层
22连接穿孔
24导电层
26保护层
28切割线
40玻璃载体工具
42黏胶层
具体实施方式
本发明配合其较佳实施例与后附之图式详述于下。应可理解，本发明中之较佳实施例系仅用以说明，而非用以限定本发明。此外，除文中之较佳实施例外，本发明亦可广泛应用于其它实施例，并且本发明并不限定于任何实施例，而应视后附之申请专利范围而定。
本发明揭露一种扩散式晶圆级封装(fan-out WLP)之结构，包含基底2具有预定端点接触金属垫3形成于其上，及预形成之晶粒置入通孔4形成于基底2。晶粒6系配置于晶粒置入通孔4之内，并且附着至环绕层21，例如环绕层21系塡充至晶粒6边缘与晶粒置入通孔4侧壁间之间隙及/或晶粒6之下方。感光层系涂布于晶粒6及预形成基底2之上(包含环绕层区域)。较佳的，感光层之材料系由弹性材料所形成。
图1系为根据本发明之一实施例之扩散式晶圆级封装(fan-out WLP)。如图1所示，扩散式晶圆级封装(fan-out WLP)之结构包含基底2具有端点接触金属垫3(有机材料之基底(organic substrate))，及晶粒置入通孔4形成于其中以容纳晶粒6。晶粒置入通孔4系形成于基底2之上表面且通过基底2至其下表面。晶粒置入通孔4系预形成于基底2之内。环绕层21系充塡于晶粒6与晶粒置入通孔4侧壁间之间隙；环绕层21亦可涂布于晶粒6之下表面上，因而晶粒6密封(sealing)。传导层(conductive layer)24系涂布于晶粒置入通孔4侧壁上，以使硅晶粒6与基底2间利用环绕层21而具有良好黏着性(better adhesion)。
晶粒6系配置于基底2上晶粒置入通孔4之内。如熟知该项技术者所熟知，接触垫(连接垫(bondingpads))10系形成于晶粒6之上。感光层(photosensitivelayer)或介电层12系形成于晶粒6与基底2上表面之上。复数开口系利用微影制程(lithography process)或暴露(expose)及生长制程(develop procedure)而形成于介电层12之内。复数开口系分别对准(aligned)接触垫或输入/输出垫(I/O pad)10，及基底2上表面上之第一端点接触金属垫3。重布层(redistributionlayer，RDL)14，亦可称为导电层14，系利用移除(晶种层(seed layer))形成于介电层12上之已选择金属层部份，以形成于介电层12之上，其中重布层(RDL)14可与晶粒6且通过输入/输出垫(I/O pad)10及第一端点接触金属垫3电性连接。基底2更包含连接穿孔22形成于基底2之内。第一端点接触金属垫3系形成于连接穿孔22之上。导电层系塡充于连接穿孔22，以利于电性连接(预形成之基底2)。第二端点连接垫18系配置于基底2之下表面及连接穿孔22之下，并且连接至基底2之第一接触金属垫3。切割线(scribe line)28系定义于封装单元之间，以选择性每一单元分离，且介电层12配置于切割线28之上。保护层(protection layer)26系用以覆盖重布层(RDL)14。多重增层(重布层(RDLs))系可藉由重复上述步骤而进行。
介电层12与环绕层21作为缓冲层，由于介电层12与环绕层21具有弹性特性(elastic properties)，因此可于温度循环时吸收晶粒6与基底2间之热应力(thermal mechanical stress)。上述结构称为栅格阵列(land grid array，LGA)型封装。
图2系显示另一实施例，导电锡球20系形成于第二端点垫18之上。其它部份与第一图相近，因此省略其说明。在此实施例中，端点垫18可作为球状阵列排列(Ball Grid Array，BGA)型封装之金属垫层(under ball metal，UBM)。复数接触导电垫3系形成于基底2之上表面及重布层14之下。
较佳的，基底2之材料系为有机基底，例如具有已定义置入通孔之环氧树脂型FR5、BT、印刷电路板(PCB)或具有预蚀刻电路之铜金属。较佳的，具有高玻璃转换温度点(Glass transition temperature，Tg)之有机基底系为环氧树脂型FR5或Bismaleimidetriazine(BT)型之基底。也可使用铜金属(热膨胀系数约为16)。玻璃、陶瓷、硅亦可作为基底。环绕层系由硅橡胶弹性材料(silicone rubber elastic materials)形成。
由于环氧树脂型有机基底(FR5/BT)之热膨胀系数(CTE)(X/Y方向)系约为16，晶粒重布之工具利用玻璃材料作为工具，且其热膨胀系数(CTE)系约为5至8。在温度循环(当温度接近玻璃转换温度点Tg)时FR5/BT不会回到原先位置，且导致须经过数个高温制程之晶圆级封装制程(WLP process)中面板(panel)上之晶粒移动(die shift)。
基底2可为圆形(round type)，例如晶圆型(wafertype)，且其径(diameter)可为200、300mm或更高。也可以采用矩形(rectangular type)，例如面板型(panel form)。基底2系预形成晶粒置入通孔4。分割线28系定义于单元之间，以分离每一单元。请参考图3，基底2包含复数预形成之晶粒置入通孔4及连接穿孔22。导电层系重新塡充至上述连接穿孔22(预形成)，因而建立连接穿孔22之结构。
在本发明之实施例中，介电层12较佳的系为弹性介电材料，并且由硅介电材料所制成，上述硅介电材料包含硅氧烷聚合物(SINR)、Dow Corning WL5000系列或其组合。在另一实施例中，介电层12系由包含聚亚酰胺(PI)层或硅树脂层之材料所制成。较佳的，介电层12系为感光层，以简化制程。
在本发明之一实施例中，上述弹性介电层系为一种热膨胀系数(CTE)大于100(ppm/℃)、延伸速率(elongation rate)约40％(较佳的为30％至50％)及硬度(hardness)介于塑料与橡胶间之材料。弹性介电层12之厚度系依照温度循环试验期间重布层/介电层接口中所累积之应力而决定。
图4系显示玻璃承载工具40，用以承载面板晶圆(panel wafer)(重布晶粒6及基底2)。黏着层42，例如紫外光烘烤型材料(UV curing material)，系形成于上述工具40之周边区域。在一实施例中，上述工具可由具有面板形式外形之玻璃所制成。晶粒置入通孔结构亦不会形成于基底之边缘。第四图之下方部份系为玻璃承载工具40与面板(晶粒与基底)之结合示意图。上述面板附着至玻璃承载工具40，并且于制程中黏着(stick)与维持(hold)上述面板。
图5系为具有晶粒置入通孔4之基底2之上视示意图。基底之边缘区域50并不具有晶粒置入通孔4，用以于晶圆级封装(WLP)制程中黏着玻璃承载工具40。完成晶圆级封装(WLP)制程后，基底2沿玻璃承载工具40之虚线而切割，表示虚线内之区域会利用封装切割制程(sawing process)来处理以封装切割(package singulation)。
参考图6，系显示与热膨胀系数(CTE)问题有关之主要部份。硅晶粒(热膨胀系数(CTE)约为2.3)系封装于上述封装之内部。FR5或BT有机环氧树脂型材料(热膨胀系数(CTE)约为16)系用以作为基底，并且其热膨胀系数(CTE)与印刷电路板或母板之热膨胀系数(CTE)相同。晶粒6与基底2间之间隙系塡充环绕层21(较佳的为弹性核心黏胶)，并且由于热膨胀系数(CTE)不相符(晶粒与环氧树脂型FR5/BT)而得以吸收热应力。再者，介电层12包含弹性材料，用以吸收晶粒垫与印刷电路板间之应力。重布层金属系为铜/金材料，并且热膨胀系数(CTE)系约为16与印刷电路板(PCB)及有机基底之热膨胀系数(CTE)相同，以及接触凸块(contact bump)之金属垫层(UBM)18配置于基底之端点接触金属垫3。印刷电路板(PCB)之金属栅(metal land)系为铜组成之金属(Cu compositionmetal)，铜之热膨胀系数(CTE)系约为16且与印刷电路板(PCB)之热膨胀系数(CTE)相同。根据上述，本发明可提供晶圆级封装良好的热膨胀系数(CTE)(与X/Y方向完全相符)解决方案。
显然地，利用本发明可解决增层(印刷电路板(PCB)与基底)下之热膨胀系数(CTE)相符之问题，并且提供较佳可靠度(在电路板层级条件(board levelcondition)之基底上端点垫(锡球(solder balls)/凸块(bumps))之X/Y方向并无热应力)及弹性分布层系用以吸收Z轴方向之应力。晶粒边缘与基底置入通孔侧壁间之间隙可用以塡充弹性介电材料，以吸收应力/热力。
在本发明之一实施例中，重布层(RDL)之材料包含钛/铜/金合金(Ti/Cu/Au alloy)或钛/铜/镍/金合金(Ti/Cu/Ni/Au alloy)；重布层(RDL)之厚度系介于2μm至15μm之间。钛/铜合金(Ti/Cu alloy)系利用溅镀(sputtering)技术而形成，例如晶种金属层(seed metallayers)，及铜/金(Cu/Au)或铜/镍/金合金(Cu/Ni/Aualloy)系由电镀(electroplating)技术所形成，利用电镀制程形成重布层(RDL)可使重布层(RDL)具有足够之厚度及较佳应力特性，以解决温度循环期间之热膨胀系数(CTE)不相符(mismatching)。金属垫可为铝或铜或其组合。如扩散式晶圆级封装(fan out WLP)之结构利用硅氧烷聚合物(SINR)作为弹性介电层及铜作为重布层(RDL)，根据应力分析，在此并未显示，重布层(RDL)/介电层界面所累积之应力减少。
如图1至图2所示，重布层(RDL)系由晶粒6扩散，并且往下与第二端点垫连接。本发明与习知技术不相同(习知技术为往上堆栈)，晶粒6系容纳于预形成之晶粒置入通孔4内，因而可减少封装之厚度。与习知技术之教示相反，并得以减少晶粒封装厚度。本发明之封装较习知技术为薄。再者，基底2系于封装前预先形成。晶粒置入通孔4系预先形成。因此，产率(throughput)可较以往更为增进。本发明揭露一种扩散式晶圆级封装(WLP)具有减小之厚度，及良好热膨胀系数(CTE)相符效能(performance)。
本发明包含制备一基底2(较佳的为有机基底FR4/FR5/BT)，接触金属垫3系形成于上表面及金属连接穿孔至下表面。置入通孔系利用较晶粒6尺寸加上大于100μm/边之尺寸而形成。深度(depth)系与晶粒厚度相同。
重布层(RDL)(层1，选择性制程)系形成于处理过之硅晶圆之上，如输入/输出金属垫(I/O pads)(连接垫)之微影制程太密集(tight)(小)时可于制程中增进良率(yield)。下一步系利用背部研磨(back-lapping)晶粒研磨至所需之厚度。利用分割制程晶圆分割成为晶粒。
因此，本发明之制程包含提供具有校准图案(alignment pattern)之晶粒重布(校准)工具40(较佳的为玻璃材料)。图案化黏胶系网印(printed)于工具40(用以黏着至晶粒之表面(主动表面))之上，再利用具有覆晶功能(flip chip function)之拣选与放置校准系统，所需晶粒6依照所需间距重布至工具40之上。接着，基底2系连接于工具之上，再环绕层材料网印于晶粒6与(FR5/BT)基底2之晶粒置入通孔4间之间隙及/或晶粒6之下表面。环绕层与基底之表面较佳的系维持于相同层级。然后，利用烘烤制程烘烤环绕层，以及利用紫外光烘烤(UV curing)连接玻璃承载工具。面板黏合剂(panel bonder)系用以玻璃承载工具40连接于基底2之上与晶粒6之背面。进行真空烘烤，再工具与面板晶圆分离。
当晶粒6系重布于基底2(面板基底)之上时，利用湿及/或干清洁进行清洁制程以清洁晶粒表面。下一步系介电层涂布于面板之表面。接着，利用微影制程以暴露(open)介层孔(via hole)(接触金属垫)及铝连接垫及/或分割线(选择性)。进行电浆清洁步骤(plasma clean step)，以清洁介层孔(via hole)与铝连接垫之表面。下一步系溅镀钛/铜(Ti/Cu)以作为晶种金属层，并且光阻(PR)涂布于介电层12与晶种金属层之上，以利于形成重布金属层(RDL)之图案。接着，进行电镀形成铜/金或铜/钛/金以作为重布金属层(RDL)，再光阻剥离且利用金属湿蚀刻以形成重布金属层(RDL metal trace)。接着，下一步系涂布与网印至介电层之顶部及/或暴露(open)分割线(选择性)。
锡球放置或焊锡黏胶网印至面板之下方，进行热回流制程(heat re-flow procedure)系预形成，以回流至锡球侧边(BGA型)。金属层系形成于介电层之顶部，以利形成顶部标示(top marking)。进行测试。面板晶圆级最后测试系利用垂式探针卡(verticalprobe card)进行，侦测垫系利用暴露预形成之接触连接垫上之介电层顶部，而形成于晶粒之电路侧边上。在测试后，基底系切割以上述封装分割成为个别单元。接着，上述封装系分别封装拣选与放置于托盘(tray)或胶带(tape)及卷轴(reel)。
本发明之优点详述如下：本发明之制程系为形成晶圆及封装之简易方法，且容易控制面板表面之粗糙(roughness)。在制程中，利用玻璃承载工具可使面板之厚度易于控制，且可忽略晶粒移动之问题。注入铸膜工具(injection mold tool)省略，且亦不会赘述有关变形、化学研磨制程之研磨程序(CMP polishprocess)。面板晶圆系易于利用晶圆及封装制程进行处理。
基底2系预先制备具有预形成之晶粒置入通孔4、连结穿孔22及端点金属垫18(有机基底)；晶粒置入通孔4之尺寸系与晶粒尺寸加上约大于100μm/边；由于硅晶粒6与基底2(FR5/BT)间之热膨胀系数(CTE)不相符，因而可利用塡充环绕层以作为压力缓冲释放区域。由于简易增层配置于晶粒6表面之顶部，因而增加封装产率(减少制造周期时间)。端点垫系形成于晶粒6主动表面之相同表面之上。
晶粒放置制程系与目前制程相同。环绕层(树脂、环氧树脂化合物、硅橡胶等)系重新塡充至晶粒边缘与晶粒置入通孔4间之间隙，以作为本发明之热应力释放缓冲区，然后进行真空热烘烤(vacuum heatcuring)。面板型制程可克服热膨胀系数(CTE)不相符之问题(利用具有接近硅晶粒之低热膨胀系数(CTE)之玻璃承载工具)。硅介电层(硅氧烷聚合物(SINR))仅涂布于主动表面及基底表面(较佳的为FR4、FR5或BT)。由于介电层(硅氧烷聚合物(SINR))系为感光层以暴露接触开口(contacting open)，因此利用光罩制程(photo mask process)而使接触垫暴露。晶粒附着材料系网印至晶粒背部及/或与晶粒连接之基底2。封装与电路层级之可靠度系较习知技术为佳，特别是在电路板层级温度循环试验，由于已定义基底2与印刷电路板母板之热膨胀系数(CTE)，因此并无热应力提供至锡凸块/球；而电路板测试之温度循环期间之先前错误模式(锡球崩裂(solder ball crack))便不会发生。因此可降低成本及简化制程。亦易于形成多重晶粒之封装。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张之专利权利范围。其专利保护范围当视后附之申请专利范围及其等同领域而定。凡熟悉此领域之技艺者，在不脱离本专利精神或范围内，所作之更动或润饰，均属于本发明所揭示精神下所完成之等效改变或设计，且应包含在下述之申请专利范围内。

Claims (10)

1.一种半导体装置封装结构，其特征在于：所述半导体装置封装结构，包含：
一基底具有一晶粒置入通孔、一连接穿孔及一第一接触垫；
一晶粒配置于该晶粒置入通孔之内；
一环绕层充塡于该晶粒与该晶粒置入通孔侧壁间之间隙，及/或形成于该晶粒之下表面；
一介电层形成于该晶粒与该基底之上；
一重布层形成于该介电层之上且耦合至该第一接触垫；
一保护层形成于该重布层之上；以及
一第二接触垫形成于该基底之下表面及该连接穿孔结构之下。
2.如权利要求1所述之半导体装置封装结构，其特征在于：更包含导电凸块耦合至该第二接触垫。
3.如权利要求1所述之半导体装置封装结构，其特征在于：其中该重布层包含钛/铜/金合金或钛/铜/镍/金合金。
4.如权利要求1所述之半导体装置封装结构，其特征在于：其中该基底之材料包含环氧树脂FR5或FR4。
5.如权利要求1所述之半导体装置封装结构，其特征在于：其中该基底之材料包含BT、硅、印刷电路板(PCB)材料、玻璃或陶瓷。
6.如权利要求1所述之半导体装置封装结构，其特征在于：其中该基底之材料包含合金或金属。
7.如权利要求1所述之半导体装置封装结构，其特征在于：其中该环绕层之材料包含弹性核心黏胶材料(elastic core paste material)。
8.如权利要求1所述之半导体装置封装结构，其特征在于：其中更包含一导电层配置于该晶粒置入通孔之侧壁。
9.如权利要求1所述之半导体装置封装结构，其特征在于：其中该介电层之材料包含弹性介电材料、感光材料、硅介电层、硅氧烷聚合物(SINR)层、聚亚酰胺(PI)层或硅树脂层。
10.一种形成半导体装置封装结构之方法，其特征在于：所述形成半导体装置封装结构之方法，包含：
提供一基底具有晶粒置入通孔、连接穿孔及接触金属垫；
图案化黏胶网印至一晶粒重布工具；
所需晶粒按所需间距重布至该晶粒重布工具；
该基底连接至该晶粒重布工具；
环绕层重新充塡至该晶粒与该晶粒置入通孔
侧壁间之间隙及/或该晶粒下表面；
玻璃载体连接至晶圆之背面；
分离该晶粒重布工具；
一介电层涂布至该晶粒之主动表面及该基底之上表面；
形成至少一导电层于该介电层之上；
形成一连接结构于该至少一导电层之上；以及
形成一保护层于该至少一导电层之上
CN2008100001070A 2007-01-03 2008-01-02 具有晶粒置入通孔之晶圆级封装及其方法 Active CN101221936B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/648,688 US8178963B2 (en) 2007-01-03 2007-01-03 Wafer level package with die receiving through-hole and method of the same
US11/648,688 2007-01-03

Publications (2)

Publication Number Publication Date
CN101221936A true CN101221936A (zh) 2008-07-16
CN101221936B CN101221936B (zh) 2012-01-11

Family

ID=39510072

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100001070A Active CN101221936B (zh) 2007-01-03 2008-01-02 具有晶粒置入通孔之晶圆级封装及其方法

Country Status (7)

Country Link
US (1) US8178963B2 (zh)
JP (1) JP2008182225A (zh)
KR (1) KR20080064088A (zh)
CN (1) CN101221936B (zh)
DE (1) DE102008003160A1 (zh)
SG (1) SG144131A1 (zh)
TW (1) TWI357643B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102412219A (zh) * 2010-09-22 2012-04-11 星科金朋有限公司 具有主动表面热移除的集成电路封装系统及其制造方法
CN103904062A (zh) * 2012-12-28 2014-07-02 欣兴电子股份有限公司 内埋式电子元件封装结构
CN104332414A (zh) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 嵌入式芯片的制造方法
CN104576575A (zh) * 2013-10-10 2015-04-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN106373947A (zh) * 2015-07-24 2017-02-01 英飞凌科技美国公司 鲁棒高性能半导体封装
CN106711094A (zh) * 2015-11-17 2017-05-24 Nepes株式会社 半导体封装件及其制造方法
CN110310895A (zh) * 2019-07-31 2019-10-08 中国电子科技集团公司第五十八研究所 一种埋入tsv转接芯片硅基扇出型三维集成封装方法及结构
CN110416091A (zh) * 2019-07-31 2019-11-05 中国电子科技集团公司第五十八研究所 一种硅基扇出型封装方法及结构

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863088B2 (en) * 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US7901981B2 (en) * 2009-02-20 2011-03-08 National Semiconductor Corporation Integrated circuit micro-module
US7898068B2 (en) * 2009-02-20 2011-03-01 National Semiconductor Corporation Integrated circuit micro-module
US7901984B2 (en) * 2009-02-20 2011-03-08 National Semiconductor Corporation Integrated circuit micro-module
WO2010096213A2 (en) * 2009-02-20 2010-08-26 National Semiconductor Corporation Integrated circuit micro-module
US8187920B2 (en) * 2009-02-20 2012-05-29 Texas Instruments Incorporated Integrated circuit micro-module
US7902661B2 (en) * 2009-02-20 2011-03-08 National Semiconductor Corporation Integrated circuit micro-module
US7843056B2 (en) * 2009-02-20 2010-11-30 National Semiconductor Corporation Integrated circuit micro-module
US7842544B2 (en) * 2009-02-20 2010-11-30 National Semiconductor Corporation Integrated circuit micro-module
TWI405302B (zh) * 2009-02-20 2013-08-11 Nat Semiconductor Corp 積體電路微模組
US8796561B1 (en) * 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8487426B2 (en) 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US8617927B1 (en) 2011-11-29 2013-12-31 Hrl Laboratories, Llc Method of mounting electronic chips
KR101831938B1 (ko) 2011-12-09 2018-02-23 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 이에 의해 제조된 팬 아웃 웨이퍼 레벨 패키지
KR101999262B1 (ko) 2012-09-12 2019-07-12 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
CN103904061A (zh) * 2012-12-25 2014-07-02 欣兴电子股份有限公司 内埋式电子元件封装结构
US8803310B1 (en) * 2013-02-08 2014-08-12 Unimicron Technology Corp. Embedded electronic device package structure
US10079160B1 (en) * 2013-06-21 2018-09-18 Hrl Laboratories, Llc Surface mount package for semiconductor devices with embedded heat spreaders
US9177919B2 (en) * 2013-11-18 2015-11-03 Xintec Inc. Chip package and method for forming the same
US20150279814A1 (en) * 2014-04-01 2015-10-01 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded chips
KR101634067B1 (ko) 2014-10-01 2016-06-30 주식회사 네패스 반도체 패키지 및 그 제조방법
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9385083B1 (en) 2015-05-22 2016-07-05 Hrl Laboratories, Llc Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10026672B1 (en) 2015-10-21 2018-07-17 Hrl Laboratories, Llc Recursive metal embedded chip assembly
US10014268B2 (en) * 2016-03-01 2018-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10121766B2 (en) 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10068855B2 (en) * 2016-09-12 2018-09-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, method of manufacturing the same, and electronic device module
KR102051373B1 (ko) 2016-09-23 2019-12-04 삼성전자주식회사 팬-아웃 센서 패키지 및 이를 포함하는 카메라 모듈
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10950562B1 (en) 2018-11-30 2021-03-16 Hrl Laboratories, Llc Impedance-matched through-wafer transition using integrated heat-spreader technology
DE102018133344B4 (de) * 2018-12-21 2024-04-04 Infineon Technologies Ag Halbleiterpanels, halbleitergehäuse, und verfahren zu ihrer herstellung
WO2020150159A1 (en) 2019-01-14 2020-07-23 Invensas Bonding Technologies, Inc. Bonded structures
CN110061069A (zh) * 2019-04-30 2019-07-26 烟台艾睿光电科技有限公司 一种wlp器件封装产品
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11322428B2 (en) * 2019-12-02 2022-05-03 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
CN112331639B (zh) * 2020-09-28 2023-10-20 惠州市聚飞光电有限公司 用于制作led光源的基板及制作方法、led光源组件
US11557706B2 (en) * 2020-09-30 2023-01-17 Ford Global Technologies, Llc Additive manufacturing of electrical circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208478A (en) * 1990-04-13 1993-05-04 Grumman Aerospace Corp. Detector interface device
JPH08111587A (ja) * 1994-10-11 1996-04-30 Fujitsu Ltd 配線板構造及びその製造方法並びに半導体装置
JP3792445B2 (ja) * 1999-03-30 2006-07-05 日本特殊陶業株式会社 コンデンサ付属配線基板
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102412219A (zh) * 2010-09-22 2012-04-11 星科金朋有限公司 具有主动表面热移除的集成电路封装系统及其制造方法
CN103904062B (zh) * 2012-12-28 2017-04-26 欣兴电子股份有限公司 内埋式电子元件封装结构
CN103904062A (zh) * 2012-12-28 2014-07-02 欣兴电子股份有限公司 内埋式电子元件封装结构
CN104576575A (zh) * 2013-10-10 2015-04-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN104576575B (zh) * 2013-10-10 2017-12-19 日月光半导体制造股份有限公司 半导体封装件及其制造方法
TWI625839B (zh) * 2014-04-09 2018-06-01 Embedded chip manufacturing method
CN104332414B (zh) * 2014-04-09 2017-08-29 珠海越亚封装基板技术股份有限公司 嵌入式芯片的制造方法
CN104332414A (zh) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 嵌入式芯片的制造方法
CN106373947A (zh) * 2015-07-24 2017-02-01 英飞凌科技美国公司 鲁棒高性能半导体封装
CN106711094A (zh) * 2015-11-17 2017-05-24 Nepes株式会社 半导体封装件及其制造方法
CN106711094B (zh) * 2015-11-17 2020-01-10 Nepes株式会社 半导体封装件及其制造方法
CN110310895A (zh) * 2019-07-31 2019-10-08 中国电子科技集团公司第五十八研究所 一种埋入tsv转接芯片硅基扇出型三维集成封装方法及结构
CN110416091A (zh) * 2019-07-31 2019-11-05 中国电子科技集团公司第五十八研究所 一种硅基扇出型封装方法及结构
CN110310895B (zh) * 2019-07-31 2024-06-21 中国电子科技集团公司第五十八研究所 一种埋入tsv转接芯片硅基扇出型三维集成封装方法及结构
CN110416091B (zh) * 2019-07-31 2024-08-23 中国电子科技集团公司第五十八研究所 一种硅基扇出型封装方法及结构

Also Published As

Publication number Publication date
JP2008182225A (ja) 2008-08-07
US8178963B2 (en) 2012-05-15
CN101221936B (zh) 2012-01-11
SG144131A1 (en) 2008-07-29
DE102008003160A1 (de) 2008-07-17
TW200830499A (en) 2008-07-16
US20080157336A1 (en) 2008-07-03
KR20080064088A (ko) 2008-07-08
TWI357643B (en) 2012-02-01

Similar Documents

Publication Publication Date Title
CN101221936B (zh) 具有晶粒置入通孔之晶圆级封装及其方法
US10559525B2 (en) Embedded silicon substrate fan-out type 3D packaging structure
US8178964B2 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US7655501B2 (en) Wafer level package with good CTE performance
US7812434B2 (en) Wafer level package with die receiving through-hole and method of the same
TWI533412B (zh) 半導體元件封裝結構及其形成方法
US20080157358A1 (en) Wafer level package with die receiving through-hole and method of the same
EP3336893A1 (en) Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor
US20080237828A1 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
US20080083980A1 (en) Cmos image sensor chip scale package with die receiving through-hole and method of the same
CN101261984A (zh) 半导体组件封装结构及其方法
KR100517075B1 (ko) 반도체 소자 제조 방법
US20090321915A1 (en) System-in-package and manufacturing method of the same
KR20080077934A (ko) 축소된 구조를 갖는 멀티칩 패키지 및 그 형성 방법
US20080211075A1 (en) Image sensor chip scale package having inter-adhesion with gap and method of the same
US11842902B2 (en) Semiconductor package with alignment mark and manufacturing method thereof
CN101335265A (zh) 具有晶粒功能之半导体封装结构
TW200933844A (en) Wafer level package with die receiving through-hole and method of the same
CN115101482A (zh) 半导体封装结构及其形成方法
TW201011877A (en) Method for forming metal line and UBM in wafer level package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee after: Quncheng Energy Co.,Ltd.

Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee before: ADL Engineering Inc.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20231017

Address after: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee after: ADL Engineering Inc.

Address before: China Taiwan Hsinchu County Hukou Township Hsinchu Industrial Zone Guangfu Road North No. 65

Patentee before: Advanced Chip Engineering Technology Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240108

Address after: No. 8, Lixing 6th Road, Hsinchu City, Science Industrial Park, Hsinchu City, Taiwan, China, China

Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd.

Address before: Room 1002, 10th Floor, Hall 2, No. 321, Section 2, Guangfu Road, East District, Hsinchu, Taiwan, China, China

Patentee before: Quncheng Energy Co.,Ltd.

TR01 Transfer of patent right