TWI520231B - 半導體元件以及在膠封之後形成通過互連結構而接地的遮蔽層之方法 - Google Patents

半導體元件以及在膠封之後形成通過互連結構而接地的遮蔽層之方法 Download PDF

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TWI520231B
TWI520231B TW099113044A TW99113044A TWI520231B TW I520231 B TWI520231 B TW I520231B TW 099113044 A TW099113044 A TW 099113044A TW 99113044 A TW99113044 A TW 99113044A TW I520231 B TWI520231 B TW I520231B
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semiconductor
sealant
layer
interconnect structure
substrate
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TW099113044A
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TW201104761A (en
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池熺朝
趙南柱
申韓吉
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史達晶片有限公司
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Description

半導體元件以及在膠封之後形成通過互連結構而接地的遮蔽層之方法
本發明係概括為關於半導體元件，且尤指一種半導體元件以及在沉積膠封物(encapsulant)於半導體晶粒上之後安裝一遮蔽層以供隔離電磁干擾(EMI,electromagnetic interference)與射頻干擾(RFI,radio frequency interference)或其他元件間干擾之方法。遮蔽層係通過一種互連結構而接地。
半導體元件係常見於現代電子產品中。半導體元件係於電氣構件的數目與密度呈多樣化。離散的半導體元件係通常含有一個型式的電氣構件，例如：發光二極體(LED,light emitting diode)、小訊號電晶體、電阻器、電容器、電感器及功率(power)金屬氧化物半導體場效電晶體(MOSFET,metal oxide semiconductor field effect transistor)。積體的半導體元件典型地含有數百個到數百萬個電氣構件。積體的半導體元件之實例係包括：微控制器、微處理器、電荷耦合元件(CCD,charge-coupled device)、太陽能電池及數位微鏡元件(DMD,digital micro-mirror device)。
半導體元件係實行廣泛範圍的作用，諸如：高速計算、傳送及接收電磁訊號、控制電子元件、轉變陽光為電力及產生視覺投影以供電視顯像。半導體元件係可見於娛樂、通訊、功率轉換、網路、電腦及消費產品之領域。半導體元件係亦可見於軍事應用、航空、汽車、工業控制器、與辦公室設備。
半導體元件係開發半導體材料的電氣性質。半導體材料的原子結構藉由電場施加或透過摻雜過程而允許其導電性被操縱。摻雜引入雜質至半導體材料中以操縱及控制半導體元件的導電性。
一種半導體元件係含有主動與被動的電氣結構。主動結構(包括：雙極與場效電晶體)係控制電流之流通。藉由改變摻雜的程度及一電場或基極電流的施加，電晶體係促進或限制電流之流通。被動結構(包括：電阻器、電容器及電感器)係建立電壓與電流之間的一種關係，其為必要的以實行種種電氣作用。被動與主動結構係電氣連接以形成電路，其使半導體元件能夠實行高速計算與其他有用的作用。
半導體元件係通常運用二個複雜的製程所製造，即：前段(front-end)製造及後段(back-end)製造，各者可能涉及數百個步驟。前段製造係涉及於半導體晶圓表面的複數個晶粒之形成。各個晶粒係典型地相同且含有藉由電氣連接主動與被動構件所形成的電路。後段製造係涉及自所完成的晶圓以單一化個別的晶粒以及封裝該晶粒以提供結構支撐及環境隔離。
半導體製造之一個目標係產生較小的半導體元件。較小的元件係典型消耗較少的功率，具有較高的性能，且可為較有效率地生產。此外，較小的半導體元件係具有較小的使用空間，其為較小的最終產品所期望的。較小晶粒尺寸可藉由前段製程之改良以造成具有較小、較高密度的主動與被動構件之晶粒而達成。後段製程係可藉由電氣互連與封裝材料之改良而造成具有較小的使用空間之半導體元件封裝。
半導體製造之另一個目標係產生較高性能的半導體元件。於元件性能的提高可藉由形成能夠操作於較高速度之主動構件而達成。於高頻應用，諸如：射頻(RF,radio frequency)無線通訊，積體被動元件(IPD,integrated passive device)係經常包含於半導體元件之內。IPD之實例係包括：電阻器、電容器、與電感器。一種典型射頻系統係需要多個IPD於一或多個半導體封裝中以實行必要的電氣作用。然而，高頻的電氣元件產生或易於受到不期望的電磁干擾(EMI)、射頻干擾(RFI)或其他的元件間干擾，諸如：電容、電感、或電導耦合。
欲降低EMI、RFI、與其他的元件間干擾，可在半導體晶粒之上形成一遮蔽層。遮蔽層係典型地安裝於半導體晶粒之膠封前。膠封物係沉積在遮蔽層之上且透過於遮蔽層的孔或開口而被擠壓於遮蔽層與半導體晶粒之間的間隙以圍繞晶粒。然而，遮蔽層引起對於膠封物的均勻流動之障礙，其可能在半導體晶粒的周圍留下空隙。此外，遮蔽層係已知自膠封物剝離，此可能降低元件性能。
將半導體晶粒隔離EMI、RFI、與其他元件間干擾同時以膠封物將半導體晶粒密封為無空隙的需要係存在。因此，於一個實施例，本發明係一種製造半導體元件之方法，其步驟包含：提供含有一導電層之一基板；形成一焊接凸塊在基板上且電氣連接至導電層；安裝一半導體晶粒至基板；沉積一膠封物在半導體晶粒與焊接凸塊之上；形成一通道於膠封物內以暴露焊接凸塊；及，形成一遮蔽層在膠封物與半導體晶粒之上。該遮蔽層係延伸進入通道且電氣連接至焊接凸塊，以提供隔離元件間干擾。
於另一個實施例，本發明係一種製造半導體元件之方法，其步驟包含：提供含有一導電層之一基板；形成一互連結構在基板上且電氣連接至導電層；安裝一半導體構件至基板；沉積一膠封物在半導體構件與互連結構之上；形成一通道於膠封物內以暴露互連結構；及，形成一遮蔽層在膠封物與半導體構件之上。該遮蔽層係電氣連接至互連結構以提供隔離元件間干擾。
於另一個實施例，本發明係一種製造半導體元件之方法，其步驟包含：提供一基板；安裝一半導體構件至基板；沉積一膠封物在半導體構件之上；形成一通道於膠封物內；及，形成一遮蔽層在膠封物與半導體構件之上。
於另一個實施例，本發明係一種半導體元件，其包含：一基板，其含有一導電層。一互連結構係形成在基板之上且電氣連接至導電層。一半導體構件係安裝至基板。一膠封物係沉積在半導體構件與互連結構之上。一通道係形成於膠封物內以暴露互連結構。一遮蔽層係形成在膠封物與半導體構件之上。該遮蔽層係電氣連接至互連結構以提供隔離元件間干擾。
本發明係參考圖式而描述於下文說明的一或多個實施例，其中，同樣的參考符號係代表相同或類似元件。儘管本發明係依據用於達成本發明的目標之最佳模式而描述，將為熟悉此技術人士所理解的是：意圖以涵蓋如可被包含由隨附的申請專利範圍及下文之揭露與圖式所支持的其之等效者所界定之本發明的精神與範疇內的替代、修改及等效者。
半導體元件係通常運用二個複雜的製程所製造：前段製造與後段製造。前段製造係涉及於半導體晶圓表面的複數個晶粒之形成。於晶圓上的各個晶粒係含有主動與被動的電氣構件，其為電氣連接以形成作用的電路。主動電氣構件(諸如：電晶體)係具有控制電流之流通的能力。被動電氣構件(諸如：電容器、電感器、電阻器及變壓器)建立電壓與電流之間的一種關係，其為必要的以實行電路作用。
被動與主動構件係藉由包括摻雜、沉積、光微影、蝕刻及平坦化之一連串的處理步驟而形成於半導體晶圓的表面上。摻雜係藉由諸如離子植入或熱擴散之技術而引入雜質至半導體材料中。摻雜過程係修改於主動元件中之半導體材料的導電性，轉變半導體材料成為一種絕緣體、導體，或動態改變半導體材料的導電性以對電場或基極電流有所響應。電晶體含有變化型式與摻雜程度的範圍，隨著必要而配置以使電晶體能夠於電場或基極電流之施加時促進或限制電流的流通。
主動與被動構件係由具有不同的電氣性質之數層材料所形成。諸層可藉由種種沉積技術而形成，沉積技術某種程度上決定於所沉積的材料型式。舉例而言，薄膜沉積係可能涉及化學汽相沉積(CVD,chemical vapor deposition)、物理汽相沉積(PVD,physical vapor deposition)、電解電鍍及無電電鍍過程。各層係通常為圖案化以形成主動構件的部分、被動構件、或於構件之間的電氣連接。
諸層係可運用光微影技術而被圖案化，其係涉及光敏材料(如光阻)之沉積於將被圖案化之層上。一圖案係運用光線自一光罩轉移至光阻。運用一種溶劑移除受到光線影響之光阻圖案的部分所，暴露下層的部分以被圖案化。移除光阻的殘餘部分，留下一圖案化層。或者是，一些型式的材料藉由直接沉積材料至運用諸如無電及電解電鍍的技術之一種先前沉積/蝕刻過程所形成的區域或空隙而圖案化。
沉積一薄膜的材料於現存的圖案上可能擴大在下面的圖案且產生一不均勻平坦表面。需要一均勻平坦表面以產生較小且較密集封裝的主動與被動構件。平坦化可被用來移除晶圓表面的材料且產生一均勻平坦表面。平面化涉及以一拋光墊拋光晶圓表面。一種研磨材料與腐蝕化學製品係於拋光期間添加至晶圓表面。研磨料的機械作用與化學製品的腐蝕作用之結合以移除任何不規則的表面形狀，造成一均勻平坦表面。
後段製造係指將所完成的晶圓切割或單一化成為個別的晶粒且接著封裝該晶粒以供結構支撐與環境隔離。欲將晶粒單一化，晶圓係沿著稱為鋸道或劃線之晶圓的非作用區域而被刻劃及切斷。晶圓係運用一種雷射切割工具或鋸條而被單一化。在單一化之後，個別晶粒係安裝至一封裝基板，其包括接腳或接觸墊以供互連於其他的系統構件。形成在半導體晶粒之上的接觸墊係接著連接至於封裝內的接觸墊。電氣連接可藉著焊接凸塊、柱凸塊、導電糊膏、或接合線(wire bond)而作成。一種膠封物或其他的製模材料係沉積於封裝之上以提供物理的支撐與電氣隔離。完成的封裝係接著插入至一種電氣系統且該半導體元件的功能性被作成為可用於其他的系統構件。
圖1說明電子元件50，其具有一晶片載體基板或印刷電路板(PCB,printed circuit board) 52，印刷電路板52係具有安裝於其表面之複數個半導體封裝。電子元件50可具有一個型式的半導體封裝、或多個型式的半導體封裝，視應用而定。不同型式的半導體封裝係為了說明而顯示於圖1。
電子元件50可為一種獨立系統，其運用該等半導體封裝以實行一或多種電氣作用。或者是，電子元件50可為一較大系統的一個子構件。舉例而言，電子元件50可為一圖形卡、網路介面卡、或其可插入至電腦之其他的訊號處理卡。半導體封裝可包括：微處理器、記憶體、特定應用積體電路(ASIC,application specific integrated circuit)、邏輯電路、類比電路、射頻電路、離散元件或其他的半導體晶粒或電氣構件。
於圖1，PCB 52提供一種通用的基板以供安裝於PCB的半導體封裝之結構支撐及電氣互連。傳導訊號線跡54係運用蒸鍍、電解電鍍、無電電鍍、網印或其他適合金屬沉積過程而形成在PCB 52的一表面上或於PCB 52的諸層內。訊號線跡54提供各個半導體封裝、安裝構件、與其他外部系統構件之間的電氣連通。線跡54亦提供各個半導體封裝之電力與接地連接。
於一些實施例中，一種半導體元件係具有二個封裝階層(levels)。第一階層封裝係用於機械及電氣式附接半導體晶粒至一中間載體之一種技術。第二階層封裝係涉及：機械及電氣式附接中間載體至PCB。於其他實施例中，一種半導體元件係可僅具有第一階層封裝，其中，晶粒係直接為機械及電氣式安裝至PCB。
為了說明，數個型式的第一階層封裝係顯示於PCB 52，包括：接合線封裝56與覆晶晶片58。此外，數個型式的第二階層封裝係顯示安裝於PCB 52上，包括：球柵陣列(BGA,ball grid array) 60、塊形晶片載體(BCC,bump chip carrier) 62、雙列直插封裝(DIP,dual in-line package) 64、岸柵陣列(LGA,land grid array) 66、多晶片模組(MCM,multi-chip module) 68、四面扁平無引線封裝(QFN,quad flat non-leaded package) 70及四面扁平封裝72。視系統需求而定，任何組合的第一與第二階層封裝型式所構成之任何組合的半導體封裝、以及其他的電子構件係可連接至PCB 52。於一些實施例中，電子元件50係包括一單個附接的半導體封裝，而其他實施例係需要多個互連的封裝。藉由組合一或多個半導體封裝在單一個基板之上，製造業者可將事先作成的構件合併至電子元件及系統。因為半導體封裝係包括複雜的功能性，電子元件可運用較便宜的構件及一種有效率的製程所製造。造成的元件係較不可能失效且製造較不昂貴，對消費者而言導致較低的成本。
圖2a至2c係顯示示範性的半導體封裝。圖2a係說明安裝DIP 64於PCB 52之上的進一步細節。半導體晶粒74係包括一作用區域，作用區域含有類比或數位電路，其實施作為形成於晶粒之內且根據晶粒的電氣設計而電氣互連之主動元件、被動元件、傳導層及介電層。舉例而言，該電路係可包括一或多個電晶體、二極體、電感器、電容器、電阻器及形成於半導體晶粒74之作用區域內的其他電路元件。接觸墊76係一或多層的傳導材料，諸如：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，且為電氣連接至形成於半導體晶粒74之內的電路元件。於DIP 64之組裝期間，半導體晶粒74係運用一種金-矽的共熔層或諸如熱環氧化物的黏著材料而安裝至一中間載體78。封裝本體係包括一種絕緣封裝材料，諸如：聚合物或陶瓷。導體引線80與接合線82係提供半導體晶粒74與PCB 52之間的電氣互連。膠封物84係沉積在封裝之上藉由阻止濕氣與微粒進入封裝及污染晶粒74、或接合線82以供環境保護。
圖2b係說明安裝BCC 62於PCB 52上之進一步細節。半導體晶粒88係運用一種底部填充(underfill)或環氧樹脂的黏著材料92而安裝在載體90之上。接合線94係提供第一階層封裝以互連接觸墊96與98之間。製模化合物或膠封物100係沉積在半導體晶粒88與接合線94之上，以針對於該元件提供物理支撐及電氣隔離。接觸墊102係運用諸如電解電鍍或無電電鍍之一種適合金屬沉積法而形成在PCB 52之一表面上以防止氧化。接觸墊102係電氣連接至於PCB 52中之一或多個傳導訊號線跡54。焊接材料係沉積於BCC 62的接觸墊98與PCB 52的接觸墊102之間且回流以形成凸塊104，其形成BCC 62與PCB 52之間的機械及電氣連接。
於圖2c中，半導體晶粒58係以一種覆晶晶片型式的第一階層封裝而面朝下安裝至中間載體106。半導體晶粒58的作用區域108係含有類比或數位電路，其實施為根據晶粒的電氣設計而形成之主動元件、被動元件、傳導層、與介電層。舉例而言，電路可包括：一或多個電晶體、二極體、電感器、電容器、電阻器及於作用區域108之內的其他電路元件。半導體晶粒58係透過焊接凸塊或球110而電氣及機械式附接至載體106。
BGA 60係運用焊接凸塊或球112以一種BGA型式的第二階層封裝而電氣及機械式附接至PCB 52。半導體晶粒58係透過焊接凸塊110、訊號線114及焊接凸塊112而電氣連接至於PCB 52內之傳導訊號線跡54。一種製模化合物或膠封物116係沉積在半導體晶粒58與載體106之上，以針對於該元件提供物理支撐及電氣隔離。覆晶晶片式半導體元件提供一短的導電路徑自半導體晶粒58的主動元件至PCB 52的傳導軌跡，藉以縮小訊號傳播距離、降低電容、及改良整體電路性能。於另一個實施例中，半導體晶粒58係可運用覆晶晶片型式的第一階層封裝且無中間載體106而直接機械及電氣式附接至PCB 52。
圖3a至3h係說明一種形成半導體元件之方法，該種半導體元件係具有在膠封之後而安裝在半導體晶粒之上的一遮蔽層。於圖3a中，一基板或載體150含有底座材料，諸如：矽(Si)、金屬引線架、陶瓷、膠布或用於結構支撐之其他適合的堅固材料。一導電層152係運用藉著PVD、CVD、濺鍍、電解電鍍、無電電鍍過程、或其他適合金屬沉積過程之圖案化而形成於基板150之內。導電層152係可為一或多層之Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層152提供訊號線跡與接觸墊，其為電氣共接或電氣隔離，視該元件的作用設計而定。
一種導電焊接材料係運用一種蒸鍍、電解電鍍、無電電鍍、球滴、或網印過程而沉積在接觸墊152a之上。焊接材料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi及其之合金，其為一選用的熔化材料。舉例而言，焊接材料係可為共熔之Sn/Pb、高鉛或無鉛。焊接材料係藉由將材料加熱高於其熔點而回流以形成圓球或凸塊154。於一些應用中，焊接凸塊154係回流第二次以改良對於接觸墊152a之電氣連接。焊接凸塊154代表其可形成在接觸墊152a之上的一個型式的互連結構。互連結構係亦可運用傳導柱、柱凸塊、微凸塊或其他的電氣互連。
一個半導體晶粒或構件156係安裝在基板150之上且以焊接凸塊158電氣連接至導電層152b。一種選用的底部填充材料160係沉積於半導體晶粒156與基板150之間。半導體晶粒156係包括具有一作用區域之一基板，作用區域係含有類比或數位電路，其實施為形成於晶粒之內且根據晶粒的電氣設計與作用而電氣互連之主動元件、被動元件、傳導層及介電層。舉例而言，該電路可包括一或多個電晶體、二極體、與形成於其作用表面內的其他電路元件，以實施基頻的類比電路或數位電路，諸如：數位訊號處理器(DSP,digital signal processor)、ASIC、記憶體或其他訊號處理電路。半導體晶粒156亦可含有用於RF訊號處理之積體被動元件(IPD)，諸如：電感器、電容器與電阻器。半導體晶粒156係可為一種覆晶晶片型式的元件或接合線型式的元件。於另一個實施例中，一個離散構件可安裝在導電墊152b之上且電氣連接至導電墊152b。
於半導體晶粒156中之IPD提供針對於高頻應用所需的電氣特性，諸如：共振器、高通濾波器、低通濾波器、帶通濾波器、對稱高品質(Hi-Q)共振變壓器、匹配網路以及調諧電容器。IPD可用來作為前端的無線RF構件，其可被定位於天線與收發器之間。電感器可為操作於高達100千兆赫茲(GHz)之一種高品質(hi-Q)的平衡-不平衡轉換器(balun)、變壓器或線圈。於一些應用中，多個平衡-不平衡轉換器係形成於同一個基板，允許多頻帶的操作。舉例而言，二或多個平衡-不平衡轉換器係運用於針對於行動電話或其他的全球行動通訊系統(GSM,global system for mobile communication)之一四頻帶(quad-band)，各個平衡-不平衡轉換器係專用於四頻帶元件之一個頻帶的操作。
一種典型RF系統係需要於一或多個半導體封裝中之多個IPD與其他高頻電路以實行必要的電氣作用。高頻電氣元件產生或易受到不期望的EMI、RFI、或其他元件之間干擾的影響，諸如：電容、電感或傳導耦合，亦習稱為串音(cross-talk)，其可能干擾相鄰或附近的電路元件之操作。
圖3c係顯示一種膠封物或模製化合物162，其運用一種糊膏印製、壓縮模製、轉移模製、液體膠封物模製、真空疊合或其他適合的塗抹器而沉積在載體150、半導體晶粒156之上且環繞焊接凸塊158。膠封物162可為聚合物複合材料，諸如：具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或具有適當填料的聚合物。膠封物162係非傳導性且環境保護半導體元件免於外部元件與污染物的影響。
膠封物162的一部分以研磨機164移除，以平面化半導體晶粒156具有背側的表面。或者是，膠封物162的體積沉積係受一厚度所控制，其對應於半導體晶粒156的背側為平面的。
膠封物162的另一部分係運用一鋸條、薄膜輔助模製(FAM,film assist molding)或雷射剝蝕移除以形成一溝槽或通道168。通道168朝下延伸至焊接凸塊154。圖3e顯示藉由FAM所形成圖3d之結構的俯視圖。圖3f顯示藉由一鋸條實行部分切割所形成的一種替代結構。焊接凸塊154係被形成環繞於半導體晶粒156。一導電層170係運用藉著PVD、CVD、濺鍍、電解電鍍、無電電鍍過程、或其他適合金屬沉積過程之圖案化而形成於通道168之內。導電層170可為一或多層之Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料。或者，導電層170為部分填充通道168之一導電糊膏。導電層170係電氣連接至焊接凸塊154。
於圖3g，一種導電焊接材料係運用一種蒸鍍、電解電鍍、無電電鍍、球滴、或網印過程而沉積在接觸墊152c之上。焊接材料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi以及其之合金，其為一選用的熔化材料。舉例而言，焊接材料係可為共熔Sn/Pb、高鉛或無鉛。焊接材料藉由將材料加熱高於其熔點而回流以形成圓球或凸塊176。於一些應用中，焊接凸塊176係回流第二次以改良對於接觸墊152c之電氣連接。焊接凸塊176代表可被形成在接觸墊152c之上的一個型式的互連結構。互連結構亦可運用傳導柱、柱凸塊、微凸塊、或其他的電氣互連。
欲降低元件間干擾，一遮蔽層172係以黏著層173而形成或安裝在膠封物162與半導體晶粒156之上。遮蔽層172可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI、與其他元件之間干擾的其他金屬與複合物。遮蔽層172亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層172係電氣連接至導電層170且熱接觸半導體晶粒156的背側。遮蔽層172係透過導電層152與170及焊接凸塊154與176而電氣連接至一低阻抗的接地點。一去角區域174可被形成於環繞遮蔽層172的周邊。一種熱介面材料可在形成遮蔽層172之前被施加至半導體晶粒156的背表面。熱介面材料係有助於將半導體晶粒156所產生的熱之分佈及消散穿過遮蔽層172。
圖3h係透過通道168之遮蔽層172的部分所取得的橫截面圖。由於膠封物162係在遮蔽層172之前而沉積，遮蔽層係未引起在半導體晶粒156之上的膠封物162之流動的任何障礙。如於先前技術所得知無任何的空隙係形成於膠封物內。遮蔽層172係較可靠且較不可能自膠封物剝離。遮蔽層172具有可靠的接合以連接於外部接地點。
一個替代實施例係顯示於圖4。在圖3c之後，溝槽或通道168係形成於膠封物162之中且接著為完全填充導電糊膏180。遮蔽層182係以黏著層183形成或安裝在膠封物162與半導體晶粒156的平坦表面之上。遮蔽層182可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI、與其他元件間干擾的其他金屬與複合物。遮蔽層182亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層182係電氣連接至導電糊膏180且熱接觸半導體晶粒156的背側。遮蔽層182係透過導電層152與180及焊接凸塊154與176而電氣連接至一低阻抗的接地點。
於另一個實施例，在圖3d之後，一較深的溝槽或通道188係切割進入焊接凸塊154中，如於圖5a所示。遮蔽層190係形成或安裝在膠封物162與半導體晶粒156的平坦表面之上。遮蔽層190係具有對接銷194用於鎖入焊接凸塊154以形成一可靠的連接。遮蔽層190可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI及其他元件間干擾的其他金屬與複合物。遮蔽層190亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層190係透過通道188而電氣連接至焊接凸塊154且熱接觸半導體晶粒156的背側。遮蔽層190係透過導電層152及焊接凸塊154與176而電氣連接至一低阻抗的接地點。一去角區域198可被形成於環繞遮蔽層190的周邊。一種熱介面材料可在形成遮蔽層190之前施加至半導體晶粒156的背表面。熱介面材料係有助於將半導體晶粒156所產生的熱量之分佈及消散跨越遮蔽層190。
圖5b係穿過於通道188中之對接銷194所取得的橫截面圖。由於膠封物162係在遮蔽層190之前沉積，遮蔽層係未引起在半導體晶粒156之上的膠封物162之流動的任何障礙。如於先前技術所得知無任何的空隙係形成於膠封物中。遮蔽層190係較可靠且較不可能自膠封物而剝離。遮蔽層190係具有可靠的接合以連接於外部接地點。
於另一個實施例中，在圖3d之後，一遮蔽層200係藉由噴灑塗覆、無電電鍍、或電鍍而保角式地施加在半導體晶粒156與膠封物162之上且進入通道168，如於圖6a所示。遮蔽層200可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂、及能夠阻斷或吸收EMI、RFI及其他元件間干擾的其他金屬與複合物。遮蔽層200係亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層200係電氣連接至焊接凸塊154且熱接觸半導體晶粒156的背側。遮蔽層200係透過導電層152及焊接凸塊154與176而電氣連接至一低阻抗的接地點。保角式的遮蔽層200係作用為針對於半導體晶粒156所產生的熱量之分佈及消散的一種散熱器。
圖6b係穿過於通道168中之遮蔽層200所取得的橫截面圖。由於膠封物162係在遮蔽層200之前而沉積，遮蔽層係未引起在半導體晶粒156之上的膠封物162之流動的任何障礙。如於先前技術所得知無任何的空隙係形成於膠封物中。遮蔽層200係較可靠且較不可能自膠封物而剝離。遮蔽層200係具有可靠的接合連接於外部接地點。
圖7a與7b說明一種形成半導體元件之替代方法，該種半導體元件具有在膠封之後而安裝在半導體晶粒上的一遮蔽層。於圖7a中，一基板或載體210係含有底座材料，諸如：矽、金屬引線架、陶瓷、膠布或用於結構支撐之其他適合的堅固材料。一導電層212係運用藉著PVD、CVD、濺鍍、電解電鍍、無電電鍍過程或其他適合金屬沉積過程之圖案化而形成於基板210之內。導電層212可為一或多層之Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層212係提供用於電氣互連之訊號線跡與接觸墊，其為電氣共接或電氣隔離，視該元件的作用設計而定。
一種導電焊接材料係運用一種蒸鍍、電解電鍍、無電電鍍、球滴或網印過程而沉積在接觸墊212a之上。焊接材料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi及其之合金，其為一選用的熔化材料。舉例而言，焊接材料係可為共熔Sn/Pb、高鉛、或無鉛。焊接材料係藉由將材料加熱高於其熔點而回流以形成圓球或凸塊214。於一些應用中，焊接凸塊214係回流第二次以改良對於接觸墊212a之電氣連接。焊接凸塊214代表可形成在接觸墊212a上之一個型式的互連結構。互連結構亦可運用傳導柱、柱凸塊、微凸塊或其他的電氣互連。
複數個半導體晶粒或構件216係配置在基板210之上且以焊接凸塊218而電氣連接至導電層212b，如於圖7b所示。一種選用式的底部填充材料220係沉積於半導體晶粒216與基板210之間。半導體晶粒216係包括其具有一作用區域之一基板，作用區域係含有類比或數位電路，其實施為形成於晶粒之內之主動元件、被動元件、傳導層及介電層且根據晶粒的電氣設計與作用而電氣互連。舉例而言，該電路係可包括一或多個電晶體、二極體及形成於其作用表面內的其他電路元件，以實施基頻的類比電路或數位電路，諸如：DSP、ASIC、記憶體或其他訊號處理電路。半導體晶粒216係亦可含有用於RF訊號處理之IPD，諸如：電感器、電容器及電阻器。半導體晶粒216係可為一種覆晶晶片型式的元件或接合線型式的元件。於另一個實施例中，一個離散構件可被安裝在導電墊212b之上且電氣連接至導電墊212b。
於半導體晶粒216中之IPD係提供針對高頻應用所需的電氣特性，諸如：共振器、高通濾波器、低通濾波器、帶通濾波器、對稱高品質的共振變壓器、匹配網路及調諧電容器。IPD可運用作為前端的無線RF構件，其可定位於天線與收發器之間。電感器可為操作於高達100千兆赫茲(GHz)之一種高品質的平衡-不平衡轉換器、變壓器、或線圈。於一些應用中，多個平衡-不平衡轉換器係形成於同一個基板，允許多頻帶的操作。舉例而言，二或多個平衡-不平衡轉換器係運用於行動電話或其他的全球行動通訊系統(GSM)之一四頻帶，各個平衡-不平衡轉換器係專用於四頻帶元件之一個頻帶的操作。
一種典型RF系統係需要於一或多個半導體封裝中之多個IPD與其他高頻電路以實行必要的電氣作用。高頻電氣元件產生或易受到不期望的EMI、RFI、或其他元件間干擾之影響，諸如：電容、電感、或傳導耦合，亦習稱為串音，其可能干擾相鄰或附近的電路元件之操作。
一種膠封物或模製材料222係運用一種糊膏印製、壓縮模製、轉移模製、液體膠封物模製、真空疊合或其他適合之塗抹器而沉積在載體210、半導體晶粒216之上且環繞焊接凸塊218。膠封物222可為聚合物複合材料，諸如：具有填料的環氧樹脂、具有填料的環氧丙烯酸酯、或具有適當填料的聚合物。膠封物222係非傳導性且環境保護半導體元件免於外部元件與污染物的損害。
膠封物222的一部分係移除，以平面化半導體晶粒216之具有一背側的表面。或者是，膠封物222的體積沉積係受一厚度所控制，其應於半導體晶粒216的背側為平面的。
膠封物222的另一部分係運用一鋸條或薄膜輔助模製(FAM)移除以形成其朝下至焊接凸塊214之溝槽或通道228。圖7b顯示在安裝遮蔽層之前由FAM所形成結構的俯視圖。焊接凸塊214係形成環繞每一個半導體晶粒216。一導電層230係運用藉著PVD、CVD、濺鍍、電解電鍍、無電電鍍過程或其他適合金屬沉積過程之圖案化而形成於通道228之內。導電層230可為一或多層之Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。或者是，導電層230係一導電糊膏其部分填充通道228。導電層230係電氣連接至焊接凸塊214。
一種導電焊接材料係運用一種蒸鍍、電解電鍍、無電電鍍、球滴、或網印過程而沉積在接觸墊212c之上。焊接材料可為任何的金屬或導電材料，例如：Sn、Ni、Au、Ag、Pb、Bi及其之合金，其為一選用的熔化材料。舉例而言，焊接材料可為共熔Sn/Pb、高鉛、或無鉛。焊接材料係藉由將材料加熱高於其熔點而回流以形成圓球或凸塊236。於一些應用中，焊接凸塊236係回流第二次以改良對於接觸墊212c之電氣連接。焊接凸塊236代表其可形成在接觸墊212c之上的一個型式的互連結構。互連結構係亦可運用傳導柱、柱凸塊、微凸塊、或其他的電氣互連。
欲降低元件間干擾，一遮蔽層232係形成或安裝在膠封物222與半導體晶粒216的平坦表面之上。遮蔽層232可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI及其他元件間干擾的其他金屬與複合物。遮蔽層232亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層232係電氣連接至導電層230且熱接觸半導體晶粒216的背側。遮蔽層232係透過導電層212與230及焊接凸塊214與236而電氣連接至一低阻抗的接地點。
於圖7a與7b之另一個實施例中，一較深的通道238係切割進入焊接凸塊214，如於圖8所示。遮蔽層240係形成或安裝至膠封物222與半導體晶粒216之上。遮蔽層240具有用於鎖入焊接凸塊214之對接銷244以形成一可靠的連接。遮蔽層240可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI與其他元件間干擾的其他金屬與複合物。遮蔽層240亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層240係透過通道238而電氣連接至焊接凸塊214且熱接觸半導體晶粒216的背側。遮蔽層240係透過導電層212及焊接凸塊214與236而電氣連接至一低阻抗的接地點。
於圖7a與7b之另一個實施例中，一遮蔽層246係藉由噴灑塗覆、無電電鍍、或電鍍而保角式施加在半導體晶粒216與膠封物222之上且進入通道228，如於圖9所示。遮蔽層246可為Cu、Al、鐵氧體或羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、箔片、環氧化物、傳導樹脂及能夠阻斷或吸收EMI、RFI與其他元件間干擾的其他金屬與複合物。遮蔽層246係亦可為一非金屬材料，諸如：碳黑或鋁薄片，以降低EMI與RFI的效應。遮蔽層246係電氣連接至焊接凸塊214且熱接觸半導體晶粒216的背側。遮蔽層246係透過導電層212及焊接凸塊214與236而電氣連接至一低阻抗的接地點。保角式的遮蔽層246係作用為針對於半導體晶粒216所產生的熱量之分佈及消散的一種散熱器。
儘管本發明之一或多個實施例係已經詳細說明，熟悉此技術人士係將理解的是：對於該些實施例的修改與調適可為之而未脫離如以下申請專利範圍所陳述之本發明的範疇。
50．．．電子元件
52．．．印刷電路板(PCB)
54．．．線跡
56．．．接合線封裝
58．．．覆晶晶片
60．．．球柵陣列
62．．．塊形晶片載體
64．．．雙列直插封裝
66．．．岸柵陣列
68．．．多晶片模組
70．．．四面扁平無引線封裝
72．．．四面扁平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導體引線
82．．．接合線
84．．．膠封物
88．．．半導體晶粒
90．．．載體
92．．．底部填充或環氧樹脂黏著材料
94．．．接合線
96、98．．．接觸墊
100．．．模製化合物或膠封物
102．．．接觸墊
104．．．凸塊
106．．．載體
108．．．作用區域
110、112．．．焊接凸塊或球
114．．．訊號線
116．．．模製化合物或膠封物
150．．．基板或載體
152．．．導電層
152a-152c．．．接觸墊/導電層
154．．．圓球或凸塊(焊接凸塊)
156．．．半導體晶粒或構件
158．．．焊接凸塊
160．．．底部填充材料
162．．．膠封物
164．．．研磨機
168．．．溝槽或通道
170．．．導電層
172．．．遮蔽層
173．．．黏著層
174．．．去角區域
176．．．焊接球或凸塊
180．．．導電糊膏
182．．．遮蔽層
183．．．黏著層
188．．．凹槽或通道
190．．．遮蔽層
194．．．對接銷
198．．．去角區域
200．．．遮蔽層
210．．．基板或載體
212．．．導電層
212a-c．．．接觸墊/導電層
214．．．焊接球或凸塊
216．．．半導體晶粒或構件
218．．．焊接凸塊
220．．．底部填充材料
222．．．膠封物或模製化合物
228．．．凹槽或通道
230．．．導電層
232．．．遮蔽層
236．．．焊接球或凸塊
238．．．通道
240．．．遮蔽層
244．．．對接銷
246．．．遮蔽層
圖1係說明一PCB具有不同型式的封裝安裝於其表面；
圖2a至2c係說明安裝於PCB的代表的半導體封裝之進一步細節；
圖3a至3h係說明一種在膠封之後形成通過焊接凸塊而接地的遮蔽層在半導體晶粒上之方法；
圖4係說明安裝在半導體晶粒上且通過焊接凸塊而接地的遮蔽層；
圖5a與5b係說明遮蔽層安裝至具有對接銷之焊接凸塊；
圖6a與6b係說明保角式施加在膠封物與半導體晶粒上的遮蔽層；
圖7a與7b係說明安裝在複數個半導體晶粒上的遮蔽層；
圖8係說明遮蔽層安裝至具有對接銷之焊接凸塊；及
圖9係說明保角式施加在膠封物與半導體晶粒上的遮蔽層。
150．．．基板或載體
152、170．．．導電層
152a、152c．．．接觸墊/導電層
154、176．．．圓球或凸塊焊接凸塊
162．．．膠封物
168．．．溝槽或通道
172．．．遮蔽層
174．．．去角區域

Claims (15)

  1. 一種製造半導體元件之方法，其包含：提供一基板，其包含一凸塊形成在該基板之上並且一半導體構件被安置於該基板之上；沉積一膠封物在該半導體構件與凸塊之上；平坦化該膠封物以及該半導體構件之一非主動表面同時留下該膠封物在該凸塊之上；及形成一通道於該膠封物之中，該通道向下延伸穿過該膠封物並且進入該凸塊，該通道穿過該膠封物而環繞該半導體構件。
  2. 如申請專利範圍第1項之方法，進一步包括：形成一遮蔽層在該膠封物與半導體構件之上，該遮蔽層包含延伸該凸塊之一對接銷而電氣連接至該凸塊以提供隔離元件間干擾。
  3. 如申請專利範圍第2項之方法，進一步包括：形成環繞該遮蔽層之一去角區域。
  4. 如申請專利範圍第1項之方法，其中該凸塊係包括一焊接凸塊、柱凸塊或微凸塊。
  5. 如申請專利範圍第2項之方法，進一步包括：保角式施加該遮蔽層在該膠封物與半導體晶粒之上且進入該通道。
  6. 一種製造半導體元件之方法，其包含：沉積一膠封物在一互連結構以及一半導體構件之上，該互連結構和該半導體構件被安置在一基板之上；形成一通道部分地穿過該膠封物並且到達該互連結 構，該通道向下延伸穿過該膠封物至該互連結構，該通道延伸部分地穿過該膠封物而環繞該半導體構件；及形成一遮蔽層在該膠封物之上，該遮蔽層電氣連接至該互連結構。
  7. 如申請專利範圍第6項之方法，進一步包括：形成該互連結構在該基板之上且電氣連接至該基板內的一導電層，該遮蔽層係電氣連接至該互連結構。
  8. 如申請專利範圍第6項之方法，進一步包括：在形成該遮蔽層之前，沉積焊接材料焊劑糊於該通道之中。
  9. 如申請專利範圍第6項之方法，進一步包括：保角式施加該遮蔽層在該膠封物與半導體構件之上且進入該通道。
  10. 如申請專利範圍第6項之方法，進一步包括：散佈由該半導體構件所產生的熱量跨過該遮蔽層。
  11. 一種半導體元件，其包含：一基板；一互連結構，其安置在該基板之上；一半導體構件，其安裝至該基板；一膠封物，其沉積在該半導體構件與互連結構之上並且環繞該半導體構件與互連結構；一通道，其被形成部分地穿過該膠封物並且向下延伸至該互連結構，該通道延伸環繞該半導體構件；及一遮蔽層，其形成在該膠封物與半導體構件之上，該遮蔽層係電氣連接至該互連結構以提供隔離元件間干擾。
  12. 如申請專利範圍第11項之半導體元件，進一步包 括：一去角區域，其形成環繞該遮蔽層的周邊。
  13. 如申請專利範圍第11項之半導體元件，進一步包括：一對接銷，其安置於該遮蔽層上，該對接銷延伸進入該通道且電氣連接至該互連結構。
  14. 如申請專利範圍第11項之半導體元件，其中，該遮蔽層係保角式施加在該膠封物與半導體構件之上且進入該通道。
  15. 如申請專利範圍第11項之半導體元件，進一步包括：一導電層，安置於該基板中，該互連結構電氣連接至該導電層。
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