JPH08250890A - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPH08250890A
JPH08250890A JP7049642A JP4964295A JPH08250890A JP H08250890 A JPH08250890 A JP H08250890A JP 7049642 A JP7049642 A JP 7049642A JP 4964295 A JP4964295 A JP 4964295A JP H08250890 A JPH08250890 A JP H08250890A
Authority
JP
Japan
Prior art keywords
electrode
frame
integrated circuit
mounting
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7049642A
Other languages
English (en)
Inventor
Hidenori Egawa
秀範 江川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7049642A priority Critical patent/JPH08250890A/ja
Priority to US08/613,136 priority patent/US5821604A/en
Publication of JPH08250890A publication Critical patent/JPH08250890A/ja
Pending legal-status Critical Current

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

(57)【要約】 【目的】平板型で裏面にアレー状の電極を有する混成集
積回路装置に於いて、実装後に生じるマザーボードとの
隙間から輻射ノイズが漏れるのを防ぐ。 【構成】裏面の凸型電極４と同一平面内に、該凸型電極
４の一部もしくは全部を取り囲む枠状凸型電極５を設け
ておくとともに、マザーボード１３の対向位置に枠状凸
型電極を含む搭載用ランドパターン１６を設けておき、
実装時に該部分を含めた半田接続を行う。これにより、
実装後に生じるマザーボードとの隙間から輻射ノイズが
漏れるのを防ぐ。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体装置に関し、特
に表面実装用ＩＣパッケージに電磁波のシールド構造を
有する混成集積回路装置に関する。
【０００２】
【従来の技術】従来の裏面に電極を有するタイプの混成
集積回路装置は、図３（ａ）に示すように、例えば半田
ボール等をアレー状に配された電極パターンに取り付け
ることで凸型電極４を形成していた。特に、電磁波のシ
ールドを目的とした場合には、パッケージの側面をすべ
てメッキ処理することにより、側面シールド壁３を設
け、ＩＣチップ７を搭載して封止した凹部６上には金属
プレートもしくは導体ペースト印刷による上部シールド
層８を設けていた。
【０００３】尚、高レベルの電磁波のシールド効果を得
る別の手段としてはパッケージ全体を覆うような別個の
金属ケースを取り付ける方法や、ＩＣチップ自体をマザ
ーボードに埋め込み、マザーボードの表面及び裏面にシ
ールド層を設ける方法があった。
【０００４】
【発明が解決しようとする課題】この従来の混成集積回
路装置では、図３（ｂ）に示すように、マザーボードへ
の実装後に、パッケージ本体１とマザーボード１３の間
にギャップ１５が生じる。該ギャップ１５は、約０．１
〜０．５ｍｍ程度のわずかなものであるが、凸型電極４
部からの電磁波が抜け出すのは容易であり、パッケージ
外部の自由空間へ輻射ノイズとなって出ていく。一般に
電磁波は、そのエネルギーが熱にかわるかもしくは、再
度配線パターンに吸収されて伝導ノイズに変らない限
り、誘電率の異なる堺面で反射を繰り返し、極僅かの隙
間から外部へ漏れる。側面シールド壁３及び上部シール
ド層８によってある程度の極部的な効果は得られるが、
パッケージ全体としては、−５〜−１０ｄＢ程度のノイ
ズ低減に留まっていた。
【０００５】また、金属ケースを用いた場合、装置の重
量が増す、実装工程が増える、実装スペースが余計に必
要となるという問題があり、マザーボードにＩＣチップ
を埋め込む場合には、原理的に、不具合時のリプレース
は極めて困難となるという問題があった。
【０００６】近年の電子デバイスの高速化、高密度化の
傾向により、輻射ノイズの問題は非常に深刻化してお
り、要求されるシールド効果のレベルも上昇して来てい
る。本発明の混成集積回路装置の目的は、パッケージ自
体は小型・薄型・軽量の表面実装タイプでありながら、
シールド性能は、金属ケースもしくはマザーボードへの
ＩＣチップ埋め込みによる場合と同等のレベルを有する
パッケージを提供することにある。
【０００７】
【課題を解決するための手段】本発明によれば、基板の
両主面の少なくともいずれか一方の面に電極を有し、か
つ電極と同一平面内に電極の一部もしくは全部を取り囲
む枠状の電極を１箇所以上設けた混成集積回路装置が得
られる。
【０００８】また、基板側面にシールド電極を有し、枠
状の電極がシールド電極と接続されている混成集積回路
装置及び枠状電極が他の基板（マザーボード）に接着さ
れ、前述の電極が封止されている混成集積回路装置が得
られる。
【０００９】
【実施例】次に本発明について図を参照して説明する。
【００１０】図１（ａ）は本発明の混成集積回路装置の
断面図及び（ｂ）上面図、図１（ｃ）は図１（ａ）の半
導体装置をマザーボードに実装した際の拡大断面図であ
る。
【００１１】この半導体装置の製造に当っては、まず、
パッケージ本体１となる基板作成の段階に於いて、スル
ーホールメッキ工程と同プロセスにより基板側面部に
も、無電解メッキを施して、例えば１０〜２０μｍ厚の
側面シールド壁３を同時に形成し、裏面電極パターン形
成後に、該部に不要部をレジストでマスクした上で選択
的な電解メッキによる厚メッキを施して、例えば０．２
〜０．３ｍｍ程度の凸型電極４及び枠状凸型電極５を同
時に形成する。さらに、基板上部からＩＣを搭載する凹
部６をルーター等により削り出し加工により形成すると
ともに、内部導体層１２を露出させる。
【００１２】次に、凹部６にＩＣチップ７をマウント
し、Ａｎ等のワイヤー１１によって内部導体層１２との
電気的接続を図り、凹部６内をエポキシ系樹脂により封
止・キュアする。尚、凹部６は樹脂で封止しない場合も
ある。しかる後、封止済の凹部６の上部の封止面と、こ
の封止面と同一平面上にある側面シールド壁３に接続す
る導体パターンとの両方を覆う範囲に、例えば２０μｍ
厚の導体ペーストを印刷し、例えば１５０°３０分程度
でキュアすることにより、上部シールド層８を形成す
る。さらに、必要に応じて上部シールド層８の上部に例
えば２０μｍ厚の保護レジスト膜９を印刷し、例えば１
５０°１０分程度でキュアすることにより設ける。
【００１３】一方、混成集積回路装置を搭載すべきマザ
ーボード１３には、図２に示すように凸型電極４及び枠
状凸型電極５の両方に対向する位置に、搭載用ランドパ
ターン１６を設けておく。その際、搭載用ランドパター
ン１６の枠状凸型電極５に対向する部分は周囲のマザー
ボード側のシールドパターン１７に隙間なく接続されて
いなければならない。実装時には、搭載用ランドパター
ン１６に沿った半田スクリーンを使用して、半田ペース
トを印刷し、リフローにより搭載する。尚、必要に応じ
て、リフロー時に膨張したガスを外部に抜く為の貫通穴
１８をマザーボード側に設けておく。
【００１４】また、本発明に第２の実施例としては、特
に図には示さないが、枠状凸型電極５を連続した一定幅
の閉曲線ではなく、所々断続的に止切れる部分を設けた
り、壁の厚みを変化させても良い。この場合、前記不連
続部分に溶融直後の半田が保持され、枠状凸型電極に沿
った半田の移動がより起りにくくなり、実装時の半田量
の均一性をより高められるという効果がある。この時実
装後に止切れた部分等が半田に充填されて、最終的に枠
状の電極が内部を密閉するようになった方が好ましい。
また、枠状電極は必らずしも全ての電極を囲む必要は無
く、検査用電極等、外部に出しておいた方が便利なもの
は出しておくと良い。更に、用途に応じて枠状電極を分
割したり、複数設けることもできる。凸型電極は、シー
ルドパターンやレジスト膜等の膜厚合計が３０〜６０μ
ｍ程度になることから、０．１ｍｍ以上あることが望ま
しく、また、接続の安定性から１ｍｍ以下にすることが
望ましい。それより高くなると、半田の接着不良が生じ
たり、接着後もはがれ易かったりすることが判明した。
更に、枠状の電極の幅は、内側の凸型電極の幅と同程度
かそれ以下であることが小型化の点で好ましい。
【００１５】
【発明の効果】以上説明したように、本発明の半導体装
置は、裏面の凸型電極の同一平面内に、凸型電極の一部
もしくは全部を取り囲む枠状の凸型電極を設けた為、マ
ザーボードへの実装時に、枠状凸型電極をも含めた半田
接続によって、パッケージ本体と、マザーボード間に生
ずるギャップからの輻射ノイズをほぼ完全に遮蔽出来、
側面シールド壁や上部シールド層と一体となって、パッ
ケージ全体としても、−２０ｄＢを越えるシールド効果
が得られる。
【００１６】また、枠状凸型電極は、凸型電極と同プロ
セスで一括型成が可能である為、新たなプロセスの追加
もなく実現出来、しかもパッケージ自体がほぼ完全なシ
ールド構造を有している為、別個に金属ケースを取り付
けるような実装時の追加工程も発生しないという効果も
ある。従って、金属ケースを用いた場合に生ずる重量の
増加、新たなスペースの確保も不要となる。
【００１７】また、本発明の半導体装置は、基本的に
は、半田接続による表面実装用の独立したＩＣパッケー
ジである為、マザーボード実装後のリプリースも可能で
ある。従って、マザーボードにＩＣチップを直接埋め込
む場合と同等の高いレベルの電磁波のシールド効果とリ
プレースの容易性の両方と同時に実現している。
【００１８】さらに、本発明の混成集積回路装置に特有
の枠型凸電極は、裏面の導体マスク及びレジストマスク
の変更のみでその形状を自由にコントロール出来、レイ
アウトの自由度は非常に高い。例えば、同一平面内に複
数箇所設けたり、各凸電極毎に設けたり、自由曲線で設
けたりすることも可能である。
【００１９】尚、枠状凸型電極は、ＩＣチップを裏返し
て搭載する技術、いわゆるフリップチップの電極構造と
しても応用出来ることは勿論である。さらに、枠状凸型
電極５は、図１（ｃ）に示すような断面形状の特有の効
果として、その両側に半田１４を保持し、凸部を有さな
い平板なパターンのみの場合よりも格段に安定な、密封
状態を実現することを可能にしている。
【図面の簡単な説明】
【図１】（ａ）本発明の一実施例の背面図及び（ｂ）Ａ
−Ａ′における断面図（ｃ）本発明の一実施例のマザー
ボード実装時の詳細断面図。
【図２】パッケージ搭載前のマザーボード（ａ）平面図
（ｂ）Ｂ−Ｂ′における断面図。
【図３】（ａ）従来の一実施例の背面図及び（ｂ）Ｃ−
Ｃ′における断面図（ｃ）従来の一実施例のマザーボー
ド実装時の詳細断面図。
【符号の説明】
１ パッケージ本体 ２ 裏面シールドパターン ３ 側面シールド壁 ４ 凸型電極 ５ 枠状凸型電極 ６ 凹部 ７ ＩＣチップ ８ 上部シールド層 ９ 保護レジスト膜 １１ Ａｎワイヤー １２ 内部導体層 １３ マザーボード １４ 半田 １５ ギャップ １６ 搭載ランドパターン １７ マザーボード側シールドパターン １８ 貫通穴

Claims (4)

    【特許請求の範囲】
  1. 【請求項１】 基板の両主面の少なくともいずれか一方
    の面に凸型電極を有し、且つ、該凸型電極と同一平面内
    に該凸型電極の一部もしくは全部を取り囲む枠状の凸型
    電極を１箇所以上設けたことを特徴とする混成集積回路
    装置。
  2. 【請求項２】 前記基板側面にシールド電極を有し、前
    記枠状の凸型電極が前記シールド電極と接続されている
    ことを特徴とする請求項１記載の混成集積回路装置。
  3. 【請求項３】 前記枠状の凸型電極が他の基板に接着さ
    れ、前記電極が封止されていることを特徴とする請求項
    １記載の混成集積回路装置。
  4. 【請求項４】 前記枠状の凸型電極の高さが、０．１ｍ
    ｍ以上１ｍｍ以下であることを特徴とする請求項１記載
    の混成集積回路装置。
JP7049642A 1995-03-09 1995-03-09 混成集積回路装置 Pending JPH08250890A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7049642A JPH08250890A (ja) 1995-03-09 1995-03-09 混成集積回路装置
US08/613,136 US5821604A (en) 1995-03-09 1996-03-08 Integrated circuit device having shield structure against electromagnetic wave

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7049642A JPH08250890A (ja) 1995-03-09 1995-03-09 混成集積回路装置

Publications (1)

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JPH08250890A true JPH08250890A (ja) 1996-09-27

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Country Link
US (1) US5821604A (ja)
JP (1) JPH08250890A (ja)

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WO1998019338A1 (fr) * 1996-10-30 1998-05-07 Hitachi Chemical Company, Ltd. Substrat porteur de microplaquette pour conditionnement de semi-conducteur, dispositif a semi-conducteur et leur procede de fabrication
JP2001250873A (ja) * 2000-01-24 2001-09-14 Infineon Technologies Ag 防護装置および装置を有する電気的な構成素子
JP2005236169A (ja) * 2004-02-23 2005-09-02 Sony Corp 磁気シールド体、磁気シールド構造及び磁気メモリ装置
JP2012160578A (ja) * 2011-01-31 2012-08-23 Toshiba Corp 半導体装置
TWI416694B (zh) * 2010-09-17 2013-11-21 Powertech Technology Inc 全罩式屏蔽至接地銲球之晶片封裝構造
JP2014112743A (ja) * 2014-03-25 2014-06-19 Toshiba Corp 半導体装置
US9166298B2 (en) 2012-08-24 2015-10-20 Kabushiki Kaisha Toshiba Wireless device, and information processing apparatus and storage device including the wireless device

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US5888850A (en) * 1997-09-29 1999-03-30 International Business Machines Corporation Method for providing a protective coating and electronic package utilizing same
DE19806550B4 (de) * 1998-02-17 2004-07-22 Epcos Ag Elektronisches Bauelement, insbesondere mit akustischen Oberflächenwellen arbeitendes Bauelement - OFW-Bauelement
FR2790327B1 (fr) * 1999-02-26 2001-04-13 Commissariat Energie Atomique Systeme electronique fonctionnant sous irradiation, procede de conception d'un tel systeme, et application de celui-ci a la commande d'un robot mobile
US6297551B1 (en) * 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
JP4218193B2 (ja) * 2000-08-24 2009-02-04 三菱電機株式会社 パワーモジュール
FR2849346B1 (fr) * 2002-12-20 2006-12-08 Thales Sa Boitier hyperfrequence a montage de surface et montage correspondant avec un circuit multicouche.
EP1699277A4 (en) * 2003-12-26 2007-08-15 Murata Manufacturing Co CERAMIC MULTILAYER SUBSTRATE
JP2010166025A (ja) * 2008-12-19 2010-07-29 Panasonic Corp 実装構造
US11181688B2 (en) * 2009-10-13 2021-11-23 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
US8546921B2 (en) 2010-08-24 2013-10-01 Qualcomm Incorporated Hybrid multilayer substrate
TWI553817B (zh) * 2014-06-17 2016-10-11 瑞昱半導體股份有限公司 具有電磁防護功能之積體電路及其製造方法
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JPH05327163A (ja) * 1992-05-20 1993-12-10 Fujitsu Ltd 電子部品の実装構造

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Cited By (13)

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WO1998019338A1 (fr) * 1996-10-30 1998-05-07 Hitachi Chemical Company, Ltd. Substrat porteur de microplaquette pour conditionnement de semi-conducteur, dispositif a semi-conducteur et leur procede de fabrication
US6331729B1 (en) 1996-10-30 2001-12-18 Hitachi Chemical Company, Ltd. Chip supporting substrate for semiconductor package, semiconductor device, and method for manufacturing them
JP2001250873A (ja) * 2000-01-24 2001-09-14 Infineon Technologies Ag 防護装置および装置を有する電気的な構成素子
JP2005236169A (ja) * 2004-02-23 2005-09-02 Sony Corp 磁気シールド体、磁気シールド構造及び磁気メモリ装置
JP4742502B2 (ja) * 2004-02-23 2011-08-10 ソニー株式会社 磁気シールド体、磁気シールド構造及び磁気メモリ装置
TWI416694B (zh) * 2010-09-17 2013-11-21 Powertech Technology Inc 全罩式屏蔽至接地銲球之晶片封裝構造
JP2012160578A (ja) * 2011-01-31 2012-08-23 Toshiba Corp 半導体装置
US8860190B2 (en) 2011-01-31 2014-10-14 Kabushiki Kaisha Toshiba Semiconductor device
US8952505B2 (en) 2011-01-31 2015-02-10 Kabushiki Kaisha Toshiba Semiconductor device
US9123731B2 (en) 2011-01-31 2015-09-01 Kabushiki Kaisha Toshiba Semiconductor device
US9401333B2 (en) 2011-01-31 2016-07-26 Kabushiki Kaisha Toshiba Semiconductor device
US9166298B2 (en) 2012-08-24 2015-10-20 Kabushiki Kaisha Toshiba Wireless device, and information processing apparatus and storage device including the wireless device
JP2014112743A (ja) * 2014-03-25 2014-06-19 Toshiba Corp 半導体装置

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