TW201806042A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW201806042A
TW201806042A TW105124953A TW105124953A TW201806042A TW 201806042 A TW201806042 A TW 201806042A TW 105124953 A TW105124953 A TW 105124953A TW 105124953 A TW105124953 A TW 105124953A TW 201806042 A TW201806042 A TW 201806042A
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electronic package
carrier
shielding element
electronic
layer
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TW105124953A
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TWI618156B (zh
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簡岳盈
王維賓
李聰明
林恩立
鄭坤一
朱育德
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矽品精密工業股份有限公司
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Priority to TW105124953A priority Critical patent/TWI618156B/zh
Priority to CN201610688893.2A priority patent/CN107689364B/zh
Priority to US15/341,100 priority patent/US9997469B2/en
Publication of TW201806042A publication Critical patent/TW201806042A/zh
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Publication of TWI618156B publication Critical patent/TWI618156B/zh
Priority to US15/975,380 priority patent/US10396040B2/en

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Abstract

一種電子封裝件，係於承載件上設置複數電子元與一擋架，令該擋架位於相鄰兩電子元件之間，且以封裝層包覆該些電子元件並使該擋架之部分表面凸出該封裝層，又於該封裝層上形成電性連接該擋架之屏蔽元件，藉以提升電磁遮蔽之功效。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係關於一種電子封裝件，更詳言之，本發明係為一種能防止電磁干擾之電子封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，簡稱EMI)產生。
如第1A至1C圖所示，習知避免EMI之射頻(Radio frequency,RF)模組1係將複數射頻晶片11a,11b與非射頻式電子元件11電性連接在一基板10上，再以如環氧樹脂之封裝層13包覆各該射頻晶片11a,11b與該非射頻式電子元件11，並於該封裝層13上形成一金屬薄膜14。該射頻模組1藉由該封裝層13保護該射頻晶片11a,11b、非射頻式電子元件11及基板10，避免外界水氣或污染物之侵害，且藉由該金屬薄膜14保護該些射頻晶片11a,11b免受外界EMI影響。
惟，習知射頻模組1之外圍雖可藉由包覆該金屬薄膜 14以達到避免EMI之目的，但卻無法避免其內部各該射頻晶片11a,11b之間的電磁波干擾(EMI)，導致訊號容易發生錯誤。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
為解決上述習知技術之種種問題，本發明遂揭露一種電子封裝件，係包括：承載件；複數電子元件，係設於該承載件上；擋架，係設於該承載件上並位於相鄰兩電子元件之間；封裝層，係形成於該承載件上並包覆該些電子元件與該擋架，且令該擋架之部分表面係凸出該封裝層；以及屏蔽元件，係設於該封裝層上且接觸該擋架凸出該封裝層之部分表面。
本發明復提供一種電子封裝件之製法，係包括：於一承載件上設置複數電子元件與一擋架，且令該擋架位於相鄰兩電子元件之間；形成封裝層於該承載件上，以令該封裝層包覆該些電子元件與該擋架，並令該擋架之部分表面凸出該封裝層；以及於該封裝層上設置屏蔽元件，並令該屏蔽元件接觸該擋架凸出該封裝層之部分表面。
前述之製法，於形成該封裝層前，將離形膜覆蓋於該擋架上，且於形成該封裝層之後，移除該離形膜。
前述之電子封裝件及其製法，該電子元件係為主動元件、被動元件或封裝結構。
前述之電子封裝件及其製法，形成該擋架之材質係為 導電材。
前述之電子封裝件及其製法，該屏蔽元件係為以濺鍍方式形成於該封裝層上之導電層。或者，該屏蔽元件係為蓋設於該封裝層上之導電蓋。
另外，前述之電子封裝件及其製法，復包括形成絕緣包覆層以包覆該屏蔽元件。
由上可知，本發明電子封裝件及其製法，主要藉由在相鄰兩電子元件之間設有該擋架，且該擋架之部分表面凸出該封裝層，使該擋架凸出該封裝層之部分表面與該屏蔽元件相互接觸以作為屏蔽結構，故相較於習知技術，本發明之電子元件周圍均有屏蔽結構，因而不僅能防止該些電子元件之間的電磁波相互干擾，且能有效防止外界電磁波干擾該些電子元件之內部電路。
1‧‧‧射頻模組
10‧‧‧基板
11‧‧‧非射頻式電子元件
11a,11b‧‧‧射頻晶片
13,23‧‧‧封裝層
14‧‧‧金屬薄膜
2‧‧‧電子封裝件
20‧‧‧承載件
202‧‧‧銲球
20b‧‧‧底面
20c,23c‧‧‧側面
21a,21b‧‧‧電子元件
210‧‧‧封裝基板
211‧‧‧晶片
212‧‧‧銲線
213‧‧‧封裝材
22‧‧‧擋架
220‧‧‧凸出部
23a‧‧‧頂面
24‧‧‧屏蔽元件
25‧‧‧絕緣包覆層
30‧‧‧離形膜
31‧‧‧模具
第1A至1C圖係為習知射頻模組之製法之剖面示意圖；以及第2A至2D圖係為本發明之電子封裝件之製法之剖面示意圖；其中，第2B’圖係為第2B圖之構件之其中一種佈設方式之上視示意圖，第2C’圖係為第2C圖之其中一製程步驟之局部放大圖，第2C”圖係為第2B’圖之後續製程之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地 瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“頂”、“底”、“側”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
以下即配合第2A至2D圖詳細說明本發明之電子封裝件2之製法。
如第2A圖所示，提供一承載件20，並設置複數電子元件21a,21b於該承載件20上，其中，該些電子元件21a,21b係以複數銲球202電性連接該承載件20。
所述之承載件20係為核心式(core)或無核心式(coreless)線路板，其具有複數電性接觸墊(圖略)與至少一接地部(圖略)。於本實施例中，該承載件20之種類繁多，例如，該承載件20復具有至少一內部線路(圖略)，且該內部線路可選擇性地電性連接該電性接觸墊與該接地部。因此，該承載件20之構造並無特別限制。
再者，其中一電子元件21a係為封裝結構，而另一電 子元件21b係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。具體地，該電子元件21a具有電性連接該承載件20之封裝基板210及設於該封裝基板210上之晶片211，且該晶片211可藉由銲線212(或圖未示之銲錫凸塊)電性連接該封裝基板210，並以封裝材213包覆該晶片211與銲線212。
又，該電子元件21b係為覆晶式晶片，即藉由複數銲球202對應電性連接至該承載件20之電性接觸墊。應可理解地，該電子元件21b亦可為打線式晶片，即藉由複數銲線對應電性連接該承載件20之電性接觸墊。
另外，該電子元件21a,21b之態樣可為射屏(RF)模組，例如：無線區域網路(Wireless LAN，簡稱WLAN)、全球定位系統(Global Positioning System，簡稱GPS)、藍芽(Bluetooth)或手持式視訊廣播(Digital Video Broadcasting-Handheld，簡稱DVB-H)、調頻(FM)等無線通訊模組。
如第2B圖所示，設置至少一擋架22於該些電子元件22a,22b之間。
於本實施例中，形成該擋架22之材質為導電材，如銅、金、鎳或鋁等之金屬，且該擋架22立設於該承載件20上而位於該些電子元件21a,21b之間，以遮蔽該些電子元件21a,21b的側壁，而能避免該些電子元件22a,22b之電磁相互干擾，使該些電子元件21a,21b得以保持應有的功 效。
再者，該擋架22之高度可依需求呈現一致(圖未示)或高低不一(如第2B圖所示)。
又，如第2B’圖所示，該擋架22與該些電子元件21a,21b之佈設方式可依需求而定。
如第2C圖所示，形成一封裝層23於該承載件20上，以包覆該擋架22與該些電子元件21a,21b，且該封裝層23之頂面23a低於部分該擋架22之端部，以令部分該擋架22之端部凸出該封裝層23，亦即該擋架22產生凸出部220，使該擋架22之部分表面(即凸出部220)外露於該封裝層23。
於本實施例中，係以模壓製程(Molding Compound)形成該封裝層23，且藉由該封裝層23可保護該些電子元件避免遭受環境汙染、氧化或破壞。
再者，如第2C’圖所示，於進行模壓製程時，係於模具31與該擋架22之間，以離形膜(release film)30覆蓋該擋架22，故於形成該封裝層23後，移除該模具31與該離形膜30時，該擋架22之部分表面(即為該離形膜30所覆蓋之端部)會突出該封裝層23之模壓面(即頂面23a)而不會被覆蓋。
又，於其中一種佈設方式中，如第2C”圖所示，該擋架22與該封裝層23之側面23c齊平。於其它佈設方式中，該擋架22亦可凸出該封裝層23之側面23c。
如第2D圖所示，將一屏蔽元件24接觸該擋架22凸 出該封裝層23之部分表面(即該凸出部220)。
於本實施例中，形成該屏蔽元件24之材質為導電材，如金屬或導電膠，但不以此為限。例如，該屏蔽元件24係利用濺鍍(sputtering deposition)之方式形成導電層(或屏蔽層)於該封裝層23之頂面23a及側面23c，但未形成至該承載件20之底面20b；或者，提供一導電蓋作為屏蔽元件24，以蓋設於該封裝層23上。
再者，該屏蔽元件24係延伸至該承載件20之部分側面20c上，以接觸該承載件20之接地部，使該屏蔽元件24與該擋架22具有接地之功能。應可理解地，於其它實施例中，亦可由該擋架22接觸該承載件20之接地部，而使該屏蔽元件24與該擋架22具有接地之功能。
又，可選擇性地形成一絕緣包覆層25於該屏蔽元件24與該承載件20之側面20c上，使該絕緣包覆層25包覆該屏蔽元件24與該擋架22之凸出部220，其中，該絕緣包覆層25未形成至該承載件20之底面20b。例如，第2D圖所示之凸出部220係外露於該絕緣包覆層25；應可理解地，該凸出部220亦可未外露於該絕緣包覆層25。
本發明之電子封裝件2之製法，係藉由該擋架22之部分表面(即凸出部220)凸出該封裝層23，使該擋架22與該屏蔽元件24相互接觸以形成屏蔽結構，以供該些電子元件21a,21b之周圍均有屏蔽結構，不僅有效防止該些電子元件21a,21b之間的電磁波相互干擾，且有效防止外界電磁波干擾該些電子元件21a,21b之內部電路。
再者，由於該擋架22之部分表面外露於該封裝層23，故於形成該封裝層23之後，不用於該封裝層23上形成外露該擋架22之開孔，因而能節省製程步驟。
又，藉由形成屏蔽元件24於該封裝層23上，故無需考量該承載件20之線路佈設，不僅使製程更簡易，且縮短製程時間，因而有效降低製作成本。
本發明提供一種電子封裝件2，係包括：一承載件20、複數電子元件21a,21b、至少一擋架22、一封裝層23以及一屏蔽元件24。
所述之電子元件21a,21b係設於該承載件20上。
所述之擋架22係設於該承載件20上並位於該些電子元件21a,21b之間。
所述之封裝層23係形成於該承載件20上並包覆該些電子元件21a,21b與該擋架22，且至少部分該擋架22之表面係凸出該封裝層23。
所述之屏蔽元件24係接觸該擋架22凸出該封裝層23之部分表面。
於一實施例中，該電子元件21a,21b係為主動元件、被動元件或封裝結構。
於一實施例中，形成該擋架22之材質係為導電材。
於一實施例中，該屏蔽元件24係為形成於該封裝層上之導電層。
於一實施例中，該屏蔽元件24係為蓋設於該封裝層23上之導電蓋。
於一實施例中，該電子封裝件2復包括一包覆該屏蔽元件24之絕緣包覆層25。
綜上所述，本發明之電子封裝件及其製法中，係藉由該擋架凸出該封裝層，使該擋架與該屏蔽元件相互接觸以作為屏蔽結構，不僅能防止該些電子元件之間的電磁波相互干擾，且能有效防止外界電磁波干擾該些電子元件之內部電路。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧承載件
20b‧‧‧底面
20c,23c‧‧‧側面
21a,21b‧‧‧電子元件
22‧‧‧擋架
220‧‧‧凸出部
23‧‧‧封裝層
23a‧‧‧頂面
24‧‧‧屏蔽元件
25‧‧‧絕緣包覆層

Claims (13)

  1. 一種電子封裝件，係包括：承載件；複數電子元件，係設於該承載件上；擋架，係設於該承載件上並位於相鄰兩電子元件之間；封裝層，係形成於該承載件上並包覆該些電子元件與該擋架，且該擋架之部分表面係凸出該封裝層；以及屏蔽元件，係設於該封裝層上且接觸該擋架凸出該封裝層之部分表面。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件係為主動元件、被動元件或封裝結構。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，形成該擋架之材質係為導電材。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽元件係為形成於該封裝層上之導電層。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該屏蔽元件係為蓋設於該封裝層上之導電蓋。
  6. 如申請專利範圍第1項所述之電子封裝件，復包括包覆該屏蔽元件之絕緣包覆層。
  7. 一種電子封裝件之製法，係包括：於一承載件上設置複數電子元件及一擋架，其中，該擋架位於相鄰兩電子元件之間；形成封裝層於該承載件上，以令該封裝層包覆該些 電子元件與該擋架，並令該擋架之部分表面凸出該封裝層；以及於該封裝層上設置一屏蔽元件，且令該屏蔽元件接觸該擋架凸出該封裝層之部分表面。
  8. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該電子元件係為主動元件、被動元件或封裝結構。
  9. 如申請專利範圍第7項所述之電子封裝件之製法，其中，形成該擋架之材質係為導電材。
  10. 如申請專利範圍第7項所述之電子封裝件之製法，其中，於形成該封裝層前，將離形膜覆蓋於該擋架上，且於形成該封裝層之後，移除該離形膜。
  11. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該屏蔽元件係為以濺鍍方式形成於該封裝層上之導電層。
  12. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該屏蔽元件係為蓋設於該封裝層上之導電蓋。
  13. 如申請專利範圍第7項所述之電子封裝件之製法，復包括形成包覆該屏蔽元件之絕緣包覆層。
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US9997469B2 (en) 2018-06-12
TWI618156B (zh) 2018-03-11
US20180261552A1 (en) 2018-09-13
US10396040B2 (en) 2019-08-27
US20180040568A1 (en) 2018-02-08
CN107689364B (zh) 2020-10-27
CN107689364A (zh) 2018-02-13

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