TWI376777B - Stacked, interconnected semiconductor packages and method of stacking and interconnecting semiconductor packages - Google Patents

Stacked, interconnected semiconductor packages and method of stacking and interconnecting semiconductor packages Download PDF

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Publication number
TWI376777B
TWI376777B TW096120561A TW96120561A TWI376777B TW I376777 B TWI376777 B TW I376777B TW 096120561 A TW096120561 A TW 096120561A TW 96120561 A TW96120561 A TW 96120561A TW I376777 B TWI376777 B TW I376777B
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TW
Taiwan
Prior art keywords
contact pads
substrate
semiconductor package
semiconductor
electrical connectors
Prior art date
Application number
TW096120561A
Other languages
Chinese (zh)
Other versions
TW200807665A (en
Inventor
Cheemen Yu
Chih Chin Liao
Hem Takiar
Original Assignee
Sandisk Corp
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Filing date
Publication date
Priority claimed from US11/427,695 external-priority patent/US7615409B2/en
Priority claimed from US11/427,689 external-priority patent/US7550834B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200807665A publication Critical patent/TW200807665A/en
Application granted granted Critical
Publication of TWI376777B publication Critical patent/TWI376777B/en

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    • H—ELECTRICITY
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)

Abstract

An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Description

1376777 九、發明說明： 【發明所屬之技術領域】 本發明實施例倍、關於一種由複數㈣^導體封裝形成 之電子元件，及一種形成該電子元件之方法。 【先前技術】 對可攜式消費者電子器件t需求之強勁增長正推動著對 大谷置儲存裝置之需要。諸如快閃記憶體儲存卡之非揮發 性半導體記憶體裝置正廣泛用⑨滿足對數&資訊儲存及交 換之日益增長之需求。其可搞性、通用性及堅固設計連同 其高可靠性及大容量已使此類記憶體裝置理想地用於種類 繁夕之電子裝置中，其中包括，例如，數位照相機、數位 音樂播放器、視訊遊戲控制臺、PDA及蜂巢式電話。 雖然已知各種各樣之封裝構形，但快閃記憶體儲存卡大 體上可製作成系統級封裝（SiP)或多晶片模組（MCM)，其中 複數個晶粒安裝於-基板上。該基板大體上可包括一具有 一蝕刻於一側或兩側上之導電層之剛性底部。電連接形成 於該晶粒與該(等)導電層之間，且該(等)導電層提供一用於 將該晶粒整合至一電子系統中之電引線結構。一旦在該晶 粒與基板之間形成電連接，則通常可將組件封閉於模製化 合物中以提供一保護性封裝。 决閃屺隐體模組可為可攜式（如在平面柵格陣列（lga)封 裝之If形下）’或可為專用式（如在球形柵格陣列（BGA)封裝 之清开/下）可攜式快閃記憶體模組製造有接觸墊，此可使 該等模組用作可移動記憶體。可將其插入一主機裝置之插 121322.doc .由此可使該等接觸墊與該主機裝置中之一印刷電路 板壓力接觸’“達成該記憶體模組與主機裝置之間的通 另方面，將專用記憶體模組錫銲或另外永久地固定 至一主機裝置之印刷電路板。 圖1中顯示-傳統BGA封裝40之橫截面。一個或多個記憶 體晶粒20及一控制器晶粒22以一層疊之組態安裝於一基板 2:上。通常，基板24可由-(例如㈣雙馬來醢亞胺三嗪樹 』）、H構成之剛性芯28來形成。可使用習知之微影及姓刻 以H合意之電引線圖案將薄銅膜層卿成於該芯之頂 " 可鍍覆右干導電圖案區域以接納錫銲球32或 其他錫銲觸點。 /藉由—阻銲遮罩36來塗佈該基板以絕緣及保護形成於 / 土 之電引線圖案。可藉由銲絲34將該晶粒電連接至 該基板》可穿過該基板形成若干通孔(未顯示)以穿過該基板 將該晶粒電連接至锯p + 錫鲜球32。一旦該晶粒經電連接，便可 將㈣裝囊封於—模製化合_中以形成封裝4〇。此後， 可藉由錫銲球32使用—f知回溶製程將封裝安裝至一主 機裝置（未顯示）之印刷電路板❶ 始終存在-種增加記憶體模組内儲存容量之驅動力。增 :子今夏之種方法係增加該封裝内使用記憶體晶粒之 數量。於可攜式記憶體封裝中，可使用之晶粒數量受到封 裝厚度的限制’該封裝之厚度必須不能超過該主機裝置中 之接納該記憶體模组之標準尺寸插槽之厚度。 ；P使#裝之厚度不受標準的限制(如在一專用記 121322.doc 1376777 憶體模組中)’在一既定封裝内可層疊之晶粒亦通常不會多 於4或5個。一封裝中所添加之晶粒越多，則在人工或㈣ 組配期間其中一個或多個晶粒被損壞之可能性越大。且产 著晶粒數量增乡，封裝的良率下降士封裝中單個晶： 出現故障，則必須摒棄該封裝，目而會浪費未出現故障之 晶粒。此外，纟測試及運作期間，封裝内大量的晶粒會耗 費大量的電流來通電該封裝。1376777 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electronic component formed by a plurality of (four) conductor packages, and a method of forming the electronic component. [Prior Art] The strong growth in demand for portable consumer electronics is driving the need for Otani storage devices. Non-volatile semiconductor memory devices such as flash memory cards are widely used to meet the growing demand for log & information storage and exchange. Its versatility, versatility and robust design, along with its high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including, for example, digital cameras, digital music players, Video game console, PDA and cellular phone. Although a wide variety of package configurations are known, flash memory memory cards can be fabricated generally in a system-in-package (SiP) or multi-chip module (MCM) in which a plurality of dies are mounted on a substrate. The substrate can generally comprise a rigid bottom having a conductive layer etched on one or both sides. An electrical connection is formed between the die and the (or other) conductive layer, and the conductive layer provides an electrical lead structure for integrating the die into an electronic system. Once an electrical connection is made between the crystal and the substrate, the assembly can typically be enclosed in a molding compound to provide a protective package. The flashback hidden body module can be portable (as in the case of a planar grid array (lga) package), or can be dedicated (such as in the ball grid array (BGA) package clear / down The portable flash memory module is manufactured with contact pads, which enable the modules to be used as removable memory. It can be inserted into a host device plug 121322.doc. Thus, the contact pads can be brought into pressure contact with one of the host device's printed circuit boards to achieve the other aspect between the memory module and the host device. The dedicated memory module is soldered or otherwise permanently fixed to a printed circuit board of a host device. Figure 1 shows a cross section of a conventional BGA package 40. One or more memory die 20 and a controller crystal The pellets 22 are mounted on a substrate 2 in a stacked configuration. Typically, the substrate 24 can be formed from a rigid core 28 of - (eg, (d) bismaleimide triazine tree), H. Conventional use can be used. The lithography and surname engrave the thin copper film layer on top of the core with the H-conductor electrical lead pattern. The right-hand conductive pattern area can be plated to receive the solder balls 32 or other solder contacts. a solder mask 36 for coating the substrate to insulate and protect the electrical lead pattern formed in /. The die can be electrically connected to the substrate by a wire 34. A plurality of vias can be formed through the substrate ( Not shown) to electrically connect the die to the saw p + tin fresh ball 32 through the substrate. Once the die is electrically connected, (4) can be encapsulated in a molded compound to form a package. Thereafter, the package can be mounted to a host by solder balls 32 using a f-resolving process. The printed circuit board of the device (not shown) is always present - the driving force for increasing the storage capacity in the memory module. The method of adding this summer is to increase the number of memory chips used in the package. In a memory package, the number of dies that can be used is limited by the thickness of the package. The thickness of the package must not exceed the thickness of the standard size slot of the host device that accepts the memory module. Not limited by the standard (such as in a special note 121322.doc 1376777 memory module) 'The number of dies that can be stacked in a given package is usually no more than 4 or 5. The crystal added in a package The more particles, the greater the possibility that one or more of the grains will be damaged during manual or (4) assembly, and the number of grains produced increases, and the yield of the package decreases. A single crystal in the package: failure, You must abandon the package and you will be able to There is no faulty die. In addition, during testing and operation, a large amount of die in the package consumes a large amount of current to energize the package.

因此’將半導體封裝層疊在一起為人們所熟知。舉例而 言，標題為”Stackable Ball Grid Array Semic〇nduct〇rTherefore, it is well known to laminate semiconductor packages together. For example, the title is "Stackable Ball Grid Array Semic〇nduct〇r

Package and Fabrication Meth〇d There〇f"之第 6 4〇7 448號 美國專利揭示了 一種將一半導體晶粒安置在其内之支撐結 構。該支#結構具有形成於其底表面上之金屬跡線。然後， 使用黏接劑將一第二跡線層固定於該晶粒之頂部上，並連 接至該晶粒及支撐結構。然後，將錫銲球設置於第二金屬 跡線層之頂。p上。然後’藉由將該第_封裝之錫鋅球錫鲜 至該第二封裝之底表面上而將一第二封裝層疊在該第一封 裝之頂部上。 傳統層疊半導體封裝具有各種缺點。舉例而言，在上述 第6,407,448號美國專利中所示之設計中，為使該等封裝能 夠層疊需要相當數量之額外結構。該等相當數量之額外結 構使製造該封裝組件所必需之處理步驟增多，並使該製造 製程之耗時及費用增多。 【發明内容】 粗略闡述之本發明實施例係關於一種包括複數個層疊半 12J322.doc ★封袭之電子;^件。該種第—實施例包括—S於電搞接 该等層疊半導體封裝之内部連接器。該第二實施例包括一 用於電#接料;I疊半導體封裝之外部連接器。 本發月第-實施例’本文中稱之為内部引線層疊式半導 體封裝組件’可藉由一對基板面板進行成批地處理。該第 比面板可包括複數個積體電路（IC)組件，舉例而言，每一者 白包括複數個電耦接至一基板之記憶體晶粒。該第二面板 。匕括複數個1C組件，舉例而言，每__者皆包括複數個記 憶體晶粒及—電糕接至-基板之控制器晶粒。 可將複數個㈣連接II附裝至形成於該等組件中第一 者上之接㈣。該等内部連接器可由—習用引線框架之材 t形成’（諸如）例如’4至6密爾厚之銅合金。該等内部連接 。：形狀可通吊具有.—基底部分，其用於與該第-1C組 :上之接觸墊相配合；_自該基底部分延伸出之頸部部 :’及帛部部分’其用於連接至第二1C組件之底部。該 W部分較佳地具有—充分之長度以將該頭部部分定位在 第1C ,且件内之最上部晶粒及任何自其延伸之輝絲之上 可/。《亥1C組件之一個、兩個、三個或四個邊緣設置該 等内部連接器。 接下來’可在—傳統囊封製程中將該等第-及第二1C組 件！封於一模製化合物中。可將該第一職件上之内部連 态凡王封閉在該模製化合物内，此後可磨平該模製化合 2以使料内料接㈣部料之表轉露於第—IC組件 表面處。 12l322.doc 1376777 在囊封及研磨步驟之後’可自其各自面板將該等IC組件 分割成單個從而界定複數個半導體封裝.一旦經切割成半 導體封裝，則可將來自不同面板之封裝結合起來以形成該 内部連接器層疊式半導體封裝組件。藉由該第二封裝之接 觸墊來結合該等封裝，該等接觸墊與來自該第一封裝之電 連接器之頭部部分電耦接。Package and Fabrication Meth〇d There is a support structure in which a semiconductor die is placed. The branch # structure has metal traces formed on its bottom surface. A second trace layer is then attached to the top of the die using an adhesive and attached to the die and support structure. The solder balls are then placed on top of the second metal trace layer. p on. A second package is then laminated on top of the first package by tinning the first package of tin zinc balls onto the bottom surface of the second package. Conventional stacked semiconductor packages have various drawbacks. For example, in the design shown in U.S. Patent No. 6,407,448, a considerable number of additional structures are required to enable the packages to be stacked. These equivalent amounts of additional structure increase the number of processing steps necessary to manufacture the package assembly and increase the time and expense of the manufacturing process. SUMMARY OF THE INVENTION The embodiments of the present invention, which are roughly illustrated, relate to an electronic device comprising a plurality of stacked layers of 12J322.doc. The first embodiment includes -S electrically interconnecting the internal connectors of the stacked semiconductor packages. The second embodiment includes an external connector for the electrical connection; the I-stack semiconductor package. The first embodiment of the present invention, referred to herein as an inner lead laminated semiconductor package assembly, can be processed in batches by a pair of substrate panels. The first aspect panel can include a plurality of integrated circuit (IC) components, for example, each of which includes a plurality of memory dies electrically coupled to a substrate. The second panel. A plurality of 1C components are included. For example, each of the __ includes a plurality of memory cells and a controller die connected to the substrate. A plurality of (four) connections II can be attached to the first (4) formed on the first of the components. The internal connectors may be formed from a material t of a conventional lead frame, such as, for example, a '4 to 6 mil thick copper alloy. These internal connections. The shape can be suspended by having a base portion for mating with the contact pad on the -1C group: a neck portion extending from the base portion: 'and a crotch portion' for connection To the bottom of the second 1C component. The W portion preferably has a sufficient length to position the head portion at the 1C and the uppermost die in the member and any filaments extending therefrom. These internal connectors are provided by one, two, three or four edges of the Hai 1C component. Next, you can place these - and second 1C components in the traditional encapsulation process! Sealed in a molded compound. The internal connected state of the first member may be enclosed in the molding compound, after which the molding compound 2 may be smoothed to expose the surface of the material (4) material to the surface of the first IC component. At the office. 12l322.doc 1376777 After the encapsulation and grinding steps, the IC components can be divided into individual pieces from their respective panels to define a plurality of semiconductor packages. Once cut into semiconductor packages, packages from different panels can be combined to The internal connector stacked semiconductor package assembly is formed. The packages are bonded by the contact pads of the second package, the contact pads being electrically coupled to the head portions of the electrical connectors from the first package.

於其中該内部連接器層疊式半導體封裝組件擬為一 裝置之實施例中，可將錫銲球臨時點銲至該組件底部上之 接觸墊。 本發明第二實施例在本文中稱為一外部連接器層叠式半 導體封裝組件。如關於該第—實施例所述，將1(：組件形成 於第-及第二基板面板上。然後，可使用—具有複數個突 出部分之凹槽將該等Ic組件囊封於一模製化合物内，該複 數個突出部分沿該模製化合物之表面内之一個或多個邊緣 界定複數個凹陷。In an embodiment where the internal connector stacked semiconductor package assembly is intended to be a device, the solder balls can be temporarily spot welded to the contact pads on the bottom of the assembly. A second embodiment of the invention is referred to herein as an external connector stacked semiconductor package assembly. As described in relation to the first embodiment, 1 (: components are formed on the first and second substrate panels. Then, the recesses having a plurality of protruding portions can be used to encapsulate the Ic components in a molding. Within the compound, the plurality of protrusions define a plurality of depressions along one or more edges in the surface of the molding compound.

在囊封之後’可自其各自面板將該等IC組件分割成單個 從而界定複數個半導體封裝。-旦經㈣成半導體封裝， 可將複數個外部連接Hgj定至該等半導體封裝之第一者。 通常，每-外部連接器可為,Π形狀且具有：—基底部 分’其與該第一封裝之夫查44主 禾囊封表面上之接觸墊接觸；一頸 部部分’其沿及田比鄰於該筮 4第封裝之外邊緣定位；及一頭 部部分，其配合至該模贺作人t 、^'化0物内之凹陷中。外部連接器 可由一習用引線框架之材料 灯科形成，且可沿該第一半導體封 裝之一個、兩個、三個或+ 凡王口P四個邊緣設置。 12l322.doc 1376777After encapsulation, the IC components can be divided into individual pieces from their respective panels to define a plurality of semiconductor packages. Once the semiconductor package is used, a plurality of external connections Hgj can be assigned to the first of the semiconductor packages. Typically, each of the external connectors may be in the shape of a crucible and have: a base portion that is in contact with a contact pad on the surface of the first encapsulation 44; a neck portion that is adjacent to the field Positioning on the outer edge of the 第4 package; and a head portion that fits into the depression in the embossed person t, ^'. The external connector may be formed by a material of the conventional lead frame and may be disposed along one of the four edges of the first semiconductor package, two, three or +. 12l322.doc 1376777

在施加該等外部連接器之後，可將該等半導體封裝結合 在-起以形成該外部連接器層叠式半導體封裝組件。藉由 該第二封裝之接觸墊來結合該等第一及第二封裝，該等接 觸塾與該外部連接器之頭部部分電韓接。於其中該=部連 . m層疊式半導體封裝組件擬為— BGA封裝之實施例I •可將錫銲球臨時點銲至該裝置底表面上之接觸墊。 -L述實施例之内部連接||及外部連用於使該組件内 φ 之半導體封裝彼此電耦接。如熟習此項技術者應瞭解，可 以一已知方式來組態各自半導體封裝内之導電圖案，以使 在該等封裝經由内部/外部電連接器耦接在一起之後，一個 . 封裝内之半導體晶粒可電耦接至第二封裝内之半導體晶粒 及/或錫銲球或其他外部電連接器。 【實施方式】 現在將參照圖2至22對實施例進行闡述，該等粗略闞述之 實施例係關於一種層疊式半導體封裝組件。應理解，本發 鲁明可以諸多不同之形式實施而不應視為僅限於本文所述各 實施例。相反，提供此等實施例旨在使本揭示内容透徹且 完整並將本發明全面傳達給熟習此項技術者。當然，本發 明意欲涵蓋此等實施例之替代形式、修改及等效形式，此 4替代形式、修改及等效形式包含於由隨附申請專利範圍 所界定之本發明範疇及精神内。此外，於下文對本發明之 詳細說明中’列出眾多具體細節以提供對本發明之一透徹 瞭解。然而’熟習此項技術者將易知，無需此等具體細節 亦可實施本發明。 121322.doc 現在將參照圖2至13解釋本發明之第一實施例，本文稱之 為内部引線層疊式半導體封裝組件。圖2顯示一對基板面板 iOOa及l〇〇b之俯視圖。面板1003及1001)分別包括複數個封 裝輪廓102a及102b ’如下文所解釋，將於該複數個封裝輪 扉處製造若干個單獨之半導體封裝。應理解，在替代實施 例中，面板100a及l〇〇b之佈局以及面板l〇〇a、l〇〇b上之封 裝輪廓102a、102b之列及行數量可變化。此外，圖申顯示 面板100a及100b具有相同之組態，且彼此具有相同數量之 封裝輪廓列及行。應理解，在替代實施例中，面板丨〇〇&之 列及行的組態及/或數量可不同於面板100b之彼組態及/或 數量。 基板面板100a、100b可係各種不同之晶片載體媒介，其 中包括一 PCB、一引線框架或一捲帶式自動接合（7^8)捲 帶。若基板面板100a、100b係PCB，則每一基板面板可由 一具有一頂部導電層及一底部導電層之芯來形成。該芯可 由各種介電材料來形成，諸如（例如）聚醯亞胺層壓片、包括 FR4及FR5之環氧樹脂、雙馬來醯亞胺三嗪（BT)及類似物。 雖然對本發明並非具有決定性，該芯可具有—介於4〇微米 (μιη)至200(μηι)之間的厚度，但在替代實施例中該芯厚度可 變化超出彼範圍。於替代實施例中，該芯可係陶瓷或有機 物。 環繞該芯之導電層可由以下材料形成：銅或銅合金、鍍 銅或鍵銅合金、合金42(42Fe/58Ni)、鍍銅鋼 '或其他已知 供在基板面板上使用之金屬及材料。該等導電層可具有一 121322.doc •12· 1376777 約為10 μιη至24 μπι之厚度，但於替代實施例中該等層之厚 度可變化超出彼範圍。 圖3係一根據本發明實施例之用於形成一内部引線層疊 半導體，，且件之製造製程之流程圖。於一步驟中，對面板 • 购及1嶋實施鑽孔以在該基板中界定通孔。儘管步驟2〇〇 . 被闡述為其t對面板聽及兩者實施鑽孔之單個步 驟’但應理解可在一不同於面板祕之時間及利用一不同 • 於面板1〇扑之製程來對面板10〇a實施鑽孔。此在以下步驟 之說明中同樣適用，除非另外指出。 接下來，於步驟202中，在每一面板中之相應導電層上形 • 成導電圖案。特定而言’如圖4之流程圖所示，於步驟2 12 中，清潔該等導電層之表面。然後，於步驟2 14中，在該等 導電層上施加一光阻劑膜。然後，於步驟216中，可將一含 有導電圖案輪廓之圖案遮罩放置於該光阻劑膜上。對該光 阻劑膜（步騾218)實施曝光及顯影（步驟22〇)以自該等導電 • 層上之待蝕刻區域移除光阻劑。接下來，於步驟222中使用 諸如氣化鐵之蝕刻劑蝕刻掉已曝光之區域以在芯上界定導 ，圖案。接下來，於步驟224中，移除該光阻劑。本發明涵 蓋其他已知之用於在基板面板1〇〇a、1〇〇b上形成導電圖案 之方法。面板100a上之導電圖案可相同於或不同於面板 1 〇〇b上之導電圖案。 再次參照圖3，於步驟232中，可在一自動光學檢測（a〇i) 裝置中檢測該面板。在經檢測後，於步驟234中將該阻銲遮 罩施加至該面板。在施加該阻銲遮罩之後，在步驟幻6中， 121322.doc 1376777 可藉由一已知之電鐘或薄膜沈積製程使用Ni/Au合金42或 類似物對每一面板100a、1〇〇b之導電圖案上之錫銲區域實 施鐘覆。於各實施例中’可將該層疊式半導體封裝組件用 作一包括經鍍覆接觸指狀物之LGA封裝。於該等實施例 中，可先用一軟鍍覆層來鍍覆指狀物，然後用一硬鍍覆層 來鍵覆指狀物以減小對該等接觸指狀物之磨損。另一選擇 係’可以一單一鍍覆製程來鍍覆該等指狀物。 然後’可在一自動檢測製程（步驟24〇)及在一最終視覺檢 測（步驟242)中對該等相應基板面板進行檢測及測試以檢查 電作業及檢查污染、劃痕和脫色。然後，於步驟244中且如 參照圖5之侧視圖所闡述’將通過檢測之基板面板送至晶粒 附裝製程。圖5顯示一如上所述製造之來自面板1〇〇3及1〇〇b 之母一者之積體電路（1C)組件。所示之ic組件11 〇a係製造於 面板11 Oa上之複數個1C組件之其中一者，而所示之IC組件 ll〇b係製造於面板i〇〇b上之複數個基板組件之其中一者。 儘管圖5-7及9-11中顯示1C組件ll〇a及11 Ob彼此毗鄰，但包 括1C組件110a及ll〇b之面板100a及100b在其結合之前（如下 文關於圖13解釋）可實際上彼此遠離。 1C組件110a可包括複數個安裝於基板114a上之記憶體晶 粒11 2a。類似地，1C組件11 0b可包括複數個安裝於基板丨丨4b 上之記憶體晶粒ll2b»圖5顯示半導體晶粒112&、112b於基 板114a、114b上層疊成一偏置佈置。該種偏置可使得在該 晶粒之邊緣處將電引線連接至該層疊中半導體晶粒之每一 者。另一選擇係’可以一對準組態來層疊該晶粒且可藉由 121322.doc •14· 1376777 此項技術中習知之-石夕間隔物來分離該晶粒。該一個或多 個晶粒可具有介於2密爾與2〇密爾範圍内之厚度，但在替代 實施例卜m多個晶粒可祕2密“厚㈣密爾。After the external connectors are applied, the semiconductor packages can be bonded together to form the external connector stacked semiconductor package assembly. The first and second packages are coupled by the contact pads of the second package, and the contact pads are electrically connected to the head portions of the external connectors. The cascading semiconductor package assembly is intended to be - BGA package embodiment I. The solder balls can be temporarily spot welded to the contact pads on the bottom surface of the device. The internal connections || and external connections of the embodiment are used to electrically couple the semiconductor packages of φ within the assembly to each other. As will be appreciated by those skilled in the art, the conductive patterns within the respective semiconductor packages can be configured in a known manner such that after the packages are coupled together via internal/external electrical connectors, a semiconductor within the package The die can be electrically coupled to the semiconductor die and/or solder balls or other external electrical connectors within the second package. [Embodiment] Embodiments will now be described with reference to Figs. 2 through 22, which are related to a stacked semiconductor package assembly. It should be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The present invention is intended to cover alternative forms, modifications, and equivalents of the embodiments, which are included in the scope and spirit of the invention as defined by the appended claims. In addition, numerous specific details are set forth in the following detailed description of the invention to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. 121322.doc A first embodiment of the present invention will now be explained with reference to Figs. 2 through 13, which are referred to herein as internal lead stacked semiconductor package assemblies. Figure 2 shows a top view of a pair of substrate panels iOOa and l〇〇b. Panels 1003 and 1001) respectively include a plurality of package profiles 102a and 102b'. As will be explained below, a plurality of individual semiconductor packages will be fabricated at the plurality of package rims. It should be understood that in alternative embodiments, the layout of panels 100a and 10b and the number of rows and rows of package profiles 102a, 102b on panels 10a, 10b may vary. In addition, the Tussen display panels 100a and 100b have the same configuration and have the same number of package outline columns and rows as each other. It should be understood that in alternative embodiments, the configuration and/or number of panels and rows and rows may be different than the configuration and/or number of panels 100b. The substrate panels 100a, 100b can be comprised of a variety of different wafer carrier media including a PCB, a lead frame or a tape automated bonding (7^8) tape. If the substrate panels 100a, 100b are PCBs, each of the substrate panels may be formed by a core having a top conductive layer and a bottom conductive layer. The core may be formed from a variety of dielectric materials such as, for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like. While not critical to the invention, the core may have a thickness of between 4 and 10 (μιη) to 200 (μηι), but in alternative embodiments the core thickness may vary beyond the range. In an alternate embodiment, the core can be ceramic or organic. The conductive layer surrounding the core may be formed of copper or copper alloy, copper or copper bond alloy, alloy 42 (42Fe/58Ni), copper plated steel ' or other metals and materials known for use on substrate panels. The conductive layers may have a thickness of from about 1232.doc • 12·1376777 of from about 10 μm to about 24 μm, although in alternate embodiments the thickness of the layers may vary beyond the range. Figure 3 is a flow diagram of a fabrication process for forming an internal lead laminate semiconductor in accordance with an embodiment of the present invention. In one step, a hole is drilled into the panel and 1 inch to define a through hole in the substrate. Although step 2〇〇 is described as a single step of drilling the panel to both the panel and the two, it should be understood that it can be used in a different time than the panel and in a different process. The panel 10A is drilled. This also applies in the description of the following steps unless otherwise stated. Next, in step 202, a conductive pattern is formed on the corresponding conductive layer in each panel. Specifically, as shown in the flow chart of Fig. 4, in step 212, the surfaces of the conductive layers are cleaned. Then, in step 214, a photoresist film is applied over the conductive layers. Then, in step 216, a pattern mask containing the contour of the conductive pattern can be placed on the photoresist film. The photoresist film (step 218) is exposed and developed (step 22) to remove the photoresist from the areas to be etched on the conductive layers. Next, the exposed regions are etched away in step 222 using an etchant such as a gasified iron to define a conductive pattern on the core. Next, in step 224, the photoresist is removed. The present invention encompasses other known methods for forming conductive patterns on substrate panels 1a, 1b. The conductive pattern on the panel 100a may be the same as or different from the conductive pattern on the panel 1 〇〇b. Referring again to Figure 3, in step 232, the panel can be detected in an automated optical inspection (a〇i) device. After testing, the solder mask is applied to the panel in step 234. After applying the solder mask, in step F1, 121322.doc 1376777 can be used for each panel 100a, 1b by a known electric clock or thin film deposition process using Ni/Au alloy 42 or the like. The soldering area on the conductive pattern is subjected to a clock cover. In various embodiments, the stacked semiconductor package assembly can be used as an LGA package including plated contact fingers. In such embodiments, the fingers may be first plated with a soft coating and then the fingers may be bonded with a hard coating to reduce wear on the contact fingers. Another option is to plate the fingers in a single plating process. The respective substrate panels can then be inspected and tested in an automated inspection process (step 24A) and in a final visual inspection (step 242) to check for electrical work and to inspect for contamination, scratches, and discoloration. Then, in step 244 and as explained with reference to the side view of Fig. 5, the substrate panel to be tested is sent to the die attach process. Fig. 5 shows an integrated circuit (1C) assembly of the mother from the panels 1〇〇3 and 1〇〇b manufactured as described above. The illustrated ic component 11 〇a is one of a plurality of 1C components fabricated on the panel 11 Oa, and the illustrated IC component 11 〇b is one of a plurality of substrate components fabricated on the panel i 〇〇 b One. Although the 1C components 11a and 11b are shown adjacent to each other in Figures 5-7 and 9-11, the panels 100a and 100b including the 1C components 110a and 11b may be practical prior to their combination (as explained below with respect to Figure 13). Stay away from each other. The 1C assembly 110a can include a plurality of memory crystals 11 2a mounted on the substrate 114a. Similarly, the 1C component 110b can include a plurality of memory die 11bb mounted on the substrate 4b. Figure 5 shows that the semiconductor die 112&, 112b are stacked on the substrate 114a, 114b in an offset arrangement. This biasing allows electrical leads to be bonded to each of the stacked semiconductor dies at the edges of the die. Another option can be to laminate the dies in an aligned configuration and the dies can be separated by a shi-shi spacer as is known in the art. The one or more grains may have a thickness in the range of 2 mils and 2 mils, but in the alternative embodiment, the plurality of grains may be 2 mils thick (four) mils.

舉例而言，晶粒U2a、112b可係快閃記憶體晶片⑽R, NAND)、SRAM及/或DDT。於各實施例中，每一ic組件 ll〇a、11Gb可包括四個記憶體晶粒，但應理解，在替代實 施例中，每一組件可包括多於或少於四個記憶體晶粒。IC 組件ll〇a、HOb其中-者可進一步包括一用於控制記憶體 晶片112aL12b之輸入/輸出（1/〇)之控制器晶片，諸如（例 如）組件110b上之控制器晶片116b。舉例而言，該控制器晶 片可係-ASIC。除上述記憶體及控制器晶片t外，本發明曰 還涵蓋其他矽晶片，或本發明涵蓋其他矽晶片作為上述記 憶體及控制器晶片之替代。 圖5-14係該内部連接器層疊式半導體封裝組件在圖3流 程圖中所述之連續製造障段中之視圖。如圖5之側視圖中所 示，於步驟246中，可在該晶粒與該等基板之間形成銲絲 118a、118b'如圖6之側視圖中所示，於步驟248中，可將 銲膏添加至1C組件110b以沿IC組件丨1〇b之頂表面之對置邊 緣界定接觸墊120。 現在參照圖7’於步驟250中，可將内部連接器13〇附裝至 1C組件ll〇b之上表面上之接觸墊12〇。内部連接器13〇可由 習用引線框架之材料來形成，諸如（例如）4密爾至6密爾厚之 銅合金或合金42。在替代實施例中，該材料之類型及該材 料之厚度可變化。内部連接器i 30之形狀可通常具有：一用 12l322.doc 15 ^376777 ::接觸墊12。相配合之第—基底部分;—自 之第二頸部部分；及一連接至IC组件、之底 二 部部分。下文將對其進行解釋。該頸部部分較佳地且^ ==以將該頭部部分定位靴組件_内之最 =及任何自其延伸之銲絲上方。於圖7中，圖中顯示内 解^30之頭部大致垂直於該等底部及頭部部分。應理 ’在本發明之另外實施财，㈣部部分可相對於 底部及頭部部分形成傾斜角。 儘管圖〇顯示内部連接器13。具有—大致"z"形之組 但應理解連接器130可具有替代之組態。舉例而言，該 額外之組態包括-正向或反向之"C”形形狀，其具有並行 之底部及頭部部分及一在其間延伸之頸部部分。在一進一 ^實施财，連接器㈣可通常為',1"形形狀，其具有自基底 Μ之中間向上延伸及/或自該頭部部分之中間向下延伸 之頭部部分。本發明亦涵蓋其他形狀。 圖8係沿圓7中線8_8截取之俯視圖。如本文中顯示，内部 連接器uo及接觸塾120係沿IC組件ii此之對置邊緣設置。 ^本系統之進一步實施射’應理解，可沿1C組件11013之 個.邊緣、二個邊緣或全部四個邊緣來設置接觸塾⑵及固 定至其之内邹連接器13〇。儘管圖中顯示五個内部連接器位 於1C組件110b之兩個對置側之每一者上，但應理解可在本 發明各實施例中設置多於五個之諸多内部連接器。 現在參照圖9,接下來於步驟252中，可將IC組件1103及 u〇b囊封於一模製化合物132内。模製化合物⑴可係一諸 121322.doc •16· 1376777 如（例如）可自Sumitomo公司及Nitpo Denk〇公司（該兩公司 總部皆設在日本）購得之樹脂。本發明亦涵蓋來自其他製造 商之其他模製複合物。可根據各種已知製程(其争包括轉移 模塑或注塑技術）施加該模製化合物以囊封基板丨丨4 a ' • U4b、晶粒112a、112b和116b及内部連接器13〇。 參照圖10及11，接下來，可磨平1(：組件u〇b上之模製化 合物132以使内部連接器13〇頭部部分之表面暴露於冗組件 # 騰之表面處（步驟254)。作為步驟254中研磨模製化合物 132之替代，應理解，在該模製步驟之後，内部連接器 之頸部部分可具有-如此之長度以使該等内部連接器之頭 。卩。P刀可與模製化合物132之表面齊平。另一選擇係，在囊 封製程時，内部連接器130之頸部部分可具有一如此之長度 則吏料内部連接器之頭部冑分可穿過模製化合物132^ 頂部向外突出。此後，可保留連接器13〇之頭部部分以稍微 突出模製化合物表面，或可研磨該等頭部部分而與該模製 | 化合物表面齊平。 現在參照圖12之側視圖，接下來，於步驟256中可將銲 膏添加至IC組件蘭下部表面上之暴露觸點以形成接觸墊 138。接觸墊138形成之後，在步驟26〇中且如圖12中指示， 可自面板驗、10_IC組件11〇a、u〇b分割成單個以形 成最終的半導體封裝14〇a&14〇b。可藉由沿直線進行切鑛 而將每一半導體封裝14〇3及屬分割成單個。然而，可在 替代實施财使用除切料之各種㈣方法，諸如（例如）， 水射流切割、雷射切割、水導雷射切割、乾燥媒體切割及 121322.doc 17 :剛石塗層線切割。儘管直線切割將界定大致矩形或正方 =半導體封裝⑽、嶋，但應理解，在本發明之另外 ?列中，+導體封裝刚…條可具有除矩形及正方形 以外之形狀。 一旦經㈣成封裝14〇a、i俱，則於步驟262中可對該等 封裝進行單獨測試以確定該等封裝是否運作正常。如此項 技術中習知，該種測試可包括電測試、預燒及其他測試。 現在參照圖13,於步驟264中，可將封裝140a^楊結合 在一起以形.成圖13中所示之内部連接器層疊式半導體封裝 件144藉由封裝14〇a之接觸塾138來結合封裝1他及 _，該等接觸塾與封裝14〇b中之電連接器13〇内之頭部部 分電輕接°然後’可將封裝刚續準至封裝丨畅以便使用 -已知構造之固定結構來進行耦接。於本發明替代實施例 中，應理解，可使面板1〇〇a與面板1〇〇b對準並將其連接至 面板100b»在連接該等面板後，可將該等面板分割成單個。 於其中該外部連接器層疊式半導體封裝組件144擬為一 BGA封冑之實施例中，可將錫銲球固定至封裝組件144。如 圖14中所示，於步驟266中，可將銲膏142施加至組件下部 表面上之金屬觸點柵格，且可將錫銲球146臨時點銲至銲膏 142。右該内部引線層疊式半導體封裝組件係用作一可攜式 裝置’則可省去步驟266。在步驟268中，無論組件144是一 具有錫銲球146之BGA封裝還是一LGA封裝，皆可在一回熔 製程中固化所有的錫銲連接。該等錫銲連接包括封裝 140a、140b與電連接器13〇之間的錫銲連接，若必要，亦包 121322.doc 1376777 括封裝140a、140b與錫銲球146之間的錫銲連接。 於步驟270中，可對組件144進行測試。於其中組件144 包括一可攜式半導體裝置之實施例中，於步驟272中可將 組件144封閉在蓋中。當組件144係用作一錫銲至一主機裝 置主板之專用裝置，則可省去步驟272。 下文將參照圖15之流程圖及圖16_22之視圖來解釋文中 稱為一外部連接器層疊式半導體封裝組件之本發明進一步 實轭例。首先參照圖15之流程圖，可重複上述步驟2〇〇·246 以提供圖16中所示之1(：組件15〇&及15〇1)。如上文關於1(：組 件140a及140b所述，組件15〇a、15〇b可包括複數個晶粒， 諸如（例如），1C組件150a上之記憶體晶粒i12a及ic組件150b 上之記憶體晶粒112b和控制器晶粒116b。可將該晶粒絲銲 至如上所述形成之基板114a及114b。 現在參照圖17之剖視圖，於步驟2 74中，可將ic組件 150a、150b囊封於一模製化合物132内。如圖17及圖18之俯 視圖所示，該囊封製程中使用之模製凹槽可包括複數個突 出部分，該複數個突出部分沿模製化合物132之一表面内之 一個或多個邊緣界定複數個凹陷丨52。應理解，在替代實施 例中，可在囊封步驟之後在模製化合物132之表面内形成凹 陷 152 〇 儘管該等圖示顯示1C組件150a及1C組件150b兩者中皆形 成凹陷152，但如下文解釋僅使用IC組件15〇b中之凹陷 152。在各實施例中，使用同—模製凹槽來囊封…組件 150a、15〇b，如此便可在IC組件15〇&及15〇1)兩者中形成凹 I21322.doc 1376777 152。於替代實施例中，可自IC組件i5〇a省去凹陷。 現在參照圖19之剖視圖，於步驟276中，在囊封之後，可 自面板1〇〇a將各個心且件15〇a分割成單個以形成一最終的 半導體封裝160a。類似地，於步驟276中，可自面板！働將 -各個ic組件150b分成單個以形成最終的半導體封裝16讥。 在分割276之後，於步驟278中，可對半導體封裝i6〇a及祕 進行測試。亦如圖19中所示，於步驟中，可將銲膏施加 鲁 1半導體封裝16Ga&16()b之底表面以分別界定接觸塾Μ心 及154b。 如圖20中所見並如關於步驟282所述，在形成該等接觸塾 .之後，可將外部連接器164固定至半導體封裝i6〇b。，每一 .外部連接器164可大致為"c"形形狀，其具有一與接觸墊 a接觸之第—基底部分、一沿及毗鄰於封裝1 60b外邊緣 ^位之第二頸部部分及—配合至凹陷152内之第三頭部部 刀外部連接器164可由一習用引線框架之材料來形成，諸 ® 如（例如），4密爾至6密爾厚之銅合金或合金“。在替代實施 例中，該材料之類型及該材料之厚度可變化。於圖2】中， 外部連接器164係沿Ic組件隱之對置邊緣設置。於本系統 ^進一步實施例中，應理解，可沿1C組件150b之一個邊緣、 二個邊緣或全部四個邊緣來設置外部連接器164。儘管圖18 中顯不用於五個外部連接器164之凹陷位於ic組件Η仳兩 個=置側之每一側上，但應理解，在本發明之各實施例中 可。又置多於五個之諸多外部連接器1 64。 在外。P連接器164施加之後，於步驟2 84中，如圖21中所 12l322.doc -20- 1376777 示’可將半導體封裝16〇a及160b結合在一起以形成外部連 接器層疊式半導體封裝組件17〇。藉由封裝16〇3之接觸墊 154a來結合封裝16〇&及16〇b，該等接觸墊與封裝i6〇b中之 外部連接器164之頭部部分電耦接。可將封裝16〇&對準至封 裝160b以便使用一夾具或其他已知構造之固定結構進行耦 接。 於其中外部連接器層疊式半導體封裝組件17〇擬為一 BGA封裝之實施例中，可將錫銲球固定至封裝組件17〇。如 圖22中所不，可將銲膏142施加至組件下部表面上之金屬觸 點柵格，且於步驟286中，可將錫銲球146臨時點銲至銲膏 14 2。若該外部連接器層疊式半導體封裝組件17 0係用作一 可攜式裝置，則可省去步驟286。無論組件17〇是一具有錫 銲球146之BGA封裝還是一LGA封裝，於步驟288中皆可 在一回熔製程中固化所有的錫銲連接。該等錫銲連接包括 封裝160a、160b與電連接器164之間的錫銲連接，若必要， 亦包括封裝160a、160b與錫銲球146之間的錫銲連接。 於v驟290中，可對組件丨7〇進行測試。於其中組件1 包括一可攜式半導體裝置之實施例中，於步驟292中，可將 組件170封閉在蓋中。若組件17〇係用作一錫銲至一主機裝 置主板之專用裝置，則可省去步驟292。 上述實施例之内部連接器13〇及外部連接器164係用於使 該組件内之半導體封裝彼此電純。如熟習此項技術者應 瞭解m已知方式來組態各自半導體封裝内之導電圖 案’以便料Μ經由内部/外部電連接器純在一起之 121322.doc -21- 1376777 後，一個封裝内之半導體晶粒可電耦接至第二封裴内之半 導體晶粒及/或錫銲球146或其他外部電連接器。因此， 錫銲一起之後，該封裝組件便可作為一單一電子元件進行 運作，諸如例如，一單一快閃記憶體裝置。若該快閃記憶 體裝置係一專用元件，則該裝置可係一 iNAND BGa。若該 快閃記憶體裝置係一可攜式元件，則該裝置可係一 SD LGA。本發明亦涵蓋其他裝置。 很明顯，該等耦接在一起之半導體封裝無需源自同一個 基板面板。因此，一第一基板面板可包括所有相同之諸如. (例如）具有一控制器及一個或多個快閃記憶體晶片之半導 體封裝。而一第二基板面板可包括所有相@之諸如（例如） 僅具有快閃記憶體晶片之半導體封裝。然後，可藉由如上 所述之内部或外部電連接器來耦接來自相應面板之封裝。 在上述實施例中，該封裝組件係由兩個覆蓋面積相同或 相近之半導體封裝組成。然而，應理解，根據該内部或外 部連接器之組態’該封裝組件可包括兩個以上半導體封 裝。類似地’在替代實施例令’該組件内封裝之大小無需 彼此相同。 出於例證及說明之目的，上文已對本發明進行了詳細說 明。本文並非意欲具有排他性或將本發明限制於所揭示之 具體形式H文之教示亦可作出諸多種修改及改變。 選擇該等所述各實施例旨在最佳地解釋本發明之原理及其 只際應用’藉以使熟習此項技術者能夠以適合於所構想具 體應用之各種實施例形式及使用各種修改來最佳地利用本 12I322.doc •22- 1376777 發月。本發明之範嘴擬由隨附申請專利範圍來界定。 【圖式簡單說明】 圖1係習用封裝之剖面側視圖。 圖2係-對基板面板之俯視圖，藉由該對基板面板可製造 • #數個根據本發明之層疊式半導體封裝組件。 圖3係根據本發明實施例之内部引線層疊式半導體封 裝組件之整個製造製程之流程圖。 • 圖4係一用於在本發明中使用之基板上形成導電圖案之 光微影製程之流程圖。 圖5-7係一對根據本發明之積體電路組件在各個製造階 段之側視圖。 . ®8<卜根據本發明—實施例之包括内部連接器之積體 • 電路組件之俯視圖。 圖9-10係一對根據本發明之積體電路組件在各個製造階 段之側視圓。 • 圖11係一囊封積體電路組件之俯視圖，該囊封積體電路 組件具有穿過一模製化合物之表面暴露之内部連接器。 圖12-14係一對根據本發明之積體電路組件在各個製造 階段之側視圖。 圖1 5係一用於形成根據本發明實施例之外部連接器層疊 式半導體封裝組件之整個製造製程之流程圖。 圖16係一對根據本發明之積體電路組件在製造期For example, the dies U2a, 112b can be flash memory chips (10) R, NAND), SRAM, and/or DDT. In various embodiments, each ic component 11a, 11Gb can include four memory dies, but it should be understood that in an alternate embodiment, each component can include more or less than four memory dies. . The IC components 11a, HOb may further include a controller wafer for controlling the input/output (1/〇) of the memory chips 112aL12b, such as, for example, the controller wafer 116b on the component 110b. For example, the controller wafer can be an ASIC. In addition to the above described memory and controller wafers t, the present invention also encompasses other germanium wafers, or the present invention encompasses other germanium wafers as an alternative to the above described memory and controller wafers. 5-14 are views of the internal connector stacked semiconductor package assembly in the continuous manufacturing barrier described in the flow diagram of Fig. 3. As shown in the side view of FIG. 5, in step 246, a wire 118a, 118b' may be formed between the die and the substrate as shown in the side view of FIG. 6, in step 248, Solder paste is added to the 1C assembly 110b to define the contact pads 120 along opposing edges of the top surface of the IC component 丨1〇b. Referring now to Figure 7', in step 250, internal connector 13A can be attached to contact pad 12A on the upper surface of 1C component 110b. The internal connector 13A can be formed from a material of a conventional lead frame such as, for example, a 4 mil to 6 mil thick copper alloy or alloy 42. In alternative embodiments, the type of material and the thickness of the material can vary. The shape of the internal connector i 30 can generally have: a 12l 322.doc 15 ^ 376777 :: contact pad 12 . a mating first-base portion; - a second neck portion; and a second portion connected to the IC assembly. This will be explained below. The neck portion is preferably and === to position the head portion above the most in the shoe assembly_ and any wire extending therefrom. In Fig. 7, the head of the inner solution 30 is shown to be substantially perpendicular to the bottom and head portions. In the alternative implementation of the present invention, the (4) portion may form an oblique angle with respect to the bottom portion and the head portion. Although the figure shows the internal connector 13. There is a group of - roughly "z" but it should be understood that the connector 130 can have an alternative configuration. For example, the additional configuration includes a -forward or reverse "C" shape having a parallel bottom and head portion and a neck portion extending therebetween. The connector (4) may generally be a ', 1" shaped shape having a head portion extending upwardly from the middle of the base cymbal and/or extending downwardly from the middle of the head portion. Other shapes are also contemplated by the present invention. A top view taken along line 8_8 of the circle 7. As shown herein, the internal connector uo and the contact 塾120 are disposed along the opposite edge of the IC component ii. ^ Further implementation of the system 'should be understood, along the 1C component The edge, the two edges, or all four edges of the 11013 are used to provide the contact 塾 (2) and the 连接 connector 13 固定 fixed therein. Although the figure shows five internal connectors on the opposite sides of the 1C assembly 110b On each of them, it should be understood that more than five internal connectors may be provided in various embodiments of the present invention. Referring now to Figure 9, next to step 252, IC component 1103 and u〇b can be provided. Sealed in a molding compound 132. Molding compound (1) Can be a 121322.doc •16· 1376777 such as, for example, resins available from Sumitomo and Nitpo Denk〇, both of which are based in Japan. The invention also covers other models from other manufacturers. The composite can be applied according to various known processes, which include transfer molding or injection molding techniques to encapsulate the substrate 丨丨 4 a ' • U4b, the dies 112a, 112b and 116b, and the internal connector 13 Referring to Figures 10 and 11, next, the molding compound 132 on the component u〇b may be grounded to expose the surface of the head portion of the internal connector 13 to the surface of the redundant component #Step 254). As an alternative to the abrasive molding compound 132 in step 254, it will be understood that after the molding step, the neck portion of the inner connector can have a length such that the head of the internal connector. The P-knife can be flush with the surface of the molding compound 132. Alternatively, during the encapsulation process, the neck portion of the internal connector 130 can have such a length that the head of the internal connector of the dip can be divided. Through the molding compound 132^ top External protrusions. Thereafter, the head portion of the connector 13 can be retained to slightly protrude the surface of the molded compound, or the head portions can be ground to be flush with the surface of the molded compound. Referring now to the side view of FIG. Next, solder paste may be added to the exposed contacts on the lower surface of the IC component to form the contact pads 138 in step 256. After the contact pads 138 are formed, in step 26 and as indicated in Figure 12, the panel is self-panelable The 10_IC components 11〇a, u〇b are divided into individual pieces to form a final semiconductor package 14〇a&14〇b. Each semiconductor package 14〇3 and the genus can be divided into individual by cutting along a straight line. . However, various (four) methods other than cutting can be used in alternative implementations such as, for example, water jet cutting, laser cutting, water-guided laser cutting, dry media cutting, and 121322.doc 17: Rigid stone coated wire cutting . While a straight cut will define a generally rectangular or square = semiconductor package (10), 嶋, it should be understood that in another column of the invention, the + conductor package may have a shape other than a rectangle and a square. Once the packages are packaged, the packages can be individually tested in step 262 to determine if the packages are functioning properly. As is known in the art, such tests can include electrical testing, burn-in, and other testing. Referring now to Figure 13, in step 264, the packages 140a can be joined together to form the internal connector stacked semiconductor package 144 shown in Figure 13 by the contact pads 138 of the package 14A. The package 1 and _ are electrically connected to the head portion of the electrical connector 13 in the package 14B, and then the package can be renewed until the package is ready for use - known construction The structure is fixed for coupling. In an alternate embodiment of the present invention, it will be appreciated that panel 1A can be aligned with panel 1b and attached to panel 100b» after joining the panels, the panels can be divided into individual pieces. In embodiments in which the external connector stacked semiconductor package assembly 144 is intended to be a BGA package, solder balls can be secured to the package assembly 144. As shown in FIG. 14, in step 266, solder paste 142 can be applied to the metal contact grid on the lower surface of the assembly, and solder balls 146 can be temporarily spot welded to solder paste 142. Right, the inner lead stacked semiconductor package assembly is used as a portable device, and step 266 can be omitted. In step 268, whether the component 144 is a BGA package with solder balls 146 or an LGA package, all solder connections can be cured in a single pass. The soldered connections include a soldered connection between the packages 140a, 140b and the electrical connector 13A, and if necessary, a package 121322.doc 1376777 includes a soldered connection between the packages 140a, 140b and the solder balls 146. In step 270, component 144 can be tested. In an embodiment where component 144 includes a portable semiconductor device, component 144 can be enclosed in the cover in step 272. When component 144 is used as a dedicated device for soldering to a host device motherboard, step 272 may be omitted. A further embodiment of the present invention, referred to herein as an external connector stacked semiconductor package assembly, will be explained with reference to the flow chart of Fig. 15 and the view of Fig. 16-22. Referring first to the flowchart of Fig. 15, the above step 2 〇〇 246 can be repeated to provide 1 (: components 15 〇 & and 15 〇 1) shown in Fig. 16. As described above with respect to 1 (: components 140a and 140b, components 15a, 15b may include a plurality of dies, such as, for example, memory on memory die i12a and ic component 150b on 1C component 150a The bulk die 112b and the controller die 116b. The die can be wire bonded to the substrates 114a and 114b formed as described above. Referring now to the cross-sectional view of Fig. 17, in step 2 74, the ic components 150a, 150b can be encapsulated. Sealed within a molding compound 132. As shown in the top views of Figures 17 and 18, the molding recess used in the encapsulation process can include a plurality of projections along one of the molding compounds 132. One or more edges within the surface define a plurality of depressions 52. It will be appreciated that in alternative embodiments, depressions 152 may be formed in the surface of the molding compound 132 after the encapsulation step, although the illustrations show 1C components The recesses 152 are formed in both the 150a and 1C assemblies 150b, but as explained below only the recesses 152 in the IC component 15B are used. In various embodiments, the same molded grooves are used to encapsulate the components 150a, 15 〇b, so you can do it in IC components 15 & 5〇1) The concave is formed in both I21322.doc 1376777 152. In an alternative embodiment, the recess can be omitted from the IC component i5〇a. Referring now to the cross-sectional view of Fig. 19, in step 276, after encapsulation, the individual cores 15a can be divided into individual pieces from the panel 1a to form a final semiconductor package 160a. Similarly, in step 276, it can be from the panel! The individual ic components 150b are divided into individual pieces to form the final semiconductor package 16A. After segmentation 276, in step 278, the semiconductor package i6〇a and the secret can be tested. As also shown in Fig. 19, in the step, solder paste may be applied to the bottom surface of the semiconductor package 16Ga & 16()b to define the contact center and 154b, respectively. As seen in Figure 20 and as described with respect to step 282, after forming the contacts, the external connector 164 can be secured to the semiconductor package i6〇b. Each of the external connectors 164 can be substantially a "c" shape having a first base portion in contact with the contact pad a, a second neck portion adjacent to and adjacent to the outer edge of the package 1 60b. And - the third head knife outer connector 164 that fits into the recess 152 can be formed from a material of a conventional lead frame, such as, for example, a 4 mil to 6 mil thick copper alloy or alloy. In an alternative embodiment, the type of material and the thickness of the material may vary. In Figure 2, the external connector 164 is disposed along the opposite edge of the Ic component. In the further embodiment of the system, it should be understood The external connector 164 can be disposed along one edge, two edges, or all four edges of the 1C assembly 150b. Although the recesses shown in Figure 18 for the five external connectors 164 are located at the ic component Η仳 two sides On each side, it should be understood that in the various embodiments of the present invention, more than five external connectors 1 64 may be placed. After the P connector 164 is applied, in step 2 84, Figure 12, 12l322.doc -20- 1376777 shows 'can be half The body packages 16A and 160b are joined together to form an external connector stacked semiconductor package assembly 17. The package 16〇& and 16〇b are bonded by the contact pads 154a of the package 16〇3, and the contact pads are The head portion of the external connector 164 in the package i6〇b is electrically coupled. The package 16〇& can be aligned to the package 160b for coupling using a fixture or other fixed structure of known construction. In the embodiment in which the stacked semiconductor package assembly 17 is a BGA package, the solder balls can be fixed to the package assembly 17. As shown in Fig. 22, the solder paste 142 can be applied to the metal on the lower surface of the package. a contact grid, and in step 286, the solder ball 146 can be temporarily spot-welded to the solder paste 14 2. If the external connector stacked semiconductor package assembly 17 is used as a portable device, Go to step 286. Regardless of whether the component 17 is a BGA package having solder balls 146 or an LGA package, all of the solder connections can be cured in a melt process in step 288. The solder connections include package 160a. Tin between 160b and electrical connector 164 The solder joint, if necessary, also includes a soldered connection between the package 160a, 160b and the solder ball 146. The component 丨7〇 can be tested in step 290. The component 1 includes a portable semiconductor device. In an embodiment, the component 170 can be enclosed in the cover in step 292. If the component 17 is used as a dedicated device for soldering to a host device motherboard, step 292 can be omitted. The interior of the above embodiment Connector 13 and external connector 164 are used to electrically clean the semiconductor packages within the assembly. Those skilled in the art should understand that m is known to configure the conductive patterns in their respective semiconductor packages so that the material is purely connected through the internal/external electrical connectors 121322.doc -21 - 1376777, in a package The semiconductor die can be electrically coupled to the semiconductor die and/or solder balls 146 or other external electrical connectors within the second package. Thus, after soldering together, the package assembly can operate as a single electronic component, such as, for example, a single flash memory device. If the flash memory device is a dedicated component, the device can be an iNAND BGa. If the flash memory device is a portable component, the device can be an SD LGA. Other devices are also contemplated by the present invention. It is obvious that the semiconductor packages that are coupled together need not originate from the same substrate panel. Thus, a first substrate panel can include all of the same semiconductor packages such as, for example, a controller and one or more flash memory chips. And a second substrate panel can include all of the semiconductor packages such as, for example, only flash memory chips. The package from the respective panel can then be coupled by an internal or external electrical connector as described above. In the above embodiment, the package assembly is composed of two semiconductor packages having the same or similar coverage areas. However, it should be understood that the package assembly can include more than two semiconductor packages depending on the configuration of the internal or external connector. Similarly, the size of the packages within the assembly in the alternative embodiment is not necessarily the same as each other. The invention has been described in detail above for the purposes of illustration and description. Various modifications and changes may be made without departing from the spirit and scope of the invention. The embodiments described above are intended to best explain the principles of the invention and the application of the application of the invention in the form of the various embodiments and Jiadi uses this 12I322.doc •22- 1376777 to send the month. The scope of the present invention is intended to be defined by the scope of the accompanying patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional side view of a conventional package. 2 is a plan view of a substrate panel by which the plurality of stacked semiconductor package assemblies according to the present invention can be fabricated. Figure 3 is a flow diagram of the overall fabrication process of an internal lead laminate semiconductor package assembly in accordance with an embodiment of the present invention. • Figure 4 is a flow diagram of a photolithographic process for forming a conductive pattern on a substrate used in the present invention. Figure 5-7 is a side elevational view of a pair of integrated circuit assemblies in accordance with the present invention at various stages of manufacture. ® 8 < Included in the present invention - an integrated body including an internal connector - a top view of the circuit assembly. Figure 9-10 is a side view of a pair of integrated circuit assemblies in accordance with the present invention at various stages of manufacture. • Figure 11 is a top plan view of a encapsulated circuit assembly having internal contacts exposed through a surface of a molding compound. Figure 12-14 is a side elevational view of a pair of integrated circuit assemblies in accordance with the present invention at various stages of manufacture. Figure 15 is a flow diagram of an overall fabrication process for forming an external connector stacked semiconductor package assembly in accordance with an embodiment of the present invention. Figure 16 is a pair of integrated circuit components according to the present invention during the manufacturing period

J〜I只1J 視圖。 圖17係一對根據本發明之積體電路組件在製造期間知J~I only 1J view. Figure 17 is a pair of integrated circuit assemblies according to the present invention during manufacture

之。J 121322.doc -23· 1376777 視圖。 圖18係一根據本發明之囊封積體電路組件之俯視圖，該 囊封積體電珞組件包括形成於模製化合物中之凹陷。 圖19-22係一對根據本發明一實施例之積體電路組件在 各個製造階段之剖面側視圖。It. J 121322.doc -23· 1376777 view. Figure 18 is a top plan view of a capsule-embedded circuit assembly in accordance with the present invention comprising recesses formed in a molding compound. 19-22 are cross-sectional side views of a pair of integrated circuit assemblies in accordance with an embodiment of the present invention at various stages of fabrication.

【主要元件符號說明】 20 記憶體晶粒 22 控制器晶粒 24 基板 28 剛性芯 30 薄銅膜層 32 模製化合物 34 銲絲 36 阻銲遮罩 38 模製化合物 40 封裝 100a 基板面板 100b 基板面板 102a 封裝輪廓 102b 封裝輪廓 110a 1C組件 110b 1C組件 112a 記憶體晶粒 112 b 記憶體晶粒 121322.doc -24- 1376777 114a 基板 114b 基板 116b 控制Is晶片 118a 銲絲 118b 銲絲 120 接觸墊 130 内部連接器 132 模製化合物 138 接觸墊 140a 半導體封裝 140b 半導體封裝 142 銲膏 144 組件 146 錫鲜球 150a 1C組件 150b 1C組件 152 凹陷 154a 接觸墊 154b 接觸墊 160a 半導體封裝 160b 半導體封裝 164 外部連接器 170 外部連接器層疊式半導體封裝組件 121322.doc -25-[Main component symbol description] 20 Memory die 22 Controller die 24 Substrate 28 Rigid core 30 Thin copper film layer 32 Mold compound 34 Wire 36 Solder mask 94 Mold compound 40 Package 100a Substrate panel 100b Substrate panel 102a package outline 102b package outline 110a 1C component 110b 1C component 112a memory die 112 b memory die 121322.doc -24- 1376777 114a substrate 114b substrate 116b control Is wafer 118a wire 118b wire 120 contact pad 130 internal connection Molding compound 138 contact pad 140a semiconductor package 140b semiconductor package 142 solder paste 144 component 146 tin fresh ball 150a 1C component 150b 1C component 152 recess 154a contact pad 154b contact pad 160a semiconductor package 160b semiconductor package 164 external connector 170 external connection Stacked semiconductor package assembly 121322.doc -25-

Claims (1)

1376777 丨-----^ / 巧年？月>日修正本 * . 匕______ 一 十、申請專利範圍： - 1. 一種半導體封裝組件 • 一第一半導體封裝 第096120561號專利申請案 中文申請專利範圍替換本(101年7月） ，其包括： ，其包含： 一具有第一及第二對置表面之第一剛性基板，該第 一基板具有一位於該第一表面上之第一組接觸墊及一 位於該第二表面上之第二組接觸墊； 一第一組一個或多個半導體晶粒其安裝於該第一 基板之第一表面上； 複數個電連接器’該複數個電連接器之一電連接器 包含： 一基底部分，其固定至該第一基板之第一表面上 該第一組接觸墊中之一接觸墊； 頸。卩°卩分’其自該基底部分延伸離開該接觸 墊；及 一頭部部分，其自該頸部部分延伸；及 一第—囊封劑，其用於囊封至少該第一組接觸 墊、該第一半導體晶粒及該電連接器之基底部分、 頸部部分和部分頭部部分；及 一第一半導體封裝，其層疊於該第一半導體封裝 上，其包括： 一具有第三及第四對置表面之第二基板，該第二 土板八有位於該第二表面上之第三組接觸墊，該 電連接器之頭部部分固定至該第三組接觸墊之一接 觸墊； 12I322-1010629.doc 1376777 2二組-個或多個半導體晶粒，其安裝在該第 暴板之第四表面上；及 劑 一用於囊封至少該第二半導體晶粒之帛二囊封 該第一基板上之該第二組 其中該第二組觸點永久配 其中該第二組觸點以可拆 5亥基底部分大致平行於該 2. 如請求項1之半導體封裝組件 觸點能夠與一主機裝置配合。 3. 如請求項2之半導體封裝組件 合至一主機裝置。 4. 如3月求項2之半導體封裝組件 卸方式配合至一主機裝置。 5·如請求項1之半導體封裝組件 ::組：觸塾之接觸墊，該頸部部分大致垂直於該基底 而該頭部部分大致垂直於該頸部部分。 6.如請求項丨之半導體 平行於該u W基底及頭部部分大致 、讀觸墊之接觸墊’而該頸部部分相對於 〇X 土底及頭部部分形成一傾斜角。 8. 7·==⑹之半導體封裝組件，其中該複數個電連接器係 该第一半導體封裝之一單個邊緣對準。 9. 如請求項1之半導體封裝組件，其中該複數 沿該第一半導體封裝之對置邊緣對準。連接"係 如請求項1之半導體封褒組件，其中該複數 沿該第-半導㈣k三個邊緣對卜 連 之半導體封裝組件，其中該複數個電連接器係 /0 Μ 半導體封裝之四個邊緣對準。 121322-1010629.doc 1376777 ii.如請求項i之半導體封裝組件，纟中該第一及第二組半導 體晶粒包括八個記憶體晶粒及一個與該八個記憶麓晶粒 通信之控制器晶粒。 12· —種組配一半導體封裝組件之方法，其包括如下步驟： U)形成一第一積體電路組件，其包括以下步驟，- Ο) 在一基板的一第一表面上形成複數個接觸墊， (π)在該基板的該第一表面上安裝兩個或兩個以上的 半導體晶粒； (b) 將複數個電連接器固定至該複數個接觸墊，該等電連 接器之第一部分連接至該等接觸墊而該等電連接器 之第二部分自該等接觸墊間隔開； (c) 將該第一積體電路組件及複數個電連接器囊封於一 模製化合物中； (d) 研磨該模製化合物之一表面，以使該等電連接器之第 二部分之表面透過該表面暴露在外，該研磨步驟不影 響女裝在該基板上的該兩個或兩個以上的半導體晶 粒； (e) 形成一第二積體電路組件，其包括一基板，該基板具 有一其上安裝一個或多個半導體晶粒且其上界定複 數個接觸墊之表面； (f) 將該第二積體電路囊封於一模製化合物中； (g) 將該等第一與第二囊封積體電路彼此固定，使該等電 連接器之第二部分之暴露表面電耦接至該第二積體 電路上之複數個接觸塾。 I21322-I010629.doc 1376777 13. 14. 15. 16. 17. 18. 19. 如請求項12之方法’其中將該等第—及第二經囊封積體 電路彼此固定之該步驟⑷包括如下步驟：將^二㈣ 電路之-接觸墊錫銲至—電連接器之第二部分之一暴露 表面。 如請求之方法，其進—步包括步驟⑻：將錫鲜球固 定至該基板之第二表面上-第二組接觸塾以界定一黯 裝置。 如請求項12之方法，其進一步包括步驟⑻：在該基板之 第二表面上界定接觸指狀物以界定一lga裝置。 如請求項12之方法’其中將複數個電連接器固定至該複 數個接觸塾之該步驟(b)包括如下步驟：沿該第一積體電 路之一單個邊緣將複數個電連接器錫銲至接觸墊。 如請求項丨2之方法，其中將複數個電連接器固定至該複 數個接觸墊之該步驟⑻包括如下步驟：沿該第一積體電 路之一對邊緣將複數個電連接器錫銲至接觸墊。 如請求項12之方法，其中將複數個電連接器固定至該複 數個接觸墊之該步驟㈨包括如下步驟：沿該第一積體電 路之三個邊緣將複數個電連接器錫銲至接觸墊。 如明求項12之方法，其中將複數個電連接器固定至該複 數個接觸墊之該步驟(b)包括如下步驟：沿該第一積體電 路之四個邊緣將複數個電連接器錫銲至接觸墊。 121322-1 〇10629.doc1376777 丨-----^ / Qiaonian? Month>Day Revision** 匕______ Ten, patent application scope: - 1. A semiconductor package assembly • A first semiconductor package No. 096120561 Patent application Chinese patent application scope replacement (July 101) The method includes: a first rigid substrate having first and second opposing surfaces, the first substrate having a first set of contact pads on the first surface and a second surface a second set of contact pads; a first set of one or more semiconductor dies mounted on the first surface of the first substrate; a plurality of electrical connectors 'one of the plurality of electrical connectors, the electrical connector comprising: a base portion fixed to one of the first set of contact pads on the first surface of the first substrate; the neck; a portion extending from the base portion away from the contact pad; and a head portion extending from the neck portion; and a first encapsulating agent for encapsulating at least the first set of contact pads a first semiconductor die and a base portion, a neck portion and a portion of the header portion of the electrical connector; and a first semiconductor package stacked on the first semiconductor package, the method comprising: a second substrate of the fourth opposite surface, the second earth plate eight having a third set of contact pads on the second surface, the head portion of the electrical connector being fixed to one of the contact pads of the third set of contact pads 12I322-1010629.doc 1376777 2 two sets of one or more semiconductor grains mounted on the fourth surface of the first storm plate; and a first one for encapsulating at least the second semiconductor die Sealing the second group on the first substrate, wherein the second set of contacts is permanently matched with the second set of contacts to be detachable, and the base portion is substantially parallel to the 2. The semiconductor package assembly contact of claim 1. Can be combined with a host device. 3. The semiconductor package component of claim 2 is coupled to a host device. 4. As in March, the semiconductor package assembly of item 2 is unloaded to a host device. 5. The semiconductor package assembly of claim 1 :: set: contact pads of the contact, the neck portion being substantially perpendicular to the substrate and the head portion being substantially perpendicular to the neck portion. 6. The semiconductor of claim 丨 is parallel to the u W substrate and the head portion, substantially touching the contact pads of the contact pads, and the neck portion forms an oblique angle with respect to the 土X soil bottom and the head portion. 8. The semiconductor package of claim 7 wherein the plurality of electrical connectors are individually edge aligned with one of the first semiconductor packages. 9. The semiconductor package of claim 1, wherein the plurality of pixels are aligned along opposite edges of the first semiconductor package. The semiconductor package assembly of claim 1, wherein the plurality of semiconductor package components along the three-edge (four) k edge of the first semiconductor connector package, wherein the plurality of electrical connector systems/0 半导体 semiconductor package The edges are aligned. 121322-1010629.doc 1376777 ii. The semiconductor package component of claim i, wherein the first and second sets of semiconductor dies comprise eight memory dies and a controller in communication with the eight memory dies Grain. 12. A method of assembling a semiconductor package assembly, comprising the steps of: U) forming a first integrated circuit component comprising the steps of: - forming a plurality of contacts on a first surface of a substrate a pad, (π) mounting two or more semiconductor dies on the first surface of the substrate; (b) fixing a plurality of electrical connectors to the plurality of contact pads, the electrical connector One portion is connected to the contact pads and the second portion of the electrical connectors are spaced apart from the contact pads; (c) the first integrated circuit component and the plurality of electrical connectors are encapsulated in a molding compound (d) grinding a surface of the molding compound such that the surface of the second portion of the electrical connector is exposed through the surface, the grinding step not affecting the two or two of the women's clothing on the substrate The above semiconductor die; (e) forming a second integrated circuit component including a substrate having a surface on which one or more semiconductor dies are mounted and on which a plurality of contact pads are defined; The second integrated circuit Encapsulating in a molding compound; (g) fixing the first and second encapsulating circuit circuits to each other to electrically couple the exposed surface of the second portion of the electrical connectors to the second integrator A plurality of contacts on the circuit. I21322-I010629.doc 1376777 13. 14. 15. 16. 17. 18. 19. The method of claim 12, wherein the step (4) of fixing the first and second encapsulation circuits to each other comprises the following Step: Solder the contact pads of the ^2 (4) circuit to one of the second portions of the electrical connector to expose the surface. In the method of claim, the method further comprises the step (8) of: fixing the tin balls to the second surface of the substrate - the second set of contacts to define a device. The method of claim 12, further comprising the step (8) of defining contact fingers on the second surface of the substrate to define a lga device. The method of claim 12, wherein the step (b) of fixing the plurality of electrical connectors to the plurality of contact pads comprises the step of soldering the plurality of electrical connectors along a single edge of the first integrated circuit. To the contact pad. The method of claim 2, wherein the step (8) of fixing the plurality of electrical connectors to the plurality of contact pads comprises the step of soldering the plurality of electrical connectors to the edge along one of the first integrated circuits Contact pad. The method of claim 12, wherein the step (9) of fixing the plurality of electrical connectors to the plurality of contact pads comprises the step of soldering the plurality of electrical connectors to the contacts along three edges of the first integrated circuit. pad. The method of claim 12, wherein the step (b) of fixing the plurality of electrical connectors to the plurality of contact pads comprises the step of: placing a plurality of electrical connector tins along four edges of the first integrated circuit Solder to the contact pad. 121322-1 〇10629.doc
TW096120561A 2006-06-29 2007-06-07 Stacked, interconnected semiconductor packages and method of stacking and interconnecting semiconductor packages TWI376777B (en)

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