TW202135243A - 扇出型堆疊式半導體封裝結構之多層模封方法 - Google Patents

扇出型堆疊式半導體封裝結構之多層模封方法 Download PDF

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TW202135243A
TW202135243A TW109107148A TW109107148A TW202135243A TW 202135243 A TW202135243 A TW 202135243A TW 109107148 A TW109107148 A TW 109107148A TW 109107148 A TW109107148 A TW 109107148A TW 202135243 A TW202135243 A TW 202135243A
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Taiwan
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molding method
layer
molding
fan
redistribution layer
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TW109107148A
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English (en)
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劉聖捷
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力成科技股份有限公司
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Priority to TW109107148A priority Critical patent/TW202135243A/zh
Priority to CN202010158099.3A priority patent/CN113363166A/zh
Priority to US16/890,859 priority patent/US20210280522A1/en
Publication of TW202135243A publication Critical patent/TW202135243A/zh

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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

本發明係一種扇出型堆疊式半導體封裝結構之多層模封方法，係準備二個不同尺寸的模塑空間，將製程中先完成的第一半導體結構置入尺寸小的第一模塑空間，以完成第一封膠體；再將之後完成的第二半導體結構置入尺寸較大的第二模塑空間，以完成第二封膠體，且該第二封膠體連同第一封膠體一併包覆；是以，本發明的多層模封方法可適用於使用大尺寸載板的扇出型面板級封裝製程，也不必使用昂貴的壓模膠。

Description

扇出型堆疊式半導體封裝結構之多層模封方法
本發明係關於一種扇出型堆疊式半導體封裝結構之模封方法，尤指一種扇出型堆疊式半導體封裝結構之多層模封方法。
請參閱圖2所示，係為一種堆疊式半導體封裝結構80，其係以晶圓級封裝製程予以封裝，其主要包含有一第一重佈線層81、一下晶片82、二上晶片83及一第二重佈線層84；其中該下晶片82係先黏著於該第二重佈線層84，並以模封方式形成一第一封膠體85，該第一封膠體85係包覆該下晶片82；再於該封膠體85上形成該第一重佈線層81，接著以覆晶接合方式將該二上晶片83接合於該第一重佈線層81上，再以一壓模膠貼合並包覆於該二上晶片83，構成一第二封膠體90。
由於壓模膠成本較模封用樹脂來得昂貴，且目前業界尚未有可支援扇出型面板級封裝製程所使用500mm(寬度)載板用的壓模膠；因此，若以扇出型面板級封裝製程形成該堆疊式半導體封裝結構的第二封膠體，會是一項技術瓶頸，有待進一步改良並克服之。
有鑑於上述扇出型面板級封裝製程封裝該堆疊式半導體封裝結構時所產生第二封膠體的問題，本發明係提出一種扇出型堆疊式半導體封裝結構之多層模封方法，可解決此一問題。
欲達上述目的所使用的主要技術手段係令該扇出型堆疊式半導體封裝結構之多層模封方法包含以下步驟： (a) 提供一扇出型半導體封裝製程用之載板； (b) 於該載板上形成多個第一封裝結構； (c) 將該些第一封裝結構置入一第一模塑空間中，以形成一第一封膠體，該第一封膠體係包覆該些第一封裝結構； (d) 於該第一封膠體的一外露表面形成一第一重佈線層； (e) 於該第一重佈線層上形成多個第二封裝結構； (f) 將該第一封膠體、該第一重佈線層及該些第二封裝結構置入一第二模塑空間中，以形成一第二封膠體，該第二封膠體係包覆該第一封膠體及該第一重佈線層；其中該第二模塑空間係大於該第一模塑空間； (g) 移除該載板；以及 (h) 進行切單步驟以形成多顆扇出型堆疊式半導體封裝結構。
由上述說明可知，本發明主要準備二個不同尺寸的模塑空間，將製程中先完成的第一半導體結構置入尺寸小的第一模塑空間，以完成第一封膠體；再將之後完成的第二半導體結構置入尺寸較大的第二模塑空間，以完成第二封膠體，該第二封膠體連同第一封膠體一併包覆；是以，本發明的多層模封方法可適用於使用大尺寸載板的扇出型面板級封裝製程，也不必使用昂貴的壓模膠。
本發明係針對扇出型面板級封裝製程的模封步驟提出改良，以下配合圖式詳細說明本發明技術。
參閱圖1A至圖1H所示，係為本發明扇出型堆疊式半導體封裝結構1之多層模封方法，其包含以下步驟(a)至(h)。
於步驟(a)中，如圖1A所示，提供一扇出型半導體封裝製程用之載板10；於本實施例，該載板10係用於扇型出面板級封裝，其寬度大於等於500mm。
於步驟(b)中，如圖1A所示，於該載板10上形成多個第一封裝結構20；於本實施例，該步驟(b)係包含如後步驟(b1)至(b3)；其中於步驟(b1)中，於該載板10上形成一第二重佈線層21；於步驟(b2)中，將多個第一晶片22的背面221黏貼於該第二重佈線層21上，各該第一晶片22的主動面222的接點係形成有凸塊223；以及於步驟(b3)中，於各該第一晶片22周圍形成有多個金屬柱23，並與該第二重佈線層21電性連接；其中該些金屬柱23與該些凸塊223係齊平。
於步驟(c)中，如圖1B所示，將該些第一封裝結構20置入一第一模塑空間721中，以形成一第一封膠體30，如圖1C所示，該第一封膠體30係包覆該些第一封裝結構20。於本實施例，如圖1B所示，準備一灌膠模具70，該模具70係包含一上模具71及一下模具72；其中該載板10連同該些第一封裝結構20固定在該上模組71，而該下模具72包含有該第一模塑空間721， 將該上模具71蓋合於該下模具72的第一模塑空間721後，即可形成該第一封膠體30。較佳地，該第一封膠體30自該灌膠模具70中取出後，其一外露表面31係與該些金屬柱23與該些凸塊223係齊平。較佳地，該第一模塑空間721尺寸為489.8 x 480.9 mm。
於步驟(d)中，如圖1C及圖1D所示，於該第一封膠體30的外露表面31形成一第一重佈線層40；該第一重佈線層40係與該些第一封裝結構20的該些金屬柱23與該些凸塊223電性連接。
於步驟(e)中，如圖1D及圖1E所示，於該第一重佈線層40上形成多個第二封裝結構50；於本實施例，各該第二封裝結構50係將二個第二晶片51的主動面511均朝向該第一重佈線層40上，並電性接合於該第一重佈線層40；接著，於各該第二封裝結構50的至少一第二晶片51的主動面511與該第一重佈線層40之間的填充一底膠52。
於步驟(f)中，如圖1E及圖1F所示，將該第一封膠體30、該第一重佈線層40及該些第二封裝結構50一同置入一第二模塑空間722中，以形成一第二封膠體60，如圖1E及圖1G所示，該第二封膠體60係包覆該第一封膠體30、該些底膠52及該第一重佈線層40；其中該第二模塑空間722係大於該第一模塑空間721。於本實施例，如圖1F所示，準備一灌膠模具70’，該模具70’係包含一上模具71’及一下模具72’；其中該載板10連同該些第二封裝結構50固定在該上模組71’，而該下模具72’包含有該第二模塑空間722， 將該上模具71’蓋合於該下模具72’的第二模塑空間722後，即可形成該第二封膠體60。較佳地，該第二模塑空間722尺寸為501.8 x 492.9 mm，可供寬度500mm的載板置入。是以，本發明可以準備二台灌膠模具，也可準備一台可調整下模具之模塑空間尺寸的灌膠模具，不以此為限。
於步驟(g)中，如圖1H所示，移除該載板10，使該第一封裝結構20對應該載板10的一表面外露，於該第一封裝結構20的外露表面形成多個外連接件211。於本實施例，於載板10移除後，第二重佈線層21外露，再於該第二重佈線層21形成錫球。
於步驟(h)中，如圖1H所示，進行切單步驟，以形成多顆扇出型堆疊式半導體封裝結構1，將位在該載板10最外側的第一及第二封膠30、60體切除。
綜上說明可知，本發明於扇出型面板級封裝製程中加入多層模封方法，主要準備二個不同尺寸的模塑空間，將製程中先完成的第一半導體結構置入尺寸小的第一模塑空間，以完成第一封膠體；再將之後完成的第二半導體結構置入尺寸較大的第二模塑空間，以完成第二封膠體，該第二封膠體連同第一封膠體一併包覆；是以，在扇出型面板級封裝製程中，本發明不必使用昂貴的壓模膠來完成該封裝堆疊式半導體封裝結構之多層封膠層。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
1:扇出型堆疊式半導體封裝結構 10:載板 20:第一封裝結構 21:第二重佈線層 211:外連接件 22:第一晶片 221:背面 222:主動面 223:凸塊 23:金屬柱 30:第一封膠體 31:表面 40:第一重佈線層 50:第一封裝結構 51:第二晶片 511:主動面 52:底膠 60:第二封膠體 70:灌膠模具 70’:灌膠模具 71:上模具 71’:上模具 72:下模具 72’:下模具 721:第一模塑空間 722:第二模塑空間 80:堆疊式半導體封裝結構 81:第一重佈線層 82:下晶片 83:上晶片 84:第二重佈線層 85:第一封膠體 90:第二封膠體
圖1A至圖1H：本發明扇出型堆疊式半導體封裝結構之多層模封方法中不同步驟的剖面圖。 圖2：既有以晶圓級封裝製程封裝的一堆疊式半導體封裝結構的剖面圖。
1:扇出型堆疊式半導體封裝結構
20:第一封裝結構
21:第二重佈線層
211:外連接件
22:第一晶片
221:背面
222:主動面
223:凸塊
23:金屬柱
30:第一封膠體
31:表面
40:第一重佈線層
50:第一封裝結構
51:第二晶片
511:主動面
52:底膠
60:第二封膠體

Claims (10)

  1. 一種扇出型堆疊式半導體封裝結構之多層模封方法，包括： (a) 提供一扇出型半導體封裝製程用之載板； (b) 於該載板上形成多個第一封裝結構； (c) 將該些第一封裝結構置入一第一模塑空間中，以形成一第一封膠體，該第一封膠體係包覆該些第一封裝結構； (d) 於該第一封膠體的一外露表面形成一第一重佈線層； (e) 於該第一重佈線層上形成多個第二封裝結構； (f) 將該第一封膠體、該第一重佈線層及該些第二封裝結構置入一第二模塑空間中，以形成一第二封膠體，該第二封膠體係包覆該第一封膠體及該第一重佈線層；其中該第二模塑空間係大於該第一模塑空間； (g) 移除該載板；以及 (h) 進行切單步驟以形成多顆扇出型堆疊式半導體封裝結構。
  2. 如請求項1所述之多層模封方法，其中於步驟(f)移除該載板後，該第一封裝結構對應該載板的一表面外露，於該第一封裝結構的外露表面形成多個外連接件。
  3. 如請求項1或2所述之多層模封方法，其中該步驟(b)係包含： (b1) 於該載板上形成一第二重佈線層； (b2) 將多個第一晶片的背面黏貼於該第二重佈線層上，各該第一晶片的主動面的接點係形成有凸塊；以及 (b3) 於各該第一晶片周圍形成有多個金屬柱，並與該第二重佈線層電性連接；其中該些金屬柱與該些凸塊係齊平。
  4. 如請求項3所述之多層模封方法，其中該步驟(c)的第一封膠體的外露表面係與該些金屬柱與該些凸塊係齊平。
  5. 如請求項4所述之多層模封方法，其中該步驟(d)的該第一重佈線層係與該些金屬柱與該些凸塊電性連接。
  6. 如請求項5所述之多層模封方法，其中該步驟(e)的各該第二封裝結構係將至少一第二晶片的主動面朝向該第一重佈線層上，並電性接合於該第一重佈線層。
  7. 如請求項4所述之多層模封方法，其中於該步驟(e)中，於各該第二封裝結構的至少一第二晶片的主動面與該第一重佈線層之間的填充一底膠。
  8. 如請求項5所述之多層模封方法，其中於該步驟(f)中該第二封膠體係進一步包覆該些底膠。
  9. 如請求項3所述之多層模封方法，其中該步驟(f)的各該外連接件係為錫球。
  10. 如請求項1所述之多層模封方法，其中： 該步驟(a)的該載板寬度係大於等於500mm； 該第二模塑空間寬度係大於等於500mm；以及 該第一模塑空間寬度係小於500mm。
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