TWI740501B - 積體電路封裝及形成封裝結構的方法 - Google Patents

積體電路封裝及形成封裝結構的方法 Download PDF

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TWI740501B
TWI740501B TW109116134A TW109116134A TWI740501B TW I740501 B TWI740501 B TW I740501B TW 109116134 A TW109116134 A TW 109116134A TW 109116134 A TW109116134 A TW 109116134A TW I740501 B TWI740501 B TW I740501B
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package
dummy die
package component
component
sealant
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TW109116134A
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TW202044432A (zh
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吳志偉
郭立中
王卜
施應慶
盧思維
葉宮辰
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台灣積體電路製造股份有限公司
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Abstract

本揭露實施例提供一種形成封裝結構的方法,包括將第二封裝部件接合到第一封裝部件,將第三封裝部件接合到第一封裝部件,附接虛設晶粒到第一封裝部件上,將第二封裝部件、第三封裝部件及虛設晶粒密封在密封劑內,以及執行平坦化製程以使第二封裝部件的頂表面與密封劑的頂表面齊平。在平坦化製程之後,密封劑的上部與虛設晶粒重疊。虛設晶粒被鋸穿而分離成第一虛設晶粒部分以及第二虛設晶粒部分。密封劑的上部也被鋸穿。

Description

積體電路封裝及形成封裝結構的方法
本發明實施例關於一種半導體封裝技術,特別係有關於一種具有虛設晶粒(dummy dies)的積體電路封裝及形成此封裝結構的方法。
自積體電路(integrated circuit,IC)的發展以來,由於各種電子元件(即電晶體、二極體、電阻、電容等)的積體密度的不斷提高,半導體產業經歷了持續快速的成長。在大多數情況下,積體密度的提高來自於最小特徵尺寸的不斷縮小,這使得更多的部件可以整合到給定區域中。
這些積體改進在本質上基本上是二維的(two-dimensional,2D),因為積體部件所佔據的區域基本上是在半導體晶圓的表面上。一般地,積體電路的密度增加和相應的面積減小已經超過將積體電路晶片直接接合到基板上的能力。中介層(interposer)已用於將球的接觸區域從晶片的接觸區域重新分配到中介層的較大的區域。再者,中介層允許用於包括多個晶片的三維的(three-dimensional,3D)封裝。其他的封裝也已經發展來納入3D的領域。
本揭露一些實施例提供一種形成封裝結構的方法,包括將第二封裝部件接合到第一封裝部件,將第三封裝部件接合到第一封裝部件,附接虛設晶粒(dummy dies)到第一封裝部件上,以及將第二封裝部件、第三封裝部件及虛設晶粒密封在密封劑內。所述形成封裝結構的方法還包括執行平坦化製程以使第二封裝部件的頂表面與密封劑的頂表面齊平,其中在平坦化製程之後,密封劑的上部與虛設晶粒重疊。所述形成封裝結構的方法更包括鋸穿(sawing-through)虛設晶粒以將虛設晶粒分離成第一虛設晶粒部分以及第二虛設晶粒部分,其中密封劑的上部被鋸穿。
本揭露一些實施例提供一種形成封裝結構的方法,包括將第一封裝部件接合到第二封裝部件,其中第一封裝部件包括裝置晶粒。所述形成封裝結構的方法還包括附接虛設晶粒到第二封裝部件上,其中虛設晶粒包括凹槽。所述形成封裝結構的方法還包括將第一封裝部件和虛設晶粒密封在密封劑內,其中密封劑包括填充該凹槽的部分。所述形成封裝結構的方法更包括使用刀具執行分割製程(singulation process)以形成一封裝(package),其中所述封裝包括第一封裝部件、一部分的第二封裝部件以及一部分的虛設晶粒,且其中刀具切穿密封劑在凹槽內的部分。
本揭露一些實施例提供一種積體電路封裝,包括第一封裝部件、第二封裝部件、虛設晶粒以及密封劑。第二封裝部件是在第一封裝部件上方且接合到第一封裝部件。虛設晶粒是在第一封裝部件上方且附接到第一封裝部件上,其中虛設晶粒具有第一頂表面以及低於第一頂表面的第二頂表面。密封劑將虛設晶粒密封在其中,其中密封劑包括與虛設晶粒的第二頂表面重疊(overlapping)的第一部分,且虛設晶粒的第一頂表面通過密封劑暴露。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然,這些實施例僅作為範例,而不該以此限定本揭露的範圍。例如,在說明書中敘述了一第一特徵形成於一第二特徵之上或上方,其可能包含第一特徵與第二特徵是直接接觸的實施例,亦可能包含了有附加特徵形成於第一特徵與第二特徵之間,而使得第一特徵與第二特徵可能未直接接觸的實施例。另外,在本揭露不同範例中可能使用重複的參考符號及/或標記,此重複係為了簡化與清晰的目的,並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
再者,空間相關用語,例如“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用語,係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。
根據各種實施例,提供了包括虛設晶粒(dummy dies)的封裝結構及其形成方法。根據一些實施例示出了形成封裝結構的中間階段。討論了一些實施例的變形。在各視圖及說明性實施例中,相似的參考符號用於表示相似的元件。根據本揭露的一些實施例,包括虛設晶粒的封裝結構被放置在主動晶粒(active dies)的附近以減小封裝結構的翹曲(warpage)。這種封裝結構的翹曲的減小通過減少主動晶粒與中介層之間的冷焊(cold joints)的可能性而使得封裝結構更可靠。根據一些實施例,虛設晶粒沿著封裝結構的周邊放置,例如在切割道(scribe line)區域內或附近。因此,當封裝結構被分割(singulated)時,虛設晶粒被鋸穿(sawed through)。留下一層模塑料(molding compound)與虛設晶粒重疊(overlapping),以避免虛設晶粒在分割(singulation)中發生破裂。
實施例將針對特定背景來描述,即使用基板上晶圓上晶片(Chip-on-Wafer-on-Substrate,CoWoS)處理的晶粒-中介層-基板堆疊封裝(Die-Interposer-Substrate stacked package)。然而,其他實施例也可以應用於其他封裝,例如晶粒-晶粒-基板堆疊封裝(Die-Die-Substrate stacked package)及其他處理。本文中討論的實施例將提供示例以使得能夠製造或使用本揭露的標的,並且具有本領域普通技術的人員將容易理解,可以在不同實施例的預期範圍之內進行修改。儘管所討論的方法實施例可以特定順序來執行,但是其他方法實施例也可以其他任何邏輯順序來執行。
第1-5、6A、6B、6C、6D、6E、6F及7-14圖示出了根據本揭露一些實施例的封裝結構形成中的中間階段的剖視圖和平面圖(例如俯視圖)。相應的製程也示意性地反應在第23圖所示的製程流程中。
第1圖示出了晶圓10的形成,根據一些實施例,晶圓10包括多個封裝部件28(第2圖)。封裝部件28可為裝置晶粒、封裝或其類似物。封裝部件28可以包括任何數量的晶粒、基板、電晶體、主動裝置、被動裝置或其類似物。在一實施例中,封裝部件28可以包括基板20,其可為體型半導體(bulk semiconductor)基板、絕緣體上覆矽(silicon-on-insulator,SOI)基板、多層半導體基板或其類似物。半導體基板由半導體材料形成,其可為矽、鍺、化合物半導體(包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)或上述之組合。也可以使用其他基板,例如多層或梯度基板。基板20可以是被摻雜的(doped)或未被摻雜的(undoped)。例如電晶體、電容、電阻、二極體等裝置可以形成在半導體基板20的主動面(active surface)22之中及/或之上。
封裝部件28可以包括互連結構24,其包括形成在主動面22上的一或多個介電層及各別的金屬化圖案。介電層中的金屬化圖案可以例如通過使用通孔(vias)及/或跡線(traces)在裝置之間路由電信號,並且還可以包含各種電性裝置,例如電容、電阻、電感或其類似物。各種裝置和金屬化圖案可以互連以執行一或多個功能。功能可以包括記憶體結構、處理結構、感測器、放大器、功率分配、輸入/輸出電路等。此外,在互連結構24之中及/或之上形成例如導電柱(例如,包括例如銅之類的金屬)的電性連接件26,以為電路和裝置提供外部電性連接。根據一些實施例,電性連接件26從互連結構24突出以形成柱狀結構。
根據本揭露一些實施例,可以在互連結構24中形成多個金屬間介電(inter-metallization dielectric,IMD)層。金屬間介電層可以由低K介電材料通過本領域已知的任何合適方法形成,例如旋塗、化學氣相沉積(chemical vapor deposition,CVD)、電漿輔助CVD(plasma-enhanced CVD,PECVD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDP-CVD)等,低K介電材料例如為磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)、氟矽玻璃(fluorosilicate glass,FSG)、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymers)、矽碳材料、其化合物、其複合物、上述之組合等。金屬化圖案可以形成在金屬間介電層中,例如通過使用微影技術在金屬間介電層上沉積和圖案化光阻材料,以暴露金屬間介電層中要成為金屬化圖案的部分。可以使用例如各向異性乾式蝕刻製程之類的蝕刻製程來在金屬間介電層中產生與金屬間介電層的暴露部分對應的凹槽及/或開口。凹槽及/或開口可以具有擴散阻擋層(diffusion barrier layer)內襯且填充有導電材料。擴散阻擋層可以包括一或多層氮化鉭、鉭、氮化鈦、鈦、鎢鈷等或其組合,通過原子層沉積(atomic layer deposition,ALD)等方式沉積形成。金屬化圖案的導電材料可以包括銅、鋁、鎢、銀、上述之組合等,通過化學氣相沉積、物理氣相沉積(physical vapor deposition,PVD)等方式沉積形成。可以去除金屬間介電層上的任何多餘的擴散阻擋層及/或導電材料,例如通過使用化學機械研磨(chemical mechanical polish,CMP)製程。
在第2圖中,晶圓10被分割成多個單獨的封裝部件28。通常地,封裝部件28包含相同的電路,例如裝置和金屬化圖案,儘管這些晶粒也可以具有不同的電路。可以通過刀具鋸切(blade sawing)、雷射切割等來分割。
每個封裝部件28可以包括一或多個邏輯晶粒(例如中央處理單元、圖形處理單元、現場可編程閘陣列(field-programmable gate array,FPGA)、系統單晶片(system-on-chip,SOC)晶粒、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒等)、功率管理晶粒(例如功率管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、信號處理晶粒(例如數位信號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如類比前端(analog front-end,AFE)晶粒)等或上述之組合。
第3-5和7-14圖示出了在封裝封裝部件和虛設晶粒的多個中間階段的剖視圖,這些封裝部件和虛設晶粒被接合到其他封裝部件。各別的製程顯示為如第23圖所示的製程流程400。在第3-5和7-14圖中,中介層用作封裝部件36的示例,在其上接合有其他封裝部件。應當理解的是,其他類型的封裝部件,例如封裝基板(有核心的或無核心的)、封裝或其類似物也可以用作封裝部件36。
第3圖示出了根據一些實施例之封裝部件32,其在處理期間包括一或多個封裝部件36。封裝部件32可以是中介層晶圓,在其內沒有主動裝置(例如電晶體和二極體)及被動裝置(例如電阻、電容、電感等)。封裝部件32也可以是包括主動及/或被動裝置的裝置晶圓。基板34可以是半導體基板或電介質基板。當是半導體基板時,基板34可以是體型半導體基板、絕緣體上覆矽(SOI)基板、多層半導體基板或其類似物。基板34的半導體材料可以是矽、鍺、化合物半導體(包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)或上述之組合。也可以使用其他基板,例如多層或梯度基板。基板34可以是被摻雜的或未被摻雜的。封裝部件32也可以是封裝基板,其可以包括核心或者可以是無核心的基板。
貫通孔(Through-vias,TVs)38形成為從基板34的第一表面37延伸到基板34中。當基板34是矽基板時,貫通孔38有時也稱為貫通基板通孔或貫通矽通孔。可以通過例如蝕刻、銑削、雷射技術、上述之組合及/或其類似的技術在基板34中形成凹槽來形成貫通孔38。可以例如通過使用氧化製程或保形(conformal)沉積製程在凹槽中形成薄的介電材料。可以通過化學氣相沉積、原子層沉積、物理氣相沉積、熱氧化、上述之組合及/或其類似的製程將薄的阻擋層保形地沉積在基板34的前側上方和開口中。可以將導電材料沉積在薄的阻擋層上方和開口中。可以通過電化學鍍覆製程、化學氣相沉積、原子層沉積、物理氣相沉積、上述之組合及/或其類似的製程來形成導電材料。導電材料的示例是銅、鎢、鋁、銀、金、上述之組合及/或其類似的材料。可通過例如化學機械研磨從基板34的前側去除導電材料和阻擋層的多餘部分。因此,貫通孔38可以包括導電材料以及在導電材料和基板34之間的薄的阻擋層。
重分佈結構40形成在基板34的第一表面37上方,並且用於將積體電路裝置(如果有的話)及/或貫通孔38電性連接在一起及/或電性連接到外部裝置。重分佈結構40可以包括一或多個介電層及在介電層中的各別個金屬化圖案。金屬化圖案可以包括通孔及/或跡線以將任何裝置及/或貫通孔38互連在一起及/或互連到外部裝置。金屬化圖案有時也稱為重分佈線路(Redistribution Lines,RDLs)。介電層可以包含氧化矽、氮化矽、碳化矽、氮氧化矽、低K介電材料,例如PSG、BPSG、FSG、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymers)、矽碳材料、其化合物、其複合物、上述之組合等。介電層可以通過本領域已知的任何合適方法形成,例如旋塗(spin-on coating)、化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積等。金屬化圖案可以形成在介電層中,例如通過使用微影技術在介電層上沉積和圖案化光阻材料,以暴露介電層中要成為金屬化圖案的部分。可以使用例如各向異性乾式蝕刻製程之類的蝕刻製程來在介電層中產生與介電層的暴露部分對應的凹槽及/或開口。凹槽及/或開口可以具有擴散阻擋層內襯且填充有導電材料。擴散阻擋層可以包含一或多層氮化鉭(TaN)、鉭(Ta)、氮化鈦(TiN)、鈦(Ti)、鎢鈷(CoW)等,通過原子層沉積(ALD)等方式沉積形成,而導電材料可以包括銅、鋁、鎢、銀、上述之組合等,通過化學氣相沉積、物理氣相沉積等方式沉積形成。可以去除介電層上的任何多餘的擴散阻擋層及/或導電材料,例如通過使用化學機械研磨(CMP)製程。
電性連接件41及電性連接件42形成在重分佈結構40的頂表面處的導電墊上。根據一些實施例,導電墊包括凸塊下金屬層 (under-bump-metallurgies,UBMs)。在所示的實施例中,焊墊(pads)形成在重分佈結構40的介電層的開口中。在另一些實施例中,焊墊(凸塊下金屬層)可延伸穿過重分佈結構40的介電層的開口,並且還在重分佈結構40的頂表面上延伸。
根據一些實施例,電性連接件41/42包括金屬柱41及在金屬柱41上方的金屬蓋層42,金屬蓋層42可以是焊料蓋(solder cap)。包括金屬柱41及金屬蓋層42的電性連接件41/42有時稱為微型凸塊(micro bumps)。根據一些實施例,金屬柱41包含導電材料,例如銅、鋁、金、鎳、鈀等或其組合,並且可以通過濺射、印刷、電鍍、化學鍍(electroless plating)、化學氣相沉積等形成。金屬柱41可以是無焊料的並且具有基本上垂直的側壁。根據一些實施例,金屬蓋層42形成在金屬柱41的頂部。金屬蓋層42可以包含鎳、錫、錫鉛、金、銅、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合,並且可以通過電鍍製程形成。
在第4圖中,封裝部件28及封裝部件44例如通過覆晶接合方法(flip-chip bonding)接合到封裝部件36的第一側,例如通過電性連接件41/42與封裝部件28/44上的金屬柱43形成導電接點39。相應的製程顯示為如第23圖所示的製程流程400中的製程402。金屬柱43可以類似於金屬柱41,故在此不再重複贅述。封裝部件28及封裝部件44可以使用例如拾取和放置工具(pick-and-place tool)放置在電性連接件41/42上。
封裝部件44可以通過與以上參考封裝部件28所述類似的處理來形成。根據一些實施例,封裝部件44包括一或多個記憶體晶粒,例如記憶體晶粒(例如DRAM晶粒、SRAM晶粒、高頻寬記憶體(High-Bandwidth Memory,HBM)晶粒、混合記憶體立方體(Hybrid Memory Cubes,HMC)晶粒、低功率(low-power,LP)雙倍資料率(double data rate,DDR)記憶體模組等)堆疊。在記憶體晶粒堆疊的實施例中,封裝部件44可以包括記憶體晶粒和記憶體控制器,例如帶有記憶體控制器的四或八個記憶體晶粒的堆疊。而且,根據一些實施例,封裝部件44可以具有不同的尺寸(例如不同高度及/或表面積),並且在其他實施例中,封裝部件44可以具有相同的尺寸(例如相同高度及/或表面積)。
根據一些實施例,封裝部件44的高度可以與封裝部件28的高度類似(如第4圖所示),或者根據一些實施例,封裝部件44和封裝部件28可以具有不同的高度。
封裝部件44包括本體46、互連結構48及電性連接件50。封裝部件44的本體46可以包括任何數量的晶粒、基板、電晶體、主動裝置、被動裝置或其類似物。在一些實施例中,本體46可以包括體型半導體基板、絕緣體上覆矽(SOI)基板、多層半導體基板或其類似物。本體46的半導體材料可以選自基板20的相似的候選材料和結構。例如電晶體、電容、電阻、二極體等的裝置可以形成在主動面之中及/或之上。
包括一或多個介電層及各別的金屬化圖案的互連結構48形成在封裝部件44的主動面上。介電層中的金屬化圖案可以例如通過使用通孔及/或跡線在裝置之間路由電信號,並且還可以包含各種電性裝置,例如電容、電阻、電感或其類似物。各種裝置和金屬化圖案可以互連以執行電性功能。此外,在互連結構48之中及/或之上形成例如導電柱(例如,包括例如銅之類的金屬)的電性連接件50,以為電路和裝置提供外部電性連接。根據一些實施例,電性連接件50從互連結構48突出以形成柱狀結構,以便在將封裝部件44接合到其他結構時使用。本領域之普通技術人員將可理解,提供以上示例是為了說明性目的。對於給定的應用,可以適當地使用其他電路。
導電接點39分別通過互連結構48和互連結構24以及電性連接件50和電性連接件26將封裝部件28和封裝部件44中的電路電耦合到封裝部件36中的貫通孔38。
封裝部件28和封裝部件44與封裝部件36之間的接合可以是焊料接合(solder bonding)或金屬與金屬(例如銅與銅)接合。在一些實施例中,封裝部件28和封裝部件44通過回焊製程接合到封裝部件36。在此回焊製程中,電性連接件41/42/43分別與電性連接件26和電性連接件50接觸,並且與重分佈結構40的焊墊接觸,以將封裝部件28和封裝部件44物理和電耦合到封裝部件36。
在第4圖以及後續附圖中,分別示出了用於形成第一封裝和第二封裝的第一封裝區域45A和第二封裝區域45B。切割道區域47在相鄰的封裝區域之間。如第4圖所示,在第一封裝區域45A和第二封裝區域45B中的每一個附接有第一晶粒28和多個第二晶粒44。
在第5圖中,底部填充材料(underfill material)52被分配到封裝部件28/44與相應的下方的重分佈結構40的部分之間的間隙中。相應的製程顯示為如第23圖所示的製程流程400中的製程404。底部填充材料52可以沿著封裝部件28和封裝部件44的側壁向上延伸。底部填充材料52可以是任何可接受的材料,例如聚合物、環氧樹脂、模製底部填充材料(modling underfill)等。底部填充材料52可以在封裝部件28和封裝部件44被附接之後通過毛細管流動過程(capillary flow process)形成。
第6A、6B、6C、6D、6E及6F圖示出了封裝結構的平面圖,該封裝結構包括黏附到封裝部件36的虛設晶粒54。第7圖是示出封裝結構中的虛設晶粒54的剖視圖。第7圖是沿著平面圖第6C圖中的線A-A。可以通過使用例如拾取和放置工具將虛設晶粒54放置在封裝部件36上。在第6A、6B、6C、6D、6E及6F圖中,”HBM”和”SOC”分別標記為示例封裝部件44和示例封裝部件28。應當理解的是,封裝部件44和封裝部件28(在適用時)可以是任何其他類型的裝置。
在第6A圖中,虛設晶粒54附接在切割道區域47內,並且具有沿著切割道區域47延伸的長度方向(lengthwise directions),切割道區域47是沿著第一方向(例如第6A圖中的垂直方向)。在第6B圖中,虛設晶粒54附接在相同區域45A及/或區域45B中的相鄰封裝部件44之間。在第6C圖中,虛設晶粒54附接在切割道區域47內並且沿著切割道區域47延伸,切割道區域47是沿著第一方向和第二方向(例如第6C圖中的垂直方向和水平方向),而且虛設晶粒54還插設在相同區域45A及/或區域45B中的相鄰封裝部件44之間。
在第6D圖中,虛設晶粒54附接在相同區域45A及/或區域45B中的相鄰封裝部件44之間,並且不在切割道區域47內,而是在切割道區域47附近。在第6E圖中,虛設晶粒54的配置與第6D圖中的配置類似,除了虛設晶粒54還附接在區域45A及/或區域45B之與封裝部件44相鄰的角落附近。同樣地,在此實施例中,虛設晶粒54不在切割道區域47內,而是在切割道區域47附近。在第6F圖中,虛設晶粒54附接在區域45A及/或區域45B之與封裝部件44相鄰的角落附近,並且不在切割道區域47內,而是在切割道區域47附近。
放置在切割道區域47內或附近的虛設晶粒54可有助於防止在第一封裝區域45A和第二封裝區域45B中的封裝被分割參見第13圖)期間或之後的翹曲。翹曲的顯著部分的發生是由於在封裝部件44與封裝部件28之間存在空間49(參見第6A圖),在其中填充有模塑料。虛設晶粒54(例如參見第6A圖)包括在空間49內的第一部分以及在該第一部分的相對側的兩個第二部分。虛設晶粒54是剛性的(rigid)以防止翹曲。舉例來說,與沒有任何虛設晶粒54的封裝相比,第6C圖的實施例(以及稍後討論的第15C圖中的經分割的封裝)可以將封裝的翹曲減小多達約60%。
虛設晶粒54可以幫助減少翹曲的一種方式是在實際的分割製程中為封裝提供支撐。虛設晶粒54可以防止翹曲的另一種方式是減小封裝部件36與隨後形成的密封劑(encapsulant)58(參見第8圖)之間的熱膨脹係數(coefficient of thermal expansion,CTE)失配(mismatch),因為虛設晶粒54具有與封裝部件36相似的熱膨脹係數,並且它們減少了封裝中必須的密封劑58的量。
參見第7圖,虛設晶粒54黏附在與封裝部件44相鄰的切割道區域47內。相應的製程顯示為如第23圖所示的製程流程400中的製程406。虛設晶粒54通過附接結構(attaching structure)56附接到封裝部件36。根據一些實施例,附接結構56是可將虛設晶粒54黏附到對應的封裝部件36的黏合劑。根據一些實施例,附接結構56包括一或多個金屬柱以及金屬蓋層(有時稱為微型凸塊),其可將虛設晶粒54接合到封裝部件36。虛設晶粒54可以由矽、介電材料等或上述之組合製成。根據一些實施例,虛設晶粒54是空白晶粒(blank dies),其整體由例如矽的均質材料形成。根據一些實施例,在虛設晶粒54中沒有形成主動裝置、被動裝置、金屬特徵等。虛設晶粒54不具有電性功能。根據一些實施例,虛設晶粒54是已被回收為虛設晶粒54的有缺陷的主動晶粒。根據一些實施例,虛設晶粒54的頂表面低於封裝部件44與封裝部件28中之一或兩者的背側。
在附接結構56是黏合劑的實施例中,附接結構56是在虛設晶粒54的底表面上,並將虛設晶粒54黏附到封裝部件36,例如圖中的重分佈結構40。黏合劑可以是任何合適的黏合劑、環氧樹脂、晶粒黏附薄膜(die attach film,DAF)或其類似物。黏合劑可以被施加到虛設晶粒54的底表面,或者可以被施加到重分佈結構40的表面上方。可以使用例如拾取和放置工具通過黏合劑將虛設晶粒54黏附到重分佈結構40。在黏附虛設晶粒54之前或之後,設置底部填充材料52,然後將其固化。
在附接結構56是微型凸塊的實施例中,附接結構56形成在虛設晶粒54的底表面、封裝部件36的頂表面或兩者上。微型凸塊可以與接合封裝部件44與封裝部件28的微型凸塊(例如電性連接件41/42)同時形成。附接結構56將虛設晶粒54接合到封裝部件36,例如圖中的重分佈結構40。虛設晶粒54的微型凸塊可以與封裝部件44和封裝部件28的電性連接件41/42/43一起進行回焊。
在第8圖中,設置或模製(mold)密封劑58以將封裝部件44和封裝部件28及虛設晶粒54密封於其中。相應的製程顯示為如第23圖所示的製程流程400中的製程408。密封劑58可以是模塑料、環氧樹脂等,並且可以通過壓縮成型(compression molding)、傳送成型(transfer molding)等施加。密封劑58與底部填充材料52可以由不同材料形成。執行固化製程以固化密封劑58,例如熱固化、紫外線(Ultra-Violet,UV)固化等。根據一些實施例,封裝部件28、封裝部件44及虛設晶粒54埋置在密封劑58內。在密封劑58固化之後,可以執行化學機械研磨(CMP)製程或機械研磨製程之類的平坦化製程以去除密封劑58的多餘部分,這些多餘部分是在封裝部件28及/或封裝部件44的頂表面上方。相應的製程顯示為如第23圖所示的製程流程400中的製程410。因此,封裝部件28及/或封裝部件44的頂表面被暴露,並且與密封劑58的頂表面齊平。
根據本揭露一些實施例,虛設晶粒54的頂表面低於密封劑58的頂表面。因此,密封劑58的部分58A覆蓋虛設晶粒54。部分58A的厚度T4是足夠大以為虛設晶粒54提供足夠的保護,以防止虛設晶粒54在隨後的分割製程(如第13圖所示)中發生不希望的破裂。否則,如果厚度T4太小,則在隨後的分割製程中,部分58A可能從虛設晶粒54剝落或剝離。厚度T4也不能夠太大,否則,虛設晶粒54將很薄,並且它們防止所產生的封裝翹曲的能力將受到損害。根據一些實施例,厚度T4大於約5微米(µm),並且可以在約5微米和約600微米之間的範圍內。
第9到12圖示出了在封裝部件36的第二側上形成結構。相應的製程顯示為如第23圖所示的製程流程400中的製程412。在第9圖中,第8圖的結構被翻轉以為在封裝部件36的第二側上的形成做好準備。儘管未示出,但是此結構可以放置在用於第9到12圖的過程的載體或支撐結構(未圖示)上。如第9圖所示,在此處理階段,封裝部件36的基板34與重分佈結構40具有一組合厚度T1,在約50微米和約415微米之間的範圍內,例如約415微米。虛設晶粒54(包括附接結構56)具有一厚度T2,在約30微米和約415微米之間的範圍內,例如約400微米。
在第10圖中,在基板34的第二側上執行薄化製程以將基板34減薄至第二表面60,直到貫通孔38被暴露。薄化製程可以包括回蝕(etch-back)製程、研磨製程等或上述之組合。根據一些實施例,在薄化製程之後,封裝部件36的基板34與重分佈結構40具有一組合厚度T3,在約30微米和約200微米之間的範圍內,例如約52微米。
在第11圖中,在基板34的第二表面60上形成重分佈結構,並且該重分佈結構是用於將貫通孔38電性連接在一起及/或電性連接到外部裝置。重分佈結構包括一或多個介電層62以及在該一或多個介電層62中的金屬化圖案64。金屬化圖案64可以包括通孔及/或跡線以將貫通孔38互連在一起及/或互連到外部裝置。金屬化圖案64有時稱為重分佈線路(RDLs)。介電層62可以包含氧化矽、氮化矽、碳化矽、氮氧化矽、低K介電材料,例如PSG、BPSG、FSG、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymers)、矽碳材料、其化合物、其複合物、上述之組合等。介電層62可以通過本領域已知的任何合適方法形成,例如旋塗、化學氣相沉積、電漿輔助化學氣相沉積、高密度電漿化學氣相沉積等。可以例如通過使用鑲嵌(damascene)製程在介電層62中形成金屬化圖案64。
在第12圖中,電性連接件66也形成在金屬化圖案64上,並且電性耦合到貫通孔38。電性連接件66形成在重分佈結構的頂表面處的金屬化圖案64上。根據一些實施例,金屬化圖案64包括凸塊下金屬層(UBMs)。在所示的實施例中,焊墊(pads)形成在重分佈結構的介電層62的開口中。在另一些實施例中,焊墊(凸塊下金屬層)可延伸穿過重分佈結構的介電層62的開口,並且還在重分佈結構的頂表面上延伸。
根據一些實施例,電性連接件66是焊球及/或金屬凸塊,例如球柵陣列(ball grid array,BGA)球,可控塌陷晶片連接(controlled collapse chip connection,C4)微型凸塊,化鎳浸金(Electro-less nickel immersion gold,ENIG)形成的凸塊、化鎳浸鈀金(Electroless Nickel Electroless Palladium Immersion Gold,ENEPIG)形成的凸塊或其類似物。電性連接件66可以包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。根據另一些實施例,電性連接件66是通過濺射、印刷、電鍍、化學鍍、化學氣相沉積等形成的金屬柱(例如銅柱)。金屬柱可以是無焊料的並且具有基本上垂直的側壁。根據一些實施例,金屬蓋層(圖未示)形成在金屬柱電性連接件66的頂部。金屬蓋層可以包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合,並且可以通過電鍍製程形成。
電性連接件66可用於接合到額外的電子部件,其可為半導體基板、印刷電路板(Printed Circuit Board,PCB)等(參見第14圖中的300)。
在第13圖中,沿著切割道區域47在相鄰區域45A與區域45B之間將封裝部件36和虛設晶粒54進行分割,以形成部件封裝(component packages)200。相應的製程顯示為如第23圖所示的製程流程400中的製程414。每個部件封裝200(除了其他特徵以外)包括封裝部件28、封裝部件36、封裝部件44及虛設晶粒54的剩餘部分54’。分割製程可以通過鋸切、切割等來進行,並且可以使用刀具來執行。每個虛設晶粒54可以具有留在個別的切縫的相對側的剩餘部分54’。如上所述,虛設晶粒54的剩餘部分54’有助於減小分割製程期間和之後引起的應力及翹曲。覆蓋虛設晶粒54的密封劑58的部分58A防止虛設晶粒54在分割製程期間發生破裂。否則,如果未形成部分58A,則虛設晶粒54可能因為切割刀具的機械力而破裂。
在分割製程之後,虛設晶粒54的剩餘部分54’具有與部件封裝200的側向範圍相接(或齊平)的側壁表面(參見例如第13及14圖)。
第14圖示出了部件封裝200附接到封裝部件300上以形成封裝結構302。電性連接件66與封裝部件300的接合焊墊對準並且放置在其上。電性連接件66可以經回焊以在封裝部件300與封裝部件36之間建立接合。封裝部件300可以包括封裝基板,例如在其中包括核心的積層基板(build-up substrate)、包括多個層壓介電薄膜的層壓基板(laminate substrate)、印刷電路板(PCB)等。封裝部件300還可以包括與部件封裝200相對的電性連接件(圖未示),例如焊球,以允許將封裝部件300安裝到另一裝置。底部填充材料(圖未示)可以被分配在部件封裝200與封裝部件300之間並且圍繞電性連接件66。底部填充材料可以是任何可接受的材料,例如聚合物、環氧樹脂、模製底部填充材料(modling underfill)等。
第15到19圖示出了根據本揭露一些實施例的形成封裝結構的中間階段的平面圖和剖視圖。除非另有說明,否則這些實施例中的部件的材料及形成過程與在第1-5、6A、6B、6C、6D、6E、6F及7-14圖所示的實施例中由相同的參考符號標記的部件的材料及形成過程基本上相同。因此,可以在對第1-5、6A、6B、6C、6D、6E、6F及7-14圖所示的實施例的討論中找到關於第15到19圖所示的部件的形成過程及材料的細節。這些實施例的初始步驟基本上與第1-5、6A、6B、6C、6D、6E及6F圖所示的相同。
第15圖示出了根據一些實施例之虛設晶粒54的平面圖。虛設晶粒54包括部分54B以及在部分54B的相對側上的多個部分54A。如第16圖所示,虛設晶粒的部分54A較部分54B厚,因此在部分54B上方形成凹槽55。舉例來說,如第16圖所示,虛設晶粒的部分54A具有厚度T5,而部分54B具有小於厚度T5的厚度T6,導致凹槽55延伸到虛設晶粒54中。根據一些實施例,差異(T5-T6)大於約5微米,並且可以在約5微米和600微米之間的範圍內。部分54B的寬度W1(參見第15圖)大於分割製程(參見第13圖)的切縫,並具有適當的製程餘量(process margin)。此外,寬度W1是足夠大,使得在分割製程之後可在切縫的相對側上留下剩餘部分54B。寬度W1可以大於約30微米,並且可以在約50微米和約1000微米之間的範圍內。
參見第16圖,虛設晶粒54附接到封裝部件32。根據一些實施例,虛設晶粒54的部分54B位在切割道區域47內,並且虛設晶粒54的其中一個部分54A位在部分54B與區域45A之間,而另一個部分54A則位在部分54B與區域45B之間。
第17圖進一步示出了通過密封劑58的密封製程。根據一些實施例,密封劑58被設置在封裝部件28和封裝部件44與虛設晶粒54之間的間隙中。而且,密封劑58被設置在虛設晶粒54的凹槽55中。然後,執行平坦化製程以去除多餘的密封劑58。在平坦化製程之後,密封劑58的部分58B留在凹槽55中,並且具有厚度T4。厚度T4可以大於約5微米,並且可以在約5微米和約600微米之間的範圍內。
在後續過程中,對第17圖所示的結構執行如第9到12圖所示的製程,並且產生如第18圖所示的結構。製程的細節與上述第9到12圖中所討論的相似,故在此不再重複贅述。在產生的部件封裝200中,虛設晶粒54的部分54B具有暴露的側壁。而且,密封劑58的部分58B從虛設晶粒54的部分54B的邊緣延伸到封裝200的邊緣,並且密封劑58的部分58B覆蓋(以倒置的方式觀看)虛設晶粒54的部分54B。在形成部件封裝200的分割製程中,密封劑58的部分58B防止虛設晶粒54的破裂。密封劑58的部分58B的寬度W2不能夠太小,否則,部分58B將從虛設晶粒54剝落。根據一些實施例,寬度W2大於約50微米,並且可以在約60微米和約500微米之間的範圍內。第19圖示出了部件封裝200與封裝部件300的接合以形成封裝結構302。
第20A、20B、20C、20D、20E及20F圖分別示出了與第6A、6B、6C、6D、6E及6F圖所示的每個虛設晶粒54實施例相對應的封裝結構302的平面圖。這些實施例是對稱的,具有封裝部件28以及在封裝部件28的相對側的封裝部件44和虛設晶粒54。
第21A、21B、21C、21D、21E及21F圖分別示出了與第6A、6B、6C、6D、6E及6F圖所示的每個虛設晶粒54實施例相對應的其他實施例中的經分割的封裝結構的平面圖。在這些實施例中,經分割的封裝結構是非對稱的,因為封裝部件44和虛設晶粒54僅在封裝部件28的一側(例如第21A、21B、21C、21D、21E及21F圖中的平面圖的上側)。可以使用與上述第1到5及7到14圖中所討論的相似的材料、結構和製程來製造這些封裝結構,故在此不再重複描述。
第22A、22B及22C圖分別示出了在與第6A、6B及6C圖相似的處理點和在虛設晶粒54配置中相似的平面圖,除了在這些實施例中,在每個封裝結構中存在更多的封裝部件44。可以使用與上述第1到5及7到14圖中所討論的相似的材料、結構和製程來製造這些封裝結構,故在此不再重複描述。
第22D圖示出了類似於第22A到22C圖中的虛設晶粒54配置的另一些實施例的平面圖,除了在這些實施例中,虛設晶粒54是在區域45A及區域45B之中並且不在切割道區域47內。可以使用與上述第1到5及7到14圖中所討論的相似的材料、結構和製程來製造這些封裝結構,故在此不再重複描述。這類型的配置(例如,切割道區域47內沒有虛設晶粒54)也可以應用於上述的任何配置。
應當理解的是,對於基於第6A、6B、6C、6D、6E及6F圖所形成的每個封裝結構,以及在第20A、20B、20C、20D、20E及20F圖、第21A、21B、21C、21D、21E及21F以及第22A、22B、22C及第22D圖所示的每個封裝結構中,可以存在封裝劑58的部分58A(參見第14圖)或部分58B(參見第19圖)。
在上面說明的實施例中,根據本揭露一些實施例討論了一些製程和特徵。也可以包括其他的特徵和製程。舉例來說,可以包括測試結構以幫助對3D封裝或3DIC裝置進行驗證測試。這些測試結構可以包括例如形成在重分佈層中或基板上的測試墊,該些測試墊允許測試3D封裝或3DIC裝置、使用探針及/或探針卡等。可以對中間結構以及最終結構進行驗證測試。此外,本文公開的結構和方法可以與測試方法結合使用,該測試方法包含了已知的優良晶粒的中間驗證,以提高成品率及降低成本。
本揭露實施例具有一些有利特徵。與主動晶粒相鄰的虛設晶粒可以幫助減小相應的封裝結構的翹曲。這種封裝結構的翹曲減小使得封裝結構更可靠。通過將密封劑的某些部份留在虛設晶粒的頂部上,可以防止虛設晶粒的不希望的破裂。
根據本揭露的一些實施例,提供一種形成封裝結構的方法,包括將第二封裝部件接合到第一封裝部件,將第三封裝部件接合到第一封裝部件,附接虛設晶粒到第一封裝部件上,以及將第二封裝部件、第三封裝部件及虛設晶粒密封在密封劑內。所述形成封裝結構的方法還包括執行平坦化製程以使第二封裝部件的頂表面與密封劑的頂表面齊平,其中在平坦化製程之後,密封劑的上部與虛設晶粒重疊。所述形成封裝結構的方法更包括鋸穿虛設晶粒以將虛設晶粒分離成第一虛設晶粒部分以及第二虛設晶粒部分,其中密封劑的上部被鋸穿。在一些實施例中,密封劑的上部的厚度大於約5微米。在一些實施例中,第二封裝部件與第三封裝部件彼此隔開一空間,其中虛設晶粒包括位在所述空間內的第一部分,以及位在所述空間的相對側的多個第二部分。在一些實施例中,在鋸穿虛設晶粒時,整個虛設晶粒是被密封劑覆蓋。在一些實施例中,在鋸穿虛設晶粒時,虛設晶粒包括暴露的第一頂表面以及被密封劑的上部覆蓋的第二頂表面(參見第18圖)。在一些實施例中,在鋸穿之操作之後,在密封劑的上部之平面圖中,密封劑的上部具有一長度以及小於長度的一寬度,其中寬度大於約50微米。在一些實施例中,虛設晶粒包含矽。在一些實施例中,平坦化製程被執行直到第三封裝部件被進一步露出。
根據本揭露的一些實施例,提供一種形成封裝結構的方法,包括將第一封裝部件接合到第二封裝部件,其中第一封裝部件包括裝置晶粒。所述形成封裝結構的方法還包括附接虛設晶粒到第二封裝部件上,其中虛設晶粒包括凹槽。所述形成封裝結構的方法還包括將第一封裝部件和虛設晶粒密封在密封劑內,其中密封劑包括填充該凹槽的部分。所述形成封裝結構的方法更包括使用刀具執行分割製程以形成一封裝,其中所述封裝包括第一封裝部件、一部分的第二封裝部件以及一部分的虛設晶粒,且其中刀具切穿密封劑在凹槽內的部分。在一些實施例中,密封劑在凹槽內的部分被切成兩個部分。在一些實施例中,凹槽沿著一長度方向(lengthwise direction)是細長的,且刀具是沿著長度方向切割。在一些實施例中,所述形成封裝結構的方法更包括在密封之操作之後和分割製程之前,執行平坦化製程以暴露虛設晶粒的一表面。在一些實施例中,密封劑在凹槽內且被刀具切穿的部分具有一厚度,所述厚度之範圍在約5微米和約600微米之間。在一些實施例中,在分割製程之後,密封劑在凹槽內的部分具有一殘留部分(參見第18圖之部分58B)在所述封裝內,且密封劑的殘留部分具有一寬度,所述寬度之範圍在約60微米和約500微米之間。在一些實施例中,當執行分割製程時,第一封裝部件通過密封劑暴露。
根據本揭露的一些實施例,提供一種積體電路封裝,包括第一封裝部件、第二封裝部件、虛設晶粒以及密封劑。第二封裝部件是在第一封裝部件上方且接合到第一封裝部件。虛設晶粒是在第一封裝部件上方且附接到第一封裝部件上,其中虛設晶粒具有第一頂表面以及低於第一頂表面的第二頂表面。密封劑將虛設晶粒密封在其中,其中密封劑包括與虛設晶粒的第二頂表面重疊(overlapping)的第一部分,且虛設晶粒的第一頂表面通過密封劑暴露。在一些實施例中,所述第二頂表面延伸到積體電路封裝的邊緣。在一些實施例中,積體電路封裝的一側壁包括虛設晶粒的一側壁。在一些實施例中,密封劑更包括在虛設晶粒與第一封裝部件之間的第二部分。在一些實施例中,所述積體電路封裝更包括第三封裝部件,第三封裝部件是在第一封裝部件上方且接合到第一封裝部件,其中在積體電路封裝的平面圖中,虛設晶粒具有一長度方向,其中,從虛設晶粒的第一端開始且垂直於所述長度方向的第一直線穿過第二封裝部件,且從虛設晶粒的第二端開始且垂直於所述長度方向的第二直線穿過第三封裝部件。
以上雖然詳細描述了本揭露的實施例及它們的優勢,但應該理解,在不背離所附請求項限定的本揭露的精神和範圍的情況下,對本揭露可作出各種變化、替代和修改。舉例而言,本領域技術人員將容易理解,可以改變本文中描述的許多特徵、功能、製程和材料而仍保持在本揭露的範圍內。此外,本申請的範圍不旨在限制於說明書中所述的製程、機器、製造、物質組成、工具、方法和步驟的特定實施例。作為本領域的普通技術人員將容易地從本揭露中理解,根據本揭露,可以利用現有的或今後將被開發的、執行與在本揭露所述的對應實施例基本相同的功能或實現基本相同的結果的製程、機器、製造、物質組成、工具、方法或步驟。因此,所附請求項旨在將這些製程、機器、製造、物質組成、工具、方法或步驟包括它們的範圍內。此外,每一個請求項構成一個單獨的實施例,且不同請求項和實施例的組合都在本揭露的範圍內。
10:晶圓 20:基板 22:主動面 24:互連結構 26:電性連接件 28:封裝部件/第一晶粒 32:封裝部件 34:基板 36:封裝部件 37:第一表面 38:貫通孔 39:導電接點 40:重分佈結構 41:電性連接件/金屬柱 42:電性連接件/金屬蓋層 43:電性連接件/金屬柱 44:封裝部件/第二晶粒 45A:(第一封裝)區域 45B:(第二封裝)區域 46:本體 47:切割道區域 48:互連結構 49:空間 50:電性連接件 52:底部填充材料 54:虛設晶粒 54A,54B:部分 54’:剩餘部分 55:凹槽 56:附接結構 58:密封劑 58A,58B:部分 60:第二表面 62:介電層 64:金屬化圖案 66:電性連接件 200:部件封裝 300:封裝部件 302:封裝結構 400:製程流程 402,404,406,408,410,412,414:製程 T1:組合厚度 T2:厚度 T3:組合厚度 T4:厚度 T5:厚度 T6:厚度 W1:寬度 W2:寬度
第1-5、6A、6B、6C、6D、6E、6F及7-14圖是根據一些實施例的形成封裝結構的示例製程中的剖視圖和平面圖。 第15到19圖是根據一些實施例的形成封裝結構的示例製程中的剖視圖和平面圖。 第20A到20F圖示出了根據一些實施例的封裝結構的平面圖。 第21A到21F圖示出了根據一些實施例的封裝結構的平面圖。 第22A到22D圖示出了根據一些實施例的封裝結構的平面圖。 第23圖示出了根據一些實施例的用於形成封裝結構的製程流程。
28:封裝部件/第一晶粒
32:封裝部件
34:基板
36:封裝部件
38:貫通孔
39:導電接點
44:封裝部件/第二晶粒
45A:(第一封裝)區域
45B:(第二封裝)區域
47:切割道區域
52:底部填充材料
54:虛設晶粒
54’:剩餘部分
56:附接結構
58:密封劑
58A:部分
60:第二表面
62:介電層
64:金屬化圖案
66:電性連接件
200:部件封裝

Claims (9)

  1. 一種形成封裝結構的方法,包括:將一第二封裝部件接合到一第一封裝部件;將一第三封裝部件接合到該第一封裝部件;附接一虛設晶粒到該第一封裝部件上;將該第二封裝部件、該第三封裝部件及該虛設晶粒密封在一密封劑內;執行一平坦化製程以使該第二封裝部件的一頂表面與該密封劑的一頂表面齊平,其中在該平坦化製程之後,該密封劑的一上部與該虛設晶粒重疊;以及鋸穿該虛設晶粒以將該虛設晶粒分離成一第一虛設晶粒部分以及一第二虛設晶粒部分,其中該密封劑的該上部被鋸穿。
  2. 如請求項1之形成封裝結構的方法,其中該第二封裝部件與該第三封裝部件彼此隔開一空間,其中該虛設晶粒包括:一第一部分,位在該空間內;以及複數個第二部分,位在該空間的相對側。
  3. 如請求項1之形成封裝結構的方法,其中在鋸穿該虛設晶粒時,整個該虛設晶粒係被該密封劑覆蓋。
  4. 如請求項1之形成封裝結構的方法,其中在鋸穿該虛設晶粒時,該虛設晶粒包括暴露的一第一頂表面以及被該密封劑的該上部覆蓋的一第二頂表面。
  5. 一種形成封裝結構的方法,包括:將一第一封裝部件接合到一第二封裝部件,其中該第一封裝部件包括一裝置晶粒;附接一虛設晶粒到該第二封裝部件上,其中該虛設晶粒包括一凹槽; 將該第一封裝部件和該虛設晶粒密封在一密封劑內,其中該密封劑包括填充該凹槽的一部分;以及使用一刀具執行一分割製程以形成一封裝,其中該封裝包括該第一封裝部件、一部分的該第二封裝部件以及一部分的該虛設晶粒,且其中該刀具切穿該密封劑在該凹槽內的該部分。
  6. 如請求項5之形成封裝結構的方法,其中該凹槽沿著一長度方向是細長的,且該刀具係沿著該長度方向切割。
  7. 如請求項5之形成封裝結構的方法,更包括:在該密封之操作之後和該分割製程之前,執行一平坦化製程以暴露該虛設晶粒的一表面。
  8. 如請求項5之形成封裝結構的方法,其中當執行該分割製程時,該第一封裝部件通過該密封劑暴露。
  9. 一種積體電路封裝,包括:一第一封裝部件;一第二封裝部件,在該第一封裝部件上方且接合到該第一封裝部件;一虛設晶粒,在該第一封裝部件上方且附接到該第一封裝部件上,其中該虛設晶粒具有一第一頂表面以及低於該第一頂表面的一第二頂表面;以及一密封劑,將該虛設晶粒密封在其中,其中該密封劑包括與該虛設晶粒的該第二頂表面重疊的一第一部分,且該虛設晶粒的該第一頂表面通過該密封劑暴露,其中該第二頂表面延伸到該積體電路封裝的一邊緣,且該積體電路封裝的一側壁包括該虛設晶粒的一側壁。
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DE102019118624A1 (de) 2020-11-19
US20230092361A1 (en) 2023-03-23
TW202044432A (zh) 2020-12-01
CN111952251A (zh) 2020-11-17
KR102241698B1 (ko) 2021-04-20
DE102019118624B4 (de) 2021-03-18
CN111952251B (zh) 2022-09-20
US10861799B1 (en) 2020-12-08
US11515267B2 (en) 2022-11-29

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