JP2011249552A - 制御回路 - Google Patents
制御回路 Download PDFInfo
- Publication number
- JP2011249552A JP2011249552A JP2010121067A JP2010121067A JP2011249552A JP 2011249552 A JP2011249552 A JP 2011249552A JP 2010121067 A JP2010121067 A JP 2010121067A JP 2010121067 A JP2010121067 A JP 2010121067A JP 2011249552 A JP2011249552 A JP 2011249552A
- Authority
- JP
- Japan
- Prior art keywords
- input port
- input
- semiconductor package
- control circuit
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
【解決手段】 動作環境において接続優先順位の異なる各種入力ポートを設けてなるBGA型の半導体パッケージ1を備えた制御回路であって、半導体パッケージ1は、第1の入力ポート31と、この第1の入力ポート31と隣り合い、且つ入力極性が異なり、且つ第1の入力ポート31よりも接続優先順位が高い第2の入力ポート32とを設けてなり、第2の入力ポート32の入力インピーダンスに対して第1の入力ポート31の入力インピーダンスを大きくしている。
【選択図】 図4
Description
2 筐体
3 半田ボール
31 第1の入力ポート
32 第2の入力ポート
4 回路基板
5 抵抗素子
6 電源回路
7 表示手段
Claims (4)
- 動作環境において接続優先順位の異なる各種入力ポートを設けてなるBGA型の半導体パッケージを備えた制御回路であって、
前記半導体パッケージは、第1の入力ポートと、この第1の入力ポートと隣り合い、且つ入力極性が異なり、且つ前記第1の入力ポートよりも接続優先順位が高い第2の入力ポートとを設けてなり、前記第2の入力ポートの入力インピーダンスに対して前記第1の入力ポートの入力インピーダンスを大きくすることを特徴とする制御回路。 - 前記半導体パッケージに接続される表示手段を備え、
前記半導体パッケージは、前記入力ポートからの入力情報に基づいて前記表示手段を駆動制御してなることを特徴とする請求項1に記載の制御回路。 - 前記半導体パッケージは、前記第1の入力ポートと前記第2の入力ポートとが短絡しているか否かを判定する判定処理を行い、前記短絡状態の場合には、前記表示手段を用いて異常状態を報知してなることを特徴とする請求項1に記載の制御回路。
- 前記半導体パッケージの前記第2の入力ポートは、演算処理、または表示制御処理に関する入力を行い、前記第1の入力ポートは、少なくとも表示制御処理に関係ない入力を行い、抵抗素子を介して前記第1の入力ポートと電源接続または接地接続することによって入力インピーダンスを設定してなることを特徴とする請求項1に記載の制御回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010121067A JP5807834B2 (ja) | 2010-05-27 | 2010-05-27 | 制御回路 |
PCT/JP2011/061140 WO2011148802A1 (ja) | 2010-05-27 | 2011-05-16 | 制御回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010121067A JP5807834B2 (ja) | 2010-05-27 | 2010-05-27 | 制御回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011249552A true JP2011249552A (ja) | 2011-12-08 |
JP5807834B2 JP5807834B2 (ja) | 2015-11-10 |
Family
ID=45003793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010121067A Active JP5807834B2 (ja) | 2010-05-27 | 2010-05-27 | 制御回路 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5807834B2 (ja) |
WO (1) | WO2011148802A1 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277574A (ja) * | 1999-03-23 | 2000-10-06 | Casio Comput Co Ltd | Lsiチップおよびその接合試験方法 |
JP2010093109A (ja) * | 2008-10-09 | 2010-04-22 | Renesas Technology Corp | 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0460472A (ja) * | 1990-06-28 | 1992-02-26 | Fujitsu Ltd | バンプ間ショートの予知方法 |
JP4412250B2 (ja) * | 2005-07-08 | 2010-02-10 | トヨタ自動車株式会社 | 半導体装置およびその端子間短絡検出方法 |
-
2010
- 2010-05-27 JP JP2010121067A patent/JP5807834B2/ja active Active
-
2011
- 2011-05-16 WO PCT/JP2011/061140 patent/WO2011148802A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277574A (ja) * | 1999-03-23 | 2000-10-06 | Casio Comput Co Ltd | Lsiチップおよびその接合試験方法 |
JP2010093109A (ja) * | 2008-10-09 | 2010-04-22 | Renesas Technology Corp | 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法 |
Also Published As
Publication number | Publication date |
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JP5807834B2 (ja) | 2015-11-10 |
WO2011148802A1 (ja) | 2011-12-01 |
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