US20140091462A1 - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
US20140091462A1
US20140091462A1 US13/729,963 US201213729963A US2014091462A1 US 20140091462 A1 US20140091462 A1 US 20140091462A1 US 201213729963 A US201213729963 A US 201213729963A US 2014091462 A1 US2014091462 A1 US 2014091462A1
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Prior art keywords
dielectric layer
layer
semiconductor chip
conductive trace
semiconductor package
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Abandoned
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US13/729,963
Inventor
Chia-Cheng Chen
Chi-Ching Ho
Shao-Tzu Tang
Yu-Che Liu
Ying-Chou Tsai
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHIA-CHENG, HO, CHI-CHING, LIU, YU-CHE, TANG, SHAO-TZU, TSAI, YING-CHOU
Publication of US20140091462A1 publication Critical patent/US20140091462A1/en
Priority to US15/632,669 priority Critical patent/US9991197B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a carrier-free semiconductor package and a fabrication method thereof.
  • a QFN (Quad Flat Non-leaded) semiconductor package is a lead frame based chip scale package, which is characterized by the fact that the leads thereof do not extend out from the package sides as in a conventional quad flat package (QFP), thereby reducing the overall package size.
  • QFP quad flat package
  • the QFN package thickness cannot be further reduced to meet the demands for lighter, thinner, shorter and smaller semiconductor product trends. Therefore, carrier-free semiconductor packages have been developed to reduce the thickness of the overall package size by dispensing with a lead frame.
  • FIGS. 1A to 1D are schematic cross-sectional views illustrating a fabrication method of a semiconductor package 1 according to the prior art.
  • the surface of a metal carrier 10 is partially removed by etching to form a plurality of wire bonding pads 101 and at least a die attach pad 102 .
  • solder mask layer 11 such as green paint is formed on the metal carrier 10 , and the wire bonding pads 101 and the die attach pad 102 covered by an anti-oxidation layer 15 are exposed from the solder mask layer 11 .
  • a semiconductor chip 17 is disposed on the die attach pad 102 through an adhesive 171 and electrically connected to the wire bonding pads 101 through a plurality of bonding wires 170 such as gold wires. Then, an encapsulant 18 is formed on the solder mask layer 11 to encapsulate the semiconductor chip 17 and the bonding wires 170 .
  • the metal carrier 10 is removed by etching to expose lower surfaces of the wire bonding pads 101 and the die attach pad 102 .
  • the wire bonding pads 101 located outside around the periphery of the semiconductor chip 17 are distant from the electrode pads 17 a of the semiconductor chip 17 , therefore longer bonding wires 170 are required, thereby increasing material cost and adversely affecting the miniaturization of the semiconductor package 1 .
  • FIGS. 2A to 2E Another fabrication method of a semiconductor package 2 has been developed, as shown in FIGS. 2A to 2E .
  • a conductive trace layer 24 is formed on a copper carrier 20 by electroplating.
  • the conductive trace layer 24 has a plurality of bonding pads 241 , a plurality of connection pads 242 , and at least a die attach pad 243 .
  • the conductive trace layer 24 is made of Pd/Ni/Pd/Au.
  • At least a semiconductor chip 27 is disposed on the die attach pad 243 through an adhesive 271 such as silver epoxy, and electrically connected to the bonding pads 241 through a plurality of bonding wires 270 .
  • an encapsulant 28 is formed on the copper carrier 20 to encapsulate the semiconductor chip 27 and the conductive trace layer 24 .
  • the copper carrier 20 is almost removed by etching.
  • an ultra-thin copper layer 25 is formed on the bonding pads 241 , the connection pads 242 , and the die attach pad 243 .
  • a solder mask layer 21 such as green paint is formed on the encapsulant 28 and a plurality of openings 210 are formed in the solder mask layer 21 for exposing portions of the ultra-thin copper layer 25 on the connection pads 242 and the die attach pad 243 .
  • an electroplating process is performed to form a plurality of solder balls 29 on the ultra-thin copper layer 25 at the openings 210 of the solder mask layer 21 .
  • the conductive trace layer 24 is formed first and then the solder mask layer 21 is formed to cover a portion of the conductive trace layer 24 .
  • the solder mask layer 21 has a poor bonding with the gold material of the conductive trace layer 24 (the ultra-thin copper layer 25 has negligible effect on the bonding between the solder mask layer 21 and the conductive trace layer 24 ). Therefore, after the solder balls 29 are formed, delamination can easily occur around the peripheries of the openings of the solder mask layer 21 , thus easily causing solder ball drop failure and consequently reducing package reliability.
  • the gold material used in the conductive trace layer 24 results in a high fabrication cost.
  • the present invention provides a semiconductor package, which comprises: a dielectric layer used for fabricating built-up layer structures having opposite first and second surfaces, and a plurality of openings penetrating the first and second surfaces; a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer; at least a semiconductor chip attached to the first surface of the dielectric layer having a plurality of electrode pads; and a plurality of bonding wires electrically connecting the electrode pads of the semiconductor chip to the bonding pads.
  • the conductive trace layer can further have a die attach pad on which the semiconductor chip is mounted, and the semiconductor chip is electrically connected to the die attach pad.
  • the bonding pads can be formed outside the periphery of the semiconductor chip.
  • the bonding pads can be formed between the connection pads and the semiconductor chip.
  • the present invention provides another semiconductor package, which comprises: a dielectric layer used for fabricating built-up layer structures having opposite first and second surfaces, and a plurality of openings penetrating the first and second surfaces; a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer; a plurality of conductive bumps formed on the respective bonding pads; and at least a semiconductor chip disposed on the conductive bumps, wherein the semiconductor chip has a plurality of electrode pads electrically connected to the bonding pads through the conductive bumps.
  • the present invention further provides a fabrication method of a semiconductor package, which comprises the steps of: providing a carrier having a dielectric layer formed on a surface thereof, wherein the dielectric layer is used for fabricating built-up layer structures; forming a conductive trace layer on the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad; attaching at least a semiconductor chip to the dielectric layer and electrically connecting the bonding pads to the semiconductor chip; forming an encapsulant over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer; removing the carrier while retaining the dielectric layer on the encapsulant; and forming a plurality of openings, through which the connection pads are exposed, penetrating the dielectric layer.
  • the carrier can be made of metal.
  • the conductive trace layer can be formed by electroplating.
  • the semiconductor chip can be electrically connected to the bonding pads through bonding wires or conductive bumps.
  • the conductive trace layer can further have a die attach pad on which the semiconductor chip is mounted.
  • the carrier can be removed by etching.
  • the dielectric layer can be made of a material selected from the groups consisting of polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, and a glass ceramic and epoxy composite material.
  • a surface treated layer can further be formed on the bonding pads.
  • an adhesive can further be formed between the dielectric layer and the semiconductor chip.
  • an encapsulant can further be formed over the first surface of the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer.
  • a plurality of solder balls can further be formed at the openings of the dielectric layer, respectively.
  • a dielectric layer made of a material used for fabricating built-up layer structures is formed to serve as an etching stop layer and a solder mask layer so as for a conductive trace layer made of copper or aluminum to be formed thereon. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer and dispenses with the conventional solder mask layer and electroless plated copper layer, thereby reducing fabrication cost.
  • the present invention prevents the delamination occurring around the peripheries of the openings of the dielectric layer, thus avoiding solder ball drop failure and improving product reliability.
  • the dielectric layer provides a strong support to the package structure so as to avoid solder ball drop failure.
  • FIGS. 1A to 1D are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the prior art, wherein FIG. 1 D′ is a schematic upper view of part of the semiconductor package and FIG. 1D is a schematic cross-sectional view along a sectional line A-A of FIG. 1 D′;
  • FIGS. 2A to 2E are schematic cross-sectional views illustrating another fabrication method of a semiconductor package according to the prior art
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the present invention, wherein FIG. 3 F′ shows another embodiment of FIG. 3F , and FIG. 3 F′′ is a schematic upper view of FIG. 3 F′ without the encapsulant;
  • FIG. 4 is a schematic cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view illustrating another embodiment of FIG. 4 .
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the present invention.
  • a carrying structure 3 a which has a carrier 30 , a dielectric layer 31 used for fabricating built-up layer structures, and a conductive layer 32 . Further, a first patterned resist layer 33 a is formed on the conductive layer 32 for exposing portions of the conductive layer 32 .
  • the dielectric layer 31 can be made of one of the materials selected from polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, or a glass ceramic and epoxy composite material.
  • ABF Ajinomoto Build-up Film
  • the dielectric material of the present invention facilitates to alleviate the CTE mismatch between the encapsulant and the dielectric material and resist cracking while being pressed during a subsequent molding process.
  • the conductive trace layer 34 has a plurality of traces 340 (as shown in FIG. 3 F′′), a plurality of bonding pads 341 and connection pads 342 connected through the traces 340 , and at least a die attach pad 343 .
  • the die attach pad 343 is used for a semiconductor chip to be mounted thereon and not connected to the traces 340 .
  • the die attach pad 343 can be electrically grounded and connected to the connection pads 342 , 342 ′ through the traces 340 .
  • the carrier 30 and the conductive layer 32 are substantially made of metal such as copper or aluminum.
  • the conductive layer 32 serves as a current conductive path for electroplating.
  • the conductive trace layer 34 is substantially made of copper or aluminum.
  • the carrier 30 , the dielectric layer 31 and the conductive layer 32 form a carrying structure 3 a.
  • the bonding pads 341 serve as wire bonding pads and are formed outside the periphery of the die attach pad 343 and located between the die attach pad 343 and the connection pads 342 , 342 ′.
  • the dielectric layer 31 has an upper surface, i.e., a first surface 31 a and a lower surface, i.e., a second surface 31 b that is opposite to the first surface 31 a .
  • the dielectric layer 31 a is bonded to the conductive layer 32 through the first surface 31 a and bonded to the carrier 30 through the second surface 31 b.
  • a second patterned resist layer 33 b is formed on the first patterned resist layer 33 a and the bonding pads 341 are exposed from the second patterned resist layer 33 b . Then, a surface treated layer 35 is formed on the bonding pads 341 .
  • a third patterned resist layer 33 c is formed on the lower side of the carrier 30 such that a support layer 36 a is formed on the carrier 30 .
  • the support layer 36 a and the surface treated layer 35 are made of same materials, such as electroless nickel/gold, ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold), DIG (Direct Immersion Gold) or electroplated nickel/electroless palladium/electroplated gold.
  • ENEPIG Electroless Nickel/Electroless Palladium/Immersion Gold
  • DIG Direct Immersion Gold
  • electroplated nickel/electroless palladium/electroplated gold such as electroless nickel/gold, ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold), DIG (Direct Immersion Gold) or electroplated nickel/electroless palladium/electroplated gold.
  • the first, second and third patterned resist layers 33 a , 33 b and 33 c and the conductive layer 32 under the first patterned resist layer 33 a are removed.
  • a semiconductor chip 37 is disposed on the die attach pad 343 through an adhesive 371 such as a silver epoxy and electrically connected to the bonding pads 341 through a plurality of bonding wires 370 .
  • an encapsulant 38 is formed over the dielectric layer 31 to encapsulate the semiconductor chip 37 and the conductive trace layer 34 .
  • the semiconductor chip 37 has a plurality of electrode pads 37 a that are electrically connected to the bonding pads 341 through the bonding wires 370 .
  • the bonding pads 341 are formed outside around the periphery of the semiconductor chip 37 and located between the semiconductor chip 37 and the connection pads 342 , 342 ′.
  • the bonding pads 341 can be formed between the connection pads 342 , 342 ′.
  • the die attach pad 343 can be omitted and the semiconductor chip 37 can be directly disposed on the first surface 31 a of the dielectric layer 31 .
  • the present invention overcomes the conventional disadvantage of bonding wire crossing, thus preventing short circuits in the package.
  • the layout of the bonding pads 341 becomes more flexible and that of the connection pads 342 , 342 ′ is, therefore, not limited by the wire bonding range of the bonding wires 370 .
  • the present invention shortens the distance between the bonding pads 341 and the electrode pads 37 a (including I/O contact pads) of the semiconductor chip 37 , thereby shortening the length of the bonding wires 370 and consequently reducing the cost and facilitating the miniaturization of the semiconductor package 3 .
  • the total number of the connection pads 342 , 342 ′ of the conductive trace layer 34 can be greater than or equal to the number of the electrode pads 37 a (including I/O contact pads) of the semiconductor chip 37 .
  • a portion of the carrier 30 that is exposed from the support layer 36 a is removed by etching while the dielectric layer 31 remains on the encapsulant 38 , thereby forming a support structure 36 on the second surface 31 b of the dielectric layer 31 .
  • a plurality of openings 310 are formed on the second surface 31 b of the dielectric layer 31 to expose the connection pads 342 , 342 ′ and the die attach pad 343 , and a plurality of solder balls 39 are formed on the connection pads 342 , 342 ′ and the die attach pad 343 at the openings 310 of the dielectric layer 31 .
  • a ball grid array is formed on the bottom of the semiconductor package 3 .
  • the die attach pad 343 can be grounded according to the application requirement.
  • the support structure 36 serves as a test structure in the fabrication process.
  • connection pads 342 ′ are exposed from the openings 310 .
  • the dielectric layer 31 can be used to protect the traces. Therefore, the conventional solder mask layer is omitted in the present invention.
  • FIG. 3 F′′ only show a portion of the electrode pads 37 a and the traces 340 . Accordingly, some of the electrode pads 37 a are shown by “.”, and only some of the traces 340 are shown. Therefore, some of the connection pads 342 , 342 ′ are not shown to be connected to the traces 340 . In practice, the connection pads 342 , 342 ′ should be connected to the ends of the traces 340 .
  • the support structure 36 can be omitted. That is, the carrier 30 is completely removed in the process of FIG. 3E .
  • a soft dielectric layer 31 made of a material used for fabricating built-up layer structures is formed, and a conductive trace layer 34 made of copper or aluminum is formed on the dielectric layer 31 . Since the dielectric layer 31 has a good bonding with copper or aluminum, the present invention prevents delamination occurring around the peripheries of the openings 310 of the dielectric layer 31 , thereby avoiding solder ball drop failure and improving product reliability.
  • the dielectric layer 31 provides a strong support to the package structure to avoid solder ball drop failure.
  • the dielectric layer 31 further serves as an etching stop layer. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer in order to reduce fabrication cost.
  • the present invention dispenses with the conventional solder mask layer, thus reducing fabrication cost.
  • the conductive trace layer 34 is made of copper or aluminum, before forming the solder balls 39 , the present invention does not require performing the conventional electroless copper plating process, thereby greatly reducing fabrication cost.
  • the cost is reduced and the miniaturization of the semiconductor package 3 is facilitated.
  • FIGS. 4 and 5 are schematic cross-sectional views illustrating semiconductor packages 4 , 5 according to other embodiments of the present invention.
  • a semiconductor chip 37 ′ is electrically connected to bonding pads 341 ′ through a plurality of conductive bumps 370 ′. That is, the die attach pad of FIG. 3A is omitted.
  • an underfill 38 ′ is formed between the semiconductor chip 37 ′ and the first surface 31 a of the dielectric layer 31 to encapsulate the conductive bumps 370 ′.
  • the underfill 38 ′ can be omitted and the conductive bumps 370 ′ can be encapsulated by the encapuslant 38 .
  • only the underfill 38 ′ is formed between the semiconductor chip 37 ′ and the first surface 31 a of the dielectric layer 31 and the encapsulant 38 is omitted.
  • the bonding pads 341 ′ can be selectively connected to the connection pads 342 or 342 ′ through the traces 340 .
  • An UBM (Under Bump Metallurgy) (not shown) is formed on the electrode pads of the semiconductor chip 37 ′ (not shown) for being bonded with the conductive bumps 370 ′.
  • the electrode pads of the flip-chipped semiconductor chip can have any layout on demands, without specific limits.
  • the UBM also has a variety of structures, without specific limits.
  • the present invention further provides a semiconductor package 3 , 3 ′, 4 , 5 , which has: a dielectric layer 31 made of a material used for fabricating built-up layer structures, a conductive trace layer 34 and at least a semiconductor chip 37 , 37 ′.
  • the dielectric layer 31 has a first surface 31 a and a second surface 31 b that is opposite the first surface 31 a , and a plurality of openings 310 penetrating the first and second surfaces 31 a , 31 b .
  • the dielectric layer 31 can be made of one of the materials selected from polyimide, ABF, a glass epoxy composite material, a fiber reinforced glass composite material, or a glass ceramic and epoxy composite material.
  • the conductive trace layer 34 is formed on the first surface 31 a of the dielectric layer 31 and has a plurality of traces 340 which connect a plurality of bonding pads 341 , 341 ′ to a plurality of connection pads 342 , 342 ′.
  • the connection pads 342 , 342 ′ are exposed from the openings 310 of the dielectric layer 31 .
  • the conductive trace layer 34 is made of copper or aluminum.
  • the semiconductor chip 37 , 37 ′ is disposed on the first surface 31 a of the dielectric layer 31 or the bonding pads 341 ′.
  • the semiconductor chip 37 , 37 ′ has a plurality of electrode pads 37 a that are electrically connected to the bonding pads 341 , 341 ′ through a plurality of bonding wires 370 or conductive bumps 370 ′.
  • the semiconductor package 3 , 3 ′, 4 further has an encapsulant 38 formed over the first surface 31 a of the dielectric layer 31 to encapsulate the semiconductor chip 37 , 37 ′ and the conductive trace layer 34 .
  • the semiconductor package 3 , 3 ′, 4 , 5 further has a surface treated layer 35 formed on the bonding pads 341 .
  • the semiconductor package 3 , 3 ′, 4 , 5 further has a plurality of solder balls 39 formed on the connection pads 342 , 342 ′ at the openings 310 .
  • the semiconductor package 3 , 3 ′, 4 , 5 further has an adhesive 371 , 38 ′ formed between the dielectric layer 31 and the semiconductor chip 37 , 37 ′.
  • the conductive trace layer 34 further has a die attach pad 343 on which the semiconductor chip 37 is mounted.
  • the die attach pad 343 can serve as an electrical connection pad.
  • the bonding pads 341 are formed outside around the periphery of the semiconductor chip 37 .
  • the bonding pads 341 are formed between the connection pads 342 , 342 ′ and the semiconductor chip 37 .
  • a dielectric layer made of a material used for fabricating built-up layer structures is formed to serve as an etching stop layer and a solder mask layer so as for a conductive trace layer made of copper or aluminum to be formed thereon. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer and dispenses with the conventional solder mask layer and electroless plated copper layer, thereby reducing fabrication cost.
  • the present invention prevents delamination from occurring around the peripheries of the openings of the dielectric layer, thus improving product reliability.
  • the cost is reduced and the miniaturization of the semiconductor package is thus facilitated.

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Abstract

A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a carrier-free semiconductor package and a fabrication method thereof.
  • 2. Description of Related Art
  • Conventionally, there are various kinds of semiconductor packages that utilize lead frames as chip carriers. For example, a QFN (Quad Flat Non-leaded) semiconductor package is a lead frame based chip scale package, which is characterized by the fact that the leads thereof do not extend out from the package sides as in a conventional quad flat package (QFP), thereby reducing the overall package size. However, limited by the encapsulant thickness of the QFN package, the QFN package thickness cannot be further reduced to meet the demands for lighter, thinner, shorter and smaller semiconductor product trends. Therefore, carrier-free semiconductor packages have been developed to reduce the thickness of the overall package size by dispensing with a lead frame.
  • FIGS. 1A to 1D are schematic cross-sectional views illustrating a fabrication method of a semiconductor package 1 according to the prior art.
  • Referring to FIG. 1A, the surface of a metal carrier 10 is partially removed by etching to form a plurality of wire bonding pads 101 and at least a die attach pad 102.
  • Referring to FIG. 1B, a solder mask layer 11 such as green paint is formed on the metal carrier 10, and the wire bonding pads 101 and the die attach pad 102 covered by an anti-oxidation layer 15 are exposed from the solder mask layer 11.
  • Referring to FIG. 1C, a semiconductor chip 17 is disposed on the die attach pad 102 through an adhesive 171 and electrically connected to the wire bonding pads 101 through a plurality of bonding wires 170 such as gold wires. Then, an encapsulant 18 is formed on the solder mask layer 11 to encapsulate the semiconductor chip 17 and the bonding wires 170.
  • Referring to FIG. 1D, the metal carrier 10 is removed by etching to expose lower surfaces of the wire bonding pads 101 and the die attach pad 102.
  • However, referring to FIG. 1D′, since the bonding wires 170 often cross over each other, they may easily come into contact with each other, thereby resulting in a short circuit.
  • Further, there are special limitations on loop height and length of the bonding wires 170 and hence the layout of the wire bonding pads 101 is limited by the wire bonding range of the bonding wires 170.
  • Furthermore, referring to FIG. 1D′, the wire bonding pads 101 located outside around the periphery of the semiconductor chip 17 are distant from the electrode pads 17 a of the semiconductor chip 17, therefore longer bonding wires 170 are required, thereby increasing material cost and adversely affecting the miniaturization of the semiconductor package 1.
  • Accordingly, another fabrication method of a semiconductor package 2 has been developed, as shown in FIGS. 2A to 2E.
  • Referring to FIG. 2A, a conductive trace layer 24 is formed on a copper carrier 20 by electroplating. The conductive trace layer 24 has a plurality of bonding pads 241, a plurality of connection pads 242, and at least a die attach pad 243. The conductive trace layer 24 is made of Pd/Ni/Pd/Au.
  • Referring to FIG. 2B, at least a semiconductor chip 27 is disposed on the die attach pad 243 through an adhesive 271 such as silver epoxy, and electrically connected to the bonding pads 241 through a plurality of bonding wires 270.
  • Then, an encapsulant 28 is formed on the copper carrier 20 to encapsulate the semiconductor chip 27 and the conductive trace layer 24.
  • Referring to FIG. 2C, by using the gold material at the bottom of the conductive trace layer 24 as an etching stop layer, the copper carrier 20 is almost removed by etching.
  • Referring to FIG. 2D, an ultra-thin copper layer 25 is formed on the bonding pads 241, the connection pads 242, and the die attach pad 243. Then, a solder mask layer 21 such as green paint is formed on the encapsulant 28 and a plurality of openings 210 are formed in the solder mask layer 21 for exposing portions of the ultra-thin copper layer 25 on the connection pads 242 and the die attach pad 243.
  • Referring to FIG. 2E, by using the ultra-thin copper layer as a current conductive path, an electroplating process is performed to form a plurality of solder balls 29 on the ultra-thin copper layer 25 at the openings 210 of the solder mask layer 21.
  • In the above-described method, the conductive trace layer 24 is formed first and then the solder mask layer 21 is formed to cover a portion of the conductive trace layer 24. The solder mask layer 21 has a poor bonding with the gold material of the conductive trace layer 24 (the ultra-thin copper layer 25 has negligible effect on the bonding between the solder mask layer 21 and the conductive trace layer 24). Therefore, after the solder balls 29 are formed, delamination can easily occur around the peripheries of the openings of the solder mask layer 21, thus easily causing solder ball drop failure and consequently reducing package reliability.
  • Further, the gold material used in the conductive trace layer 24 results in a high fabrication cost.
  • Therefore, there is an urgent need to provide a semiconductor package and a fabrication method thereof to overcome the above-described disadvantages.
    • SUMMARY OF THE INVENTION
  • In view of the above-described disadvantages, the present invention provides a semiconductor package, which comprises: a dielectric layer used for fabricating built-up layer structures having opposite first and second surfaces, and a plurality of openings penetrating the first and second surfaces; a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer; at least a semiconductor chip attached to the first surface of the dielectric layer having a plurality of electrode pads; and a plurality of bonding wires electrically connecting the electrode pads of the semiconductor chip to the bonding pads.
  • In the above-described package, the conductive trace layer can further have a die attach pad on which the semiconductor chip is mounted, and the semiconductor chip is electrically connected to the die attach pad.
  • In the above-described package, the bonding pads can be formed outside the periphery of the semiconductor chip.
  • In the above-described package, the bonding pads can be formed between the connection pads and the semiconductor chip.
  • The present invention provides another semiconductor package, which comprises: a dielectric layer used for fabricating built-up layer structures having opposite first and second surfaces, and a plurality of openings penetrating the first and second surfaces; a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer; a plurality of conductive bumps formed on the respective bonding pads; and at least a semiconductor chip disposed on the conductive bumps, wherein the semiconductor chip has a plurality of electrode pads electrically connected to the bonding pads through the conductive bumps.
  • The present invention further provides a fabrication method of a semiconductor package, which comprises the steps of: providing a carrier having a dielectric layer formed on a surface thereof, wherein the dielectric layer is used for fabricating built-up layer structures; forming a conductive trace layer on the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad; attaching at least a semiconductor chip to the dielectric layer and electrically connecting the bonding pads to the semiconductor chip; forming an encapsulant over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer; removing the carrier while retaining the dielectric layer on the encapsulant; and forming a plurality of openings, through which the connection pads are exposed, penetrating the dielectric layer.
  • In the above-described method, the carrier can be made of metal.
  • In the above-described method, the conductive trace layer can be formed by electroplating.
  • In the above-described method, the semiconductor chip can be electrically connected to the bonding pads through bonding wires or conductive bumps.
  • In the above-described method, the conductive trace layer can further have a die attach pad on which the semiconductor chip is mounted.
  • In the above-described method, the carrier can be removed by etching.
  • In the above-described packages and method, the dielectric layer can be made of a material selected from the groups consisting of polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, and a glass ceramic and epoxy composite material.
  • In the above-described packages and method, a surface treated layer can further be formed on the bonding pads.
  • In the above-described packages and method, an adhesive can further be formed between the dielectric layer and the semiconductor chip.
  • In the above-described packages and method, an encapsulant can further be formed over the first surface of the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer.
  • In the above-described packages and method, a plurality of solder balls can further be formed at the openings of the dielectric layer, respectively.
  • According to the present invention, a dielectric layer made of a material used for fabricating built-up layer structures is formed to serve as an etching stop layer and a solder mask layer so as for a conductive trace layer made of copper or aluminum to be formed thereon. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer and dispenses with the conventional solder mask layer and electroless plated copper layer, thereby reducing fabrication cost.
  • Further, since a strong bonding is formed between the dielectric layer and copper or aluminum, the present invention prevents the delamination occurring around the peripheries of the openings of the dielectric layer, thus avoiding solder ball drop failure and improving product reliability.
  • In addition, the dielectric layer provides a strong support to the package structure so as to avoid solder ball drop failure.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIGS. 1A to 1D are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the prior art, wherein FIG. 1D′ is a schematic upper view of part of the semiconductor package and FIG. 1D is a schematic cross-sectional view along a sectional line A-A of FIG. 1D′;
  • FIGS. 2A to 2E are schematic cross-sectional views illustrating another fabrication method of a semiconductor package according to the prior art;
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the present invention, wherein FIG. 3F′ shows another embodiment of FIG. 3F, and FIG. 3F″ is a schematic upper view of FIG. 3F′ without the encapsulant;
  • FIG. 4 is a schematic cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention; and
  • FIG. 5 is a schematic cross-sectional view illustrating another embodiment of FIG. 4.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The following embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
  • It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “upper”, “lower”, “a” etc. are merely for illustrative purpose and should not be construed to limit the scope of the present invention.
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating a fabrication method of a semiconductor package according to the present invention.
  • Referring to FIG. 3A, a carrying structure 3 a is provided, which has a carrier 30, a dielectric layer 31 used for fabricating built-up layer structures, and a conductive layer 32. Further, a first patterned resist layer 33 a is formed on the conductive layer 32 for exposing portions of the conductive layer 32.
  • In the present embodiment, the dielectric layer 31 can be made of one of the materials selected from polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, or a glass ceramic and epoxy composite material. Compared with the conventional prepreg material, the dielectric material of the present invention facilitates to alleviate the CTE mismatch between the encapsulant and the dielectric material and resist cracking while being pressed during a subsequent molding process.
  • Then, by using the conductive layer 32 as a current conductive path, an electroplating process is performed to form a conductive trace layer 34 on the dielectric layer 31. The conductive trace layer 34 has a plurality of traces 340 (as shown in FIG. 3F″), a plurality of bonding pads 341 and connection pads 342 connected through the traces 340, and at least a die attach pad 343. In the present embodiment, the die attach pad 343 is used for a semiconductor chip to be mounted thereon and not connected to the traces 340. In other embodiments, the die attach pad 343 can be electrically grounded and connected to the connection pads 342, 342′ through the traces 340.
  • In the present embodiment, the carrier 30 and the conductive layer 32 are substantially made of metal such as copper or aluminum. The conductive layer 32 serves as a current conductive path for electroplating. The conductive trace layer 34 is substantially made of copper or aluminum.
  • The carrier 30, the dielectric layer 31 and the conductive layer 32 form a carrying structure 3 a.
  • The bonding pads 341 serve as wire bonding pads and are formed outside the periphery of the die attach pad 343 and located between the die attach pad 343 and the connection pads 342, 342′.
  • The dielectric layer 31 has an upper surface, i.e., a first surface 31 a and a lower surface, i.e., a second surface 31 b that is opposite to the first surface 31 a. The dielectric layer 31 a is bonded to the conductive layer 32 through the first surface 31 a and bonded to the carrier 30 through the second surface 31 b.
  • Referring to FIG. 3B, a second patterned resist layer 33 b is formed on the first patterned resist layer 33 a and the bonding pads 341 are exposed from the second patterned resist layer 33 b. Then, a surface treated layer 35 is formed on the bonding pads 341.
  • Meanwhile, a third patterned resist layer 33 c is formed on the lower side of the carrier 30 such that a support layer 36 a is formed on the carrier 30.
  • In the present embodiment, the support layer 36 a and the surface treated layer 35 are made of same materials, such as electroless nickel/gold, ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold), DIG (Direct Immersion Gold) or electroplated nickel/electroless palladium/electroplated gold.
  • Referring to FIG. 3C, the first, second and third patterned resist layers 33 a, 33 b and 33 c and the conductive layer 32 under the first patterned resist layer 33 a are removed.
  • Referring to FIG. 3D, a semiconductor chip 37 is disposed on the die attach pad 343 through an adhesive 371 such as a silver epoxy and electrically connected to the bonding pads 341 through a plurality of bonding wires 370.
  • Then, an encapsulant 38 is formed over the dielectric layer 31 to encapsulate the semiconductor chip 37 and the conductive trace layer 34.
  • In the present embodiment, referring to FIG. 3F″, the semiconductor chip 37 has a plurality of electrode pads 37 a that are electrically connected to the bonding pads 341 through the bonding wires 370.
  • The bonding pads 341 are formed outside around the periphery of the semiconductor chip 37 and located between the semiconductor chip 37 and the connection pads 342, 342′.
  • In another embodiment, the bonding pads 341 can be formed between the connection pads 342, 342′.
  • In another embodiment, the die attach pad 343 can be omitted and the semiconductor chip 37 can be directly disposed on the first surface 31 a of the dielectric layer 31.
  • Referring to FIG. 3F″, since the bonding wires 370 are not directly connected to the connection pads 342, 342′, the present invention overcomes the conventional disadvantage of bonding wire crossing, thus preventing short circuits in the package.
  • Through the configuration of the traces 340, the layout of the bonding pads 341 becomes more flexible and that of the connection pads 342, 342′ is, therefore, not limited by the wire bonding range of the bonding wires 370.
  • Further, the present invention shortens the distance between the bonding pads 341 and the electrode pads 37 a (including I/O contact pads) of the semiconductor chip 37, thereby shortening the length of the bonding wires 370 and consequently reducing the cost and facilitating the miniaturization of the semiconductor package 3.
  • Furthermore, referring to FIG. 3F″, the total number of the connection pads 342, 342′ of the conductive trace layer 34 can be greater than or equal to the number of the electrode pads 37 a (including I/O contact pads) of the semiconductor chip 37.
  • Referring to FIG. 3E, a portion of the carrier 30 that is exposed from the support layer 36 a is removed by etching while the dielectric layer 31 remains on the encapsulant 38, thereby forming a support structure 36 on the second surface 31 b of the dielectric layer 31.
  • Referring to FIG. 3F, a plurality of openings 310 are formed on the second surface 31 b of the dielectric layer 31 to expose the connection pads 342, 342′ and the die attach pad 343, and a plurality of solder balls 39 are formed on the connection pads 342, 342′ and the die attach pad 343 at the openings 310 of the dielectric layer 31. As such, a ball grid array is formed on the bottom of the semiconductor package 3. The die attach pad 343 can be grounded according to the application requirement.
  • In the present embodiment, the support structure 36 serves as a test structure in the fabrication process.
  • In another embodiment, the outermost connection pads 342′ are exposed from the openings 310.
  • The dielectric layer 31 can be used to protect the traces. Therefore, the conventional solder mask layer is omitted in the present invention.
  • For purposes of simplification, FIG. 3F″ only show a portion of the electrode pads 37 a and the traces 340. Accordingly, some of the electrode pads 37 a are shown by “.”, and only some of the traces 340 are shown. Therefore, some of the connection pads 342, 342′ are not shown to be connected to the traces 340. In practice, the connection pads 342, 342′ should be connected to the ends of the traces 340.
  • In another embodiment, referring to FIG. 3F′, the support structure 36 can be omitted. That is, the carrier 30 is completely removed in the process of FIG. 3E.
  • According to the present invention, a soft dielectric layer 31 made of a material used for fabricating built-up layer structures is formed, and a conductive trace layer 34 made of copper or aluminum is formed on the dielectric layer 31. Since the dielectric layer 31 has a good bonding with copper or aluminum, the present invention prevents delamination occurring around the peripheries of the openings 310 of the dielectric layer 31, thereby avoiding solder ball drop failure and improving product reliability.
  • Further, the dielectric layer 31 provides a strong support to the package structure to avoid solder ball drop failure. The dielectric layer 31 further serves as an etching stop layer. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer in order to reduce fabrication cost.
  • Furthermore, by using the dielectric layer 31 as a solder mask layer after removing the carrier 30, the present invention dispenses with the conventional solder mask layer, thus reducing fabrication cost. In addition, since the conductive trace layer 34 is made of copper or aluminum, before forming the solder balls 39, the present invention does not require performing the conventional electroless copper plating process, thereby greatly reducing fabrication cost.
  • Moreover, by replacing the conventional long bonding wires with the conductive trace layer 34 made of copper or aluminum, the cost is reduced and the miniaturization of the semiconductor package 3 is facilitated.
  • FIGS. 4 and 5 are schematic cross-sectional views illustrating semiconductor packages 4, 5 according to other embodiments of the present invention. Referring to FIG. 4, a semiconductor chip 37′ is electrically connected to bonding pads 341′ through a plurality of conductive bumps 370′. That is, the die attach pad of FIG. 3A is omitted. Then, an underfill 38′ is formed between the semiconductor chip 37′ and the first surface 31 a of the dielectric layer 31 to encapsulate the conductive bumps 370′. In another embodiment, the underfill 38′ can be omitted and the conductive bumps 370′ can be encapsulated by the encapuslant 38. In another embodiment, referring to FIG. 5, only the underfill 38′ is formed between the semiconductor chip 37′ and the first surface 31 a of the dielectric layer 31 and the encapsulant 38 is omitted.
  • In the present embodiment, the bonding pads 341′ can be selectively connected to the connection pads 342 or 342′ through the traces 340.
  • An UBM (Under Bump Metallurgy) (not shown) is formed on the electrode pads of the semiconductor chip 37′ (not shown) for being bonded with the conductive bumps 370′. The electrode pads of the flip-chipped semiconductor chip can have any layout on demands, without specific limits. The UBM also has a variety of structures, without specific limits.
  • The present invention further provides a semiconductor package 3, 3′, 4, 5, which has: a dielectric layer 31 made of a material used for fabricating built-up layer structures, a conductive trace layer 34 and at least a semiconductor chip 37, 37′.
  • The dielectric layer 31 has a first surface 31 a and a second surface 31 b that is opposite the first surface 31 a, and a plurality of openings 310 penetrating the first and second surfaces 31 a, 31 b. The dielectric layer 31 can be made of one of the materials selected from polyimide, ABF, a glass epoxy composite material, a fiber reinforced glass composite material, or a glass ceramic and epoxy composite material.
  • The conductive trace layer 34 is formed on the first surface 31 a of the dielectric layer 31 and has a plurality of traces 340 which connect a plurality of bonding pads 341, 341′ to a plurality of connection pads 342, 342′. The connection pads 342, 342′ are exposed from the openings 310 of the dielectric layer 31. The conductive trace layer 34 is made of copper or aluminum.
  • The semiconductor chip 37, 37′ is disposed on the first surface 31 a of the dielectric layer 31 or the bonding pads 341′. The semiconductor chip 37, 37′ has a plurality of electrode pads 37 a that are electrically connected to the bonding pads 341, 341′ through a plurality of bonding wires 370 or conductive bumps 370′.
  • The semiconductor package 3, 3′, 4 further has an encapsulant 38 formed over the first surface 31 a of the dielectric layer 31 to encapsulate the semiconductor chip 37, 37′ and the conductive trace layer 34.
  • The semiconductor package 3, 3′, 4, 5 further has a surface treated layer 35 formed on the bonding pads 341.
  • The semiconductor package 3, 3′, 4, 5 further has a plurality of solder balls 39 formed on the connection pads 342, 342′ at the openings 310.
  • The semiconductor package 3, 3′, 4, 5 further has an adhesive 371, 38′ formed between the dielectric layer 31 and the semiconductor chip 37, 37′.
  • In an embodiment, the conductive trace layer 34 further has a die attach pad 343 on which the semiconductor chip 37 is mounted. The die attach pad 343 can serve as an electrical connection pad.
  • In an embodiment, the bonding pads 341 are formed outside around the periphery of the semiconductor chip 37.
  • In an embodiment, the bonding pads 341 are formed between the connection pads 342, 342′ and the semiconductor chip 37.
  • According to the present invention, a dielectric layer made of a material used for fabricating built-up layer structures is formed to serve as an etching stop layer and a solder mask layer so as for a conductive trace layer made of copper or aluminum to be formed thereon. Therefore, the present invention eliminates the need of a gold material used in forming the conductive trace layer and dispenses with the conventional solder mask layer and electroless plated copper layer, thereby reducing fabrication cost.
  • Further, since a strong bonding is formed between the dielectric layer and copper or aluminum, the present invention prevents delamination from occurring around the peripheries of the openings of the dielectric layer, thus improving product reliability.
  • In addition, by replacing the conventional long bonding wires (most are gold wires) with the conductive trace layer made of copper or aluminum, the cost is reduced and the miniaturization of the semiconductor package is thus facilitated.
  • The above descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims

Claims (27)

What is claimed is:
1. A semiconductor package, comprising:
a dielectric layer used for fabricating built-up layer structures and having opposite first and second surfaces and a plurality of openings penetrating the first and second surfaces;
a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer;
at least a semiconductor chip attached to the first surface of the dielectric layer having a plurality of electrode pads; and
a plurality of bonding wires electrically connecting the electrode pads of the semiconductor chip to the bonding pads of the conductive trace layer.
2. The semiconductor package of claim 1, wherein the dielectric layer is made of a material selected from the group consisting of polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, and a glass ceramic and epoxy composite material.
3. The semiconductor package of claim 1, further comprising a surface treated layer formed on the bonding pads.
4. The semiconductor package of claim 1, further comprising a plurality of solder balls formed at the openings of the dielectric layer.
5. The semiconductor package of claim 1, further comprising an adhesive formed between the dielectric layer and the semiconductor chip.
6. The semiconductor package of claim 1, further comprising an encapsulant formed over the first surface of the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer.
7. The semiconductor package of claim 1, wherein the conductive trace layer further has a die attach pad on which the semiconductor chip is mounted.
8. The semiconductor package of claim 7, wherein the semiconductor chip is electrically connected to the die attach pad.
9. The semiconductor package of claim 1, wherein the bonding pads are formed outside peripheries of the semiconductor chip.
10. The semiconductor package of claim 1, wherein the bonding pads are formed between the connection pads and the semiconductor chip.
11. A semiconductor package, comprising:
a dielectric layer used for fabricating built-up layer structures and having opposite first and second surfaces and a plurality of openings penetrating the first and second surfaces;
a conductive trace layer formed on the first surface of the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad, and the connection pads are exposed through the openings of the dielectric layer;
a plurality of conductive bumps formed on the respective bonding pads; and
at least a semiconductor chip disposed on the conductive bumps, wherein the semiconductor chip has a plurality of electrode pads electrically connected to the bonding pads through the conductive bumps.
12. The semiconductor package of claim 11, wherein the dielectric layer is made of a material selected from the group consisting of polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, and a glass ceramic and epoxy composite material.
13. The semiconductor package of claim 11, further comprising a surface treated layer formed on the bonding pads.
14. The semiconductor package of claim 11, further comprising a plurality of solder balls formed at the openings of the dielectric layer.
15. The semiconductor package of claim 11, further comprising an adhesive formed between the dielectric layer and the semiconductor chip.
16. The semiconductor package of claim 11, further comprising an encapsulant formed over the first surface of the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer.
17. A fabrication method of a semiconductor package, comprising the steps of:
providing a carrier having a dielectric layer formed on a surface thereof, wherein the dielectric layer used for fabricating built-up layer structures;
forming a conductive trace layer on the dielectric layer, wherein the conductive trace layer has a plurality of traces, each of the traces electrically connects a bonding pad and a connection pad;
attaching at least a semiconductor chip to the dielectric layer and electrically connecting the semiconductor chip to the bonding pads;
forming an encapsulant over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer;
removing the carrier while retaining the dielectric layer on the encapsulant; and
forming a plurality of openings, through which the connection pads are exposed, penetrating the dielectric layer.
18. The fabrication method of claim 17, wherein the carrier is made of metal.
19. The fabrication method of claim 17, wherein the dielectric layer is made of a material selected from the group consisting of polyimide, ABF (Ajinomoto Build-up Film), a glass epoxy composite material, a fiber reinforced glass composite material, and a glass ceramic and epoxy composite material.
20. The fabrication method of claim 17, wherein the conductive trace layer is formed by electroplating.
21. The fabrication method of claim 17, wherein the conductive trace layer further has a die attach pad on which the semiconductor chip is mounted.
22. The fabrication method of claim 17, wherein the semiconductor chip is electrically connected to the bonding pads through bonding wires or conductive bumps.
23. The fabrication method of claim 17, wherein the carrier is removed by etching.
24. The fabrication method of claim 17, further comprising forming a surface treated layer on the bonding pads.
25. The fabrication method of claim 17, further comprising forming a plurality of solder balls at the openings of the dielectric layer.
26. The fabrication method of claim 17, further comprising forming an adhesive between the dielectric layer and the semiconductor chip.
27. The fabrication method of claim 17, further comprising forming an encapsulant over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061160A1 (en) * 2013-08-28 2015-03-05 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
US20170352638A1 (en) * 2016-03-01 2017-12-07 Infineon Technologies Ag Semiconductor device including antistatic die attach material

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI563577B (en) * 2014-10-09 2016-12-21 Phoenix Pioneer Technology Co Ltd Package structure and method of manufacture
TWI558286B (en) * 2014-10-28 2016-11-11 恆勁科技股份有限公司 Package structure and method of fabricating the same
TWI559470B (en) * 2015-08-06 2016-11-21 力成科技股份有限公司 Non-substrate semiconductor package structure and manufacturing method thereof
TWI622151B (en) * 2016-12-07 2018-04-21 矽品精密工業股份有限公司 Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package
CN108242403A (en) * 2016-12-27 2018-07-03 冠宝科技股份有限公司 A kind of no substrate semiconductor encapsulation making method
TWI690039B (en) * 2019-07-03 2020-04-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI760726B (en) * 2020-04-14 2022-04-11 矽品精密工業股份有限公司 Electronic package, manufacturing method thereof and conductive structure

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US20010014538A1 (en) * 1998-06-10 2001-08-16 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US20010052647A1 (en) * 1998-05-07 2001-12-20 3M Innovative Properties Company Laminated integrated circuit package
US20030179549A1 (en) * 2002-03-22 2003-09-25 Zhong Chong Hua Low voltage drop and high thermal perfor mance ball grid array package
US20040106229A1 (en) * 2002-06-27 2004-06-03 Tongbi Jiang Methods for assembling multiple semiconductor devices
US20050051890A1 (en) * 2001-05-07 2005-03-10 Broadcom Corporation Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method for making the same
US6882042B2 (en) * 2000-12-01 2005-04-19 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US20060163749A1 (en) * 2005-01-25 2006-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US20060180914A1 (en) * 2005-02-14 2006-08-17 Stats Chippac Ltd. Stacked die package system
US20090146298A1 (en) * 2007-12-07 2009-06-11 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US20110156227A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Semiconductor package structure
US20120049363A1 (en) * 2010-09-01 2012-03-01 Unimicron Technology Corporation Package structure
US20130249068A1 (en) * 2012-03-20 2013-09-26 Byung Tai Do Integrated circuit packaging system with external interconnect and method of manufacture thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283473B (en) * 2002-11-08 2007-07-01 Advanced Semiconductor Eng Stack package structure and electrically-connected board for stack package
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US20110159543A1 (en) 2008-07-15 2011-06-30 Maartje Verschuur Scalable process for culturing per.c6 cells and producing products therefrom
JP2010093109A (en) * 2008-10-09 2010-04-22 Renesas Technology Corp Semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor module
TWI469310B (en) * 2009-03-17 2015-01-11 Powertech Technology Inc Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure
KR101711499B1 (en) * 2010-10-20 2017-03-13 삼성전자주식회사 Semiconductor package and method of forming the same
TW201231860A (en) * 2011-01-18 2012-08-01 Gio Optoelectronics Corp Light emitting apparatus
US9275877B2 (en) * 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US20010052647A1 (en) * 1998-05-07 2001-12-20 3M Innovative Properties Company Laminated integrated circuit package
US20010014538A1 (en) * 1998-06-10 2001-08-16 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6882042B2 (en) * 2000-12-01 2005-04-19 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US20050051890A1 (en) * 2001-05-07 2005-03-10 Broadcom Corporation Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method for making the same
US20030179549A1 (en) * 2002-03-22 2003-09-25 Zhong Chong Hua Low voltage drop and high thermal perfor mance ball grid array package
US20040106229A1 (en) * 2002-06-27 2004-06-03 Tongbi Jiang Methods for assembling multiple semiconductor devices
US20060163749A1 (en) * 2005-01-25 2006-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US20060180914A1 (en) * 2005-02-14 2006-08-17 Stats Chippac Ltd. Stacked die package system
US20090146298A1 (en) * 2007-12-07 2009-06-11 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US20110156227A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Semiconductor package structure
US20110159643A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
US20120049363A1 (en) * 2010-09-01 2012-03-01 Unimicron Technology Corporation Package structure
US20130249068A1 (en) * 2012-03-20 2013-09-26 Byung Tai Do Integrated circuit packaging system with external interconnect and method of manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061160A1 (en) * 2013-08-28 2015-03-05 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
US9209153B2 (en) * 2013-08-28 2015-12-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
US20170352638A1 (en) * 2016-03-01 2017-12-07 Infineon Technologies Ag Semiconductor device including antistatic die attach material
US10304795B2 (en) * 2016-03-01 2019-05-28 Infineon Technologies Ag Semiconductor device including antistatic die attach material

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TWI480989B (en) 2015-04-11
US20170294372A1 (en) 2017-10-12

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