KR100394775B1 - 와이어본딩 방법 및 이를 이용한 반도체패키지 - Google Patents
와이어본딩 방법 및 이를 이용한 반도체패키지 Download PDFInfo
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- KR100394775B1 KR100394775B1 KR10-2000-0076328A KR20000076328A KR100394775B1 KR 100394775 B1 KR100394775 B1 KR 100394775B1 KR 20000076328 A KR20000076328 A KR 20000076328A KR 100394775 B1 KR100394775 B1 KR 100394775B1
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- Prior art keywords
- semiconductor chip
- input
- wire
- circuit
- circuit pattern
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000465 moulding Methods 0.000 description 7
- 238000010408 sweeping Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (4)
- 회로기판의 중앙부에 각각 다수의 입출력 패드가 구비된 제 1 반도체 칩과 제 2 반도체칩이 차례로 수직방향으로 적층형성되고, 상기 반도체 칩 외주연에 다수의 회로 패턴이 형성되어 상기 제 1 반도체 칩과 제 2 반도체 칩의 입출력 패드와 상기 회로패턴을 도전성 와이어로 본딩하여 상호 신호 교환이 이루어지도록 도전성와이어로 본딩하는 방법에 있어서,상기 하부쪽의 제 1 반도체 칩의 입출력패드와 회로 패턴을 접속하는 바텀 와이어가 상부쪽의 제 2 반도체 칩의 입출력 패드와 회로 패턴을 접속하는 탑 와이어 보다 두께가 얇게 형성시키는 것을 특징으로 하는 와이어 본딩 방법.
- (삭제)
- 수직 방향으로 차례로 적층형성되는 각각 다수의 입출력 패드가 구비된 제 1 반도체 칩과 제 2 반도체칩과;상기 제 1반도체 칩의 저면에 접착수단으로 접착되어 있되, 수지층을 중심으로 상기 적층형성된 제 1 반도체칩 및 제 2 반도체 칩의 외주연에 다수의 회로패턴이 형성됨과 동시에, 상기 제 1 반도체칩 및 제 2 반도체 칩의 외주연에 다수의 회로패턴이 형성되어 있으며, 상기 수지층의 상면 또는 저면에는 상기 회로패턴과 연결된 다수의 볼랜드를 포함하여 이루어진 회로기판과;상기 제1반도체칩의 입출력패드와 상기 전달 패턴을 전기적으로 접속시키는 바텀 와이어 및 상기 제2반도체칩의 입출력패드와 상기 전달패턴을 전기적으로 접속시키는 탑 와이어와;상기 제1반도체칩, 제2반도체칩, 도전성와이어 등을 외부환경으로부터 보호하기 위해 감싸는 봉지재와;상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어되, 상기 하부쪽의 제 1 반도체 칩의 입출력패드와 회로 패턴을 접속하는 바텀 와이어가 상부쪽의 제 2 반도체 칩의 입출력 패드와 회로 패턴을 접속하는 탑 와이어 보다 두께가 얇게 형성시키는 것을 특징으로 반도체 패키지.
- (삭제)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2000-0076328A KR100394775B1 (ko) | 2000-12-14 | 2000-12-14 | 와이어본딩 방법 및 이를 이용한 반도체패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2000-0076328A KR100394775B1 (ko) | 2000-12-14 | 2000-12-14 | 와이어본딩 방법 및 이를 이용한 반도체패키지 |
Publications (2)
Publication Number | Publication Date |
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KR20020047746A KR20020047746A (ko) | 2002-06-22 |
KR100394775B1 true KR100394775B1 (ko) | 2003-08-19 |
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KR10-2000-0076328A KR100394775B1 (ko) | 2000-12-14 | 2000-12-14 | 와이어본딩 방법 및 이를 이용한 반도체패키지 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100871709B1 (ko) | 2007-04-10 | 2008-12-08 | 삼성전자주식회사 | 칩 스택 패키지 및 그 제조방법 |
CN108878408A (zh) * | 2017-05-10 | 2018-11-23 | 叶秀慧 | 薄型化双芯片的叠接封装结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04221837A (ja) * | 1990-12-21 | 1992-08-12 | Mitsubishi Electric Corp | 半導体装置 |
KR930011182A (ko) * | 1991-11-13 | 1993-06-23 | 김광호 | 반도체 장치 및 그 제조방법 |
JPH0697218A (ja) * | 1992-09-14 | 1994-04-08 | Hitachi Ltd | 半導体装置 |
JPH10135399A (ja) * | 1996-10-31 | 1998-05-22 | Hitachi Ltd | 半導体装置およびその製造方法並びにそれに使用されるリードフレーム |
-
2000
- 2000-12-14 KR KR10-2000-0076328A patent/KR100394775B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04221837A (ja) * | 1990-12-21 | 1992-08-12 | Mitsubishi Electric Corp | 半導体装置 |
KR930011182A (ko) * | 1991-11-13 | 1993-06-23 | 김광호 | 반도체 장치 및 그 제조방법 |
JPH0697218A (ja) * | 1992-09-14 | 1994-04-08 | Hitachi Ltd | 半導体装置 |
JPH10135399A (ja) * | 1996-10-31 | 1998-05-22 | Hitachi Ltd | 半導体装置およびその製造方法並びにそれに使用されるリードフレーム |
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