JPH04221837A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH04221837A
JPH04221837A JP2413389A JP41338990A JPH04221837A JP H04221837 A JPH04221837 A JP H04221837A JP 2413389 A JP2413389 A JP 2413389A JP 41338990 A JP41338990 A JP 41338990A JP H04221837 A JPH04221837 A JP H04221837A
Authority
JP
Japan
Prior art keywords
pads
package
semiconductor device
semiconductor chip
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2413389A
Other languages
English (en)
Inventor
Koichi Kaneko
金子 公一
Akira Yamada
朗 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2413389A priority Critical patent/JPH04221837A/ja
Publication of JPH04221837A publication Critical patent/JPH04221837A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49431Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】この発明は、多ピン化されたパッ
ケージと半導体チップとのワイヤボンディングを要する
半導体装置に関するものである。
【0002】
【従来の技術】図2は従来の一般的な多ピン化されたパ
ッケージと半導体チップとのワイヤボンディングを有す
る半導体装置を示す図であり、図において、1はパッケ
ージ、2はパッケージ1の上段端子、3はパッケージ1
の下段端子、4は半導体チップ、5は半導体チップ4内
のパッド、6はパッケージ1の上段端子2及び下段端子
3と、半導体チップ4内のパッド5とを接続するワイヤ
を示す。
【0003】次に動作について説明する。同図では半導
体チップ4内のパッド5が1列に等間隔で配置されてお
り、パッケージ1の上段端子2及び下段端子3と、半導
体チップ4内のパッド5に対して、ワイヤ6を使用して
順次ワイヤボンディングを行っていく。
【0004】
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、パッケージの上段端子
及び下段端子と、半導体チップ内のパッドに対してワイ
ヤボンディングを行う際、半導体チップ内の隣接するパ
ッド周辺においてワイヤが交差しやすく、組立不良とな
る可能性が高いという問題点があった。
【0005】この発明は上記のような問題点を解消する
ためになされたもので、ワイヤ交差による組立不良のな
い半導体装置を提供することを目的とする。
【0006】
【課題を解決するための手段】この発明に係る半導体装
置は、半導体チップのパッドの配置を交互2列にしてワ
イヤが交差しないようにすると同時に、ワイヤ長の長い
ワイヤを用いて、パッケージの上段端子と半導体チップ
の内側パッドとのワイヤボンディングを半導体装置への
入力信号について行い、ワイヤ長の短いワイヤを用いて
、パッケージの下段端子と半導体チップの外側パッドと
のワイヤボンディングを半導体装置の出力信号について
行ったものである。
【0007】
【作用】この発明においては、半導体チップのパッドの
配置を交互2列にし、ワイヤ長の長いワイヤを用いて、
パッケージの上段端子と半導体チップの内側パッドとの
ワイヤボンディングを半導体装置への入力信号について
行い、ワイヤ長の短いワイヤを用いて、パッケージの下
段端子と半導体チップの外側パッドとのワイヤボンディ
ングを半導体装置の出力信号について行ったので、ワイ
ヤ同士の交差を防止すると共に、パッドの配置を交互2
列にしたことによるワイヤ長増大が原因のノイズの影響
から生ずる半導体装置の誤動作及び性能低下が抑止され
る。
【0008】
【実施例】図1は、この発明の一実施例による半導体チ
ップのパッドの配置を交互2列にした場合のワイヤボン
ディングを有する半導体装置を示す。図において、図2
と同一符号は同一部分を示し、5aは半導体チップ4内
の内側パッド、5bは半導体チップ4内の外側パッド、
6aは内側パッド5aと上段端子2とを接続するワイヤ
、6bは外側パッド5bと下段端子3とを接続するワイ
ヤである。
【0009】次に動作について説明する。同図では、半
導体チップ4内において、内側パッド5aと外側パッド
5bが交互2列に配置されており、内側パッド5aには
半導体装置への入力信号を割り当て、外側パッド5bに
は半導体装置の出力信号を割り当てている。そして、パ
ッケージ1の上段端子2と内側パッド5aとをワイヤ長
の長いワイヤ6aによって接続し、パッケージ1の下段
端子3と外側パッド5bとをワイヤ長の短いワイヤ6b
によって接続する。これはワイヤ長が長いとノイズの原
因となるインダクタンスが大きくなるため、半導体装置
の動作および性能に影響を与える出力信号に対してはイ
ンダクタンスの小さい、ワイヤ長が短いワイヤ6bを使
用したものである。
【0010】なお上記実施例では、パッケージの端子が
2段構成及び半導体チップ内のパッドが交互2列に配置
されている場合について説明したが、パッケージの端子
の構成が2段以上又は半導体チップ内のパッドの配置が
2列以上である場合についても上記のワイヤボンディン
グ方法を施せばよく、この場合も同様の効果を奏する。
【0011】
【発明の効果】以上のようにこの発明によれば、半導体
チップのパッドの配置を交互2列にし、ワイヤ長の長い
ワイヤを用いて、パッケージの上段端子と半導体チップ
の内側パッドとのワイヤボンディングを半導体装置への
入力信号について行い、ワイヤ長の短いワイヤを用いて
、パッケージの下段端子と半導体チップの外側パッドと
のワイヤボンディングを半導体装置の出力信号について
行うことにより、ワイヤの交差を防止すると共に、パッ
ドの配置を交互2列にしたことで増大したワイヤ長が原
因となって生じるノイズの影響による半導体装置の誤動
作及び性能低下を抑止できる効果がある。
【図面の簡単な説明】
【図1】この発明の一実施例による半導体チップのパッ
ドの配置を交互2列にした場合のワイヤボンディングを
有する半導体装置を示す構成図である。
【図2】従来の半導体チップのパッドが1列で等間隔に
配置されている場合のワイヤボンディングを有する半導
体装置を示す構成図である。
【符号の説明】
1    パッケージ 2    パッケージの上段端子 3    パッケージの下段端子 4    半導体チップ 5a  半導体チップ内の内側パッド 5b  半導体チップ内の外側パッド 6a  内側パッドと上段端子とを接続するワイヤ長の
長いワイヤ 6b  外側パッドと下段端子とを接続するワイヤ長の
短いワイヤ

Claims (1)

    【特許請求の範囲】
  1. 【請求項1】  パッケージ側の端子が2段以上の構成
    である半導体装置において、該パッケージに搭載する半
    導体チップのパッドを交互2列以上に配置し、ワイヤ長
    の長いワイヤを用いて、前記パッケージの上段端子と前
    記半導体チップの内側パッドとのワイヤボンディングを
    半導体装置への入力信号について行い、ワイヤ長の短い
    ワイヤを用いて、前記パッケージの下段端子と前記半導
    体チップの外側パッドとのワイヤボンディングを半導体
    装置の出力信号について行ったことを特徴とする半導体
    装置。
JP2413389A 1990-12-21 1990-12-21 半導体装置 Pending JPH04221837A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2413389A JPH04221837A (ja) 1990-12-21 1990-12-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2413389A JPH04221837A (ja) 1990-12-21 1990-12-21 半導体装置

Publications (1)

Publication Number Publication Date
JPH04221837A true JPH04221837A (ja) 1992-08-12

Family

ID=18522045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2413389A Pending JPH04221837A (ja) 1990-12-21 1990-12-21 半導体装置

Country Status (1)

Country Link
JP (1) JPH04221837A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745656A (ja) * 1993-07-26 1995-02-14 Nec Corp 半導体装置
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
EP0902471A3 (en) * 1997-09-12 1999-11-03 Oki Electric Industry Company, Limited Semiconductor integrated circuit device and package structure for the same
EP0971411A2 (en) * 1998-07-06 2000-01-12 Hitachi, Ltd. Semiconductor device
US6025650A (en) * 1994-08-24 2000-02-15 Fujitsu Limited Semiconductor device including a frame terminal
EP1028428A1 (en) * 1999-02-12 2000-08-16 STMicroelectronics Limited Conductor structure
WO2003023843A1 (fr) * 2001-09-05 2003-03-20 Renesas Thechnology Corp. Dispositif a semi-conducteur, son procede de fabrication et dispositif de communication radio
KR100394775B1 (ko) * 2000-12-14 2003-08-19 앰코 테크놀로지 코리아 주식회사 와이어본딩 방법 및 이를 이용한 반도체패키지
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745656A (ja) * 1993-07-26 1995-02-14 Nec Corp 半導体装置
US6025650A (en) * 1994-08-24 2000-02-15 Fujitsu Limited Semiconductor device including a frame terminal
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
EP0902471A3 (en) * 1997-09-12 1999-11-03 Oki Electric Industry Company, Limited Semiconductor integrated circuit device and package structure for the same
US6489680B2 (en) 1998-07-06 2002-12-03 Hitachi, Ltd. Semiconductor device
US7068521B2 (en) 1998-07-06 2006-06-27 Renesas Technology Corp. Semiconductor device
EP0971411A3 (en) * 1998-07-06 2000-09-06 Hitachi, Ltd. Semiconductor device
US8295057B2 (en) 1998-07-06 2012-10-23 Murata Manufacturing Co., Ltd. Semiconductor device
US6330165B1 (en) 1998-07-06 2001-12-11 Hitachi, Ltd. Semiconductor device
EP0971411A2 (en) * 1998-07-06 2000-01-12 Hitachi, Ltd. Semiconductor device
US7817437B2 (en) 1998-07-06 2010-10-19 Renensas Electronics Corporation Semiconductor device
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device
US6943441B2 (en) 1998-07-06 2005-09-13 Renesas Technology Corp. Semiconductor device
EP1770777A3 (en) * 1998-07-06 2009-01-21 Hitachi, Ltd. Semiconductor device with a shielding bond wire
EP1770777A2 (en) * 1998-07-06 2007-04-04 Hitachi, Ltd. Semiconductor device
EP1028428A1 (en) * 1999-02-12 2000-08-16 STMicroelectronics Limited Conductor structure
US6259018B1 (en) 1999-02-12 2001-07-10 Stmicroelectronics Limited Conductor structure
KR100394775B1 (ko) * 2000-12-14 2003-08-19 앰코 테크놀로지 코리아 주식회사 와이어본딩 방법 및 이를 이용한 반도체패키지
US7119004B2 (en) 2001-09-05 2006-10-10 Renesas Technology Corp. Semiconductor device, its manufacturing method, and ratio communication device
US7453147B2 (en) 2001-09-05 2008-11-18 Renesas Technology Corp. Semiconductor device, its manufacturing method, and radio communication device
WO2003023843A1 (fr) * 2001-09-05 2003-03-20 Renesas Thechnology Corp. Dispositif a semi-conducteur, son procede de fabrication et dispositif de communication radio

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