TW201036138A - Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure - Google Patents

Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure Download PDF

Info

Publication number
TW201036138A
TW201036138A TW098108666A TW98108666A TW201036138A TW 201036138 A TW201036138 A TW 201036138A TW 098108666 A TW098108666 A TW 098108666A TW 98108666 A TW98108666 A TW 98108666A TW 201036138 A TW201036138 A TW 201036138A
Authority
TW
Taiwan
Prior art keywords
wafer
substrate
recess
disposed
flip
Prior art date
Application number
TW098108666A
Other languages
Chinese (zh)
Other versions
TWI469310B (en
Inventor
Hung-Hsin Hsu
Chih-Wei Wu
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW98108666A priority Critical patent/TWI469310B/en
Publication of TW201036138A publication Critical patent/TW201036138A/en
Application granted granted Critical
Publication of TWI469310B publication Critical patent/TWI469310B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Wire Bonding (AREA)

Abstract

A flip-chip stacked package structure and its package method are disclosed herein. It utilizes a substrate provided with a cavity for arranging at least one chip stacked inside and stacking another chip thereon by utilizing the flip-chip step. There is also arranged other chip on another side of the substrate. The present invention can design the cavity into a stairway-type cavity for stacking chips and effectively improve the integrated density for the flip-chip package.

Description

201036138 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種晶片封裝技術，特別是關於一種 覆晶堆疊封裝結構及其封裝方法。 【先前技術】 〇 覆晶封裝是採用導電凸塊作為晶片與基板連接的封 裝技術。其係利用將晶片主動面朝下藉由凸塊與基板接 合，來達到封裝的方式。除了可大幅度提高晶片piN腳 的^度之外，更可以降低雜訊的干擾、強化電性的效能、 提咼散熱能力、及縮減封裝體積等。然而，如何增加覆晶 封裝之封裝體積集度亦為一重要課題。 【發明内容】 〇 I了解決上述問題，本發明目的之-係提供-種覆 晶堆疊封裝結構及其封褒方法，藉由使用具有凹穴之基板 將晶片以覆晶方式設置於内並可覆晶堆疊另一晶片於其 上，基板另-側亦可將晶片覆晶封裝於其上，可有效增加 覆晶封裝之積集度。 為了達到上述目的，本發明一實施例之一種覆晶堆 • 4封裝結構’係包括：—基板，係具有-上表面與一下表 面，其中至少一凹穴設置於基板之上表面；一第一晶片， . 係'設置於基板之凹穴底部’其中第一晶片之主動面係朝向 凹八底口P並與基板電性連接；一第二晶片，係設置於基板 3 201036138 之上表面，其中第二晶片係覆蓋凹穴且第二晶片之主動面 - 係朝向基板之上表面並與基板電性連接；一第三晶片，係 設置於基板之下表面，其中第三晶片之主動面係朝向基板 v 之下表面並與基板電性連接；以及複數個焊球，係設置於 基板之下表面。 本發明另一實施例之一種覆晶堆疊封裝方法，係包 括下列步驟：提供一基板，係具有一上表面與一下表面且 至少一凹穴設置於基板之上表面，其中複數個焊墊設置於 Ο 基板之上表面、下表面與凹穴底部上，且設置於凹穴底部 之焊墊係環繞凹穴底部之中心一黏著區域設置；用喷霧方 ，提供一助焊材料於焊墊上；設置一第一晶片於凹穴底 #，其中第一晶片之主動面係朝向凹穴底部並與焊墊電性 連，，叹置一第二晶片於基板之上表面，其中第二晶片係 覆蓋凹八且第二晶片之主動面係朝向基板之上表面並與 焊墊電性連接；設置一第三晶片，於基板之下表面，其中 第 片之主動面係朝向基板之下表面並與焊塾電性連 接，進行一覆晶底部填膠程序；以及設置複數個焊球於基 ) 板之下表面的焊塾上。 +以下藉由具體實施例配合所附的圖式詳加說明，當 更合易瞭解本發明之目的、技術内容、特點及其所達成之 功效。 【實施方式】 圖1A與圖iB所示為根據本發明一實施例之覆晶堆 疊封褒結構的剖面示意圖與正面透視圖。於本實施例中， 此覆晶堆疊封裝結構係包括：一基板10: —第一晶片20 ; 4 201036138 一第二晶片30 ; —第三晶片40 ;以及複數個焊球7〇。其 中，基板10具有一上表面16與一下表面18。第一晶片 20與第二晶片30係以覆晶方式堆疊於基板1〇 _側，而 弟二晶片4〇則以覆晶方式設置於基板1 〇之另側。201036138 VI. Description of the Invention: [Technical Field] The present invention relates to a chip packaging technology, and more particularly to a flip chip stacked package structure and a packaging method thereof. [Prior Art] 覆 Flip chip package is a package technology that uses conductive bumps as a connection between a wafer and a substrate. The method of achieving the package is achieved by bonding the active face of the wafer face down by the bumps to the substrate. In addition to greatly improving the piN of the wafer, it can reduce noise interference, enhance electrical performance, improve heat dissipation, and reduce package size. However, how to increase the package volume of the flip chip package is also an important issue. SUMMARY OF THE INVENTION In order to solve the above problems, the object of the present invention is to provide a flip chip stacked package structure and a sealing method thereof, by using a substrate having a recess to place a wafer in a flip chip manner. The flip chip is stacked on the other wafer, and the other side of the substrate can also be flip-chip mounted on the wafer, which can effectively increase the integration of the flip chip package. In order to achieve the above object, a flip chip stack 4 package structure of an embodiment of the present invention includes: a substrate having an upper surface and a lower surface, wherein at least one recess is disposed on an upper surface of the substrate; The wafer, is disposed at the bottom of the recess of the substrate, wherein the active surface of the first wafer is oriented toward the concave bottom port P and electrically connected to the substrate; a second wafer is disposed on the upper surface of the substrate 3 201036138, wherein The second wafer covers the recess and the active surface of the second wafer is oriented toward the upper surface of the substrate and electrically connected to the substrate; a third wafer is disposed on the lower surface of the substrate, wherein the active surface of the third wafer is oriented The lower surface of the substrate v is electrically connected to the substrate; and a plurality of solder balls are disposed on the lower surface of the substrate. A flip chip stacking method according to another embodiment of the present invention includes the following steps: providing a substrate having an upper surface and a lower surface and at least one recess disposed on the upper surface of the substrate, wherein the plurality of pads are disposed on the substrate之上 the upper surface of the substrate, the lower surface and the bottom of the recess, and the solder pad disposed at the bottom of the recess is disposed around the center of the bottom of the recess; a spray material is provided on the solder pad; The first wafer is at the bottom of the cavity, wherein the active surface of the first wafer faces the bottom of the cavity and is electrically connected to the pad, and a second wafer is slanted on the upper surface of the substrate, wherein the second wafer is covered by the concave And the active surface of the second wafer is directed toward the upper surface of the substrate and electrically connected to the solder pad; a third wafer is disposed on the lower surface of the substrate, wherein the active surface of the first film faces the lower surface of the substrate and is electrically connected to the soldering pad Sexual connection, a flip-chip underfill process; and a plurality of solder balls on the underside of the base plate. The following is a detailed description of the specific embodiments, the technical contents, the features, and the effects achieved by the present invention in conjunction with the accompanying drawings. [Embodiment] Figs. 1A and 1B are a cross-sectional view and a front perspective view showing a flip chip stacking structure according to an embodiment of the present invention. In this embodiment, the flip chip package structure includes: a substrate 10: a first wafer 20; 4 201036138 a second wafer 30; a third wafer 40; and a plurality of solder balls 7A. The substrate 10 has an upper surface 16 and a lower surface 18. The first wafer 20 and the second wafer 30 are stacked on the substrate 1 _ side in a flip chip manner, and the second wafer 4 设置 is provided on the other side of the substrate 1 in a flip chip manner.

接續上述說明，至少一凹穴14設置於基板1〇之上 表面16。基板10之上表面16、下表面18以及凹穴14 底部均設置有焊墊12。第一晶片20係設置於基板1〇之 凹穴14底部，其中第一晶片2〇之主動面係朝向凹穴14 底部並與基板10利用其上焊墊12電性連接。第二晶片 %係設置於基板10之上表面16，其中第二晶片3〇係覆 蓋凹穴14且第二晶片30之主動面係朝向基板1〇之上表 面16並與基板1〇利用其上焊墊12電性連接。另外，第 三晶片40係設置於基板1〇之下表面18，其中第三晶片 4〇之主動面係朝向基板1〇之下表面18並與基板ι〇利用 其上焊塾12電性連接；以及複數個焊球7()，係設置於基 板10之下表面18的焊塾12上。 凊參照上述說明，請參照圖2A與圖2F，於另一實 2中’基板1G上表面16設置的凹穴14可為一階梯狀 其中’於階梯狀凹穴14之底層與階梯狀凹穴Μ 二層的基板1G表面上均設置有複數個焊塾12於其 。—第四晶片50設置於階梯狀凹穴14之第二層上。i 曰^ 一晶片20係設置於階梯狀凹穴心底層；而細 曰曰片50係覆蓋第一晶片2〇 . 你紐人 阳乃，以及苐四晶片50之主動面 係朝向階梯狀凹穴14之篦__ % ^ ^ 之弟—層之基板10並與利用其上焊 势丨2與基板10電性連接。 汗 請參照圖2Α、圖2Β、m or si、 本發明一 圖 圖2C、圖2D、圖2E與圖2F， -實&例覆晶堆疊封裝方法係包括下列步驟。首 5 201036138 先，如圖2A所示，提供一基板10。此基板10具有一上 表面16與一下表面18且至少一凹穴14設置於基板1〇 之上表面16。其中，複數個焊墊12設置於基板10之上 表面16、下表面μ與凹穴14底部上。其中，設置於凹 穴14底部之焊墊12係環繞凹穴14底部之中心一黏著區 域设置’如圖1B所示。於本實施例中，凹穴14為一階 梯狀凹穴，除了底層設置焊墊12外，因此於階梯狀凹穴 14之第二層或其他層亦設置焊墊12於其上。Following the above description, at least one pocket 14 is disposed on the upper surface 16 of the substrate 1 . The upper surface 16 of the substrate 10, the lower surface 18, and the bottom of the recess 14 are each provided with a solder pad 12. The first wafer 20 is disposed on the bottom of the cavity 14 of the substrate 1 , wherein the active surface of the first wafer 2 faces the bottom of the cavity 14 and is electrically connected to the substrate 10 by the upper pad 12 . The second wafer % is disposed on the upper surface 16 of the substrate 10, wherein the second wafer 3 is covered by the recess 14 and the active surface of the second wafer 30 faces the upper surface 16 of the substrate 1 and is used with the substrate 1 The pad 12 is electrically connected. In addition, the third wafer 40 is disposed on the lower surface 18 of the substrate 1 , wherein the active surface of the third wafer 4 is directed toward the lower surface 18 of the substrate 1 and electrically connected to the substrate 1 using the upper solder pad 12 ; And a plurality of solder balls 7() are disposed on the solder bumps 12 on the lower surface 18 of the substrate 10. Referring to the above description, referring to FIG. 2A and FIG. 2F, in another embodiment 2, the recess 14 provided on the upper surface 16 of the substrate 1G may be a stepped shape in which the bottom layer of the stepped recess 14 and the stepped recess are formed. Μ Two layers of the substrate 1G are provided with a plurality of soldering fins 12 on the surface thereof. The fourth wafer 50 is disposed on the second layer of the stepped recess 14. i 曰^ A wafer 20 is disposed on the bottom layer of the stepped cavity; and the fine film 50 covers the first wafer 2 你. Your New Man Yang, and the active surface of the 晶片4 wafer 50 face the stepped cavity After 14 __ % ^ ^ brother - the substrate 10 of the layer is electrically connected to the substrate 10 by using the upper soldering force 丨 2 . Sweat Referring to Figure 2A, Figure 2, m or si, a second embodiment of the invention, Figure 2C, Figure 2D, Figure 2E and Figure 2F, the actual & First 5 201036138 First, as shown in FIG. 2A, a substrate 10 is provided. The substrate 10 has an upper surface 16 and a lower surface 18 and at least one recess 14 is disposed on the upper surface 16 of the substrate 1 . Wherein, a plurality of pads 12 are disposed on the upper surface 16 of the substrate 10, the lower surface μ and the bottom of the recess 14. Wherein, the solder pad 12 disposed at the bottom of the recess 14 is disposed around the center of the bottom of the recess 14 in an adhesive region as shown in Fig. 1B. In the present embodiment, the recess 14 is a stepped trap, and the pad 12 is disposed on the second layer or other layers of the stepped recess 14 in addition to the pad 12 disposed on the bottom layer.

接著，如圖2B所示，利用喷霧方式提供一助焊材料 於焊墊12上。之後，提供一黏著材料6〇，於黏著區域用 以黏著設置第一晶片20於凹穴14底部，如圖2C與圖2D 所示其中，第一晶片20之主動面係朝向凹穴μ底部並 與焊墊12電性連接。 於本實施例中，凹穴14為階梯狀，因此可疊置複數 個晶片於凹穴14内。繼續，請參照圖2E，設置一第四晶 片於階梯狀凹穴14之第二層上。其中，第一晶片2曰〇 係设置於階梯狀凹穴14之底層，而第四晶片5〇係覆蓋第 晶片20。第四晶片50之主動面係朝向階梯狀凹穴14 之第二層之基板1G並與其上焊塾12電性連接。於設置第 :晶片50前更包含一步驟，係提供一黏著材料6〇，於第 —晶片20之背面用以黏著第四晶片5〇。之後，設置— 二=於基板10之上表面16並覆蓋凹穴14。同樣的， 6 0 片3 °前更包含—步驟，係提供—黏著材料 、第四晶片50背面用以黏著第二晶片3〇。1中Next, as shown in Fig. 2B, a fluxing material is provided on the pad 12 by means of a spray. Thereafter, an adhesive material 6 is provided, and the first wafer 20 is adhered to the bottom of the cavity 14 in the adhesive region, as shown in FIG. 2C and FIG. 2D, wherein the active surface of the first wafer 20 faces the bottom of the cavity μ and It is electrically connected to the pad 12 . In the present embodiment, the recess 14 is stepped so that a plurality of wafers can be stacked in the recess 14. Continuing, referring to Figure 2E, a fourth wafer is placed on the second layer of the stepped recess 14. The first wafer 2 is disposed on the bottom layer of the stepped recess 14 and the fourth wafer 5 is covered on the first wafer 20. The active surface of the fourth wafer 50 faces the substrate 1G of the second layer of the stepped recess 14 and is electrically connected to the upper soldering pad 12. Further, before the setting of the wafer 50, a step of providing an adhesive material 6〇 is provided on the back surface of the first wafer 20 for bonding the fourth wafer 5〇. Thereafter, the setting - two = is on the upper surface 16 of the substrate 10 and covers the recess 14. Similarly, the 60 piece 3 ° step further includes a step of providing an adhesive material, and the back surface of the fourth wafer 50 is used to adhere the second wafer 3 . 1

So30係Γ凹穴14且第二晶片3〇之主動面係朝向 ，板:。之上表面16並與其上谭塾12電性連接。設置： 第二日曰片40於基板1〇之下表_。於設置第三晶片切 201036138 則更包含一步驟，係提供一黏著材料60，於基板1〇之下 表面18用以黏著第三晶片4〇。其中，第三晶片4〇之主 動面係朝向基板10之下表面18並與其上焊墊12電性連 • 接。於不同實施例中，如圖1A，第二晶片30係利用黏著 材料黏著固定於第一晶片20上。。 繼續上述說明，請參照圖2F，進行一覆晶底部填膠 程序填入底部填膠60’·以及設置複數個焊球7〇於基板1〇 :表面18的焊墊12上。其中，於進行覆晶底部填膠程序 0 前更包含一回焊（reflow)程序。 於上述實施例中，複數個導電凸塊（圖上未標）設 置於第一晶片20、第二晶片30、第三晶片4〇與第四晶片 5〇之主動面用以與設置在基板1〇上焊墊12電性連接。 本發明藉由使用具有凹穴之基板將晶片以覆晶方式 設置於内並可覆晶堆疊另一晶片於其上，基板另一側亦可 將晶片覆晶封裝於其上，可有效增加覆晶封裝之積集度， 且本發明可依照需求將凹穴設計成階梯狀用以堆疊複數 〇 個晶片。 以上所述之實施例僅係為說明本發明之技術思想及 特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之 内谷並據以實施，當不能以之限定本發明之專利範圍，即 大凡依本發明所揭示之精神所作之均等變化或修飾，仍應 涵蓋在本發明之專利範圍内。 7 201036138 【圖式簡單說明】 圖1A與圖1B所示為根據本發明一實施例之示意圖。 圖2A、圖2B、圖2C、圖2D、圖2E與圖2F所示為根據 本發明一實施例之示意圖。 【主要元件符號說明】The So30 system is recessed 14 and the active surface of the second wafer 3 is oriented, the plate:. The upper surface 16 is electrically connected to the upper layer 12 thereof. Settings: The second day of the cymbal 40 is on the substrate 1 〇 under the table _. The third wafer cut 201036138 further includes a step of providing an adhesive material 60 for bonding the third wafer 4 to the lower surface of the substrate. The main surface of the third wafer 4 is directed toward the lower surface 18 of the substrate 10 and electrically connected to the upper pad 12 thereof. In various embodiments, as shown in Fig. 1A, the second wafer 30 is adhesively attached to the first wafer 20 by an adhesive material. . Continuing with the above description, referring to Fig. 2F, a flip-chip underfill process is performed to fill the underfill 60' and a plurality of solder balls 7 are placed on the pads 12 of the substrate 1: surface 18. Among them, a reflow process is included before the flip chip bottom filling process 0. In the above embodiment, a plurality of conductive bumps (not shown) are disposed on the active surfaces of the first wafer 20, the second wafer 30, the third wafer 4, and the fourth wafer 5 to be disposed on the substrate 1 The solder pads 12 are electrically connected. In the present invention, the wafer is flip-chip mounted on the substrate by using a substrate having a recess and the other wafer can be stacked thereon, and the wafer can be flip-chip mounted thereon on the other side of the substrate, thereby effectively increasing the coverage. The degree of integration of the crystal package, and the present invention can design the recesses in a step shape for stacking a plurality of wafers as needed. The embodiments described above are merely illustrative of the technical spirit and characteristics of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the invention and to implement the invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. 7 201036138 [Schematic Description of the Drawings] FIGS. 1A and 1B are schematic views showing an embodiment of the present invention. 2A, 2B, 2C, 2D, 2E and 2F are schematic views showing an embodiment of the present invention. [Main component symbol description]

10 基板 12 焊墊 14 凹穴 16 上表面 18 下表面 20 第一晶片 30 第二晶片 40 第二晶片 50 第四晶片 60 底部填膠 60, 黏著材料 70 焊球10 Substrate 12 Pad 14 Pocket 16 Upper surface 18 Lower surface 20 First wafer 30 Second wafer 40 Second wafer 50 Fourth wafer 60 Underfill 60, Adhesive material 70 Solder balls

Claims (1)

201036138 七、申請專利範圍： 1. 一種覆晶堆疊封裝結構，係包含： 一基板，係具有一上表面與一下表面，其中至少一凹穴 設置於該基板之該上表面； 一第一晶>{，係設置於該基板之該凹穴底部，其中該第 一晶片之主動面係朝向該凹穴底部並與該基板電性連接，201036138 VII. Patent application scope: 1. A flip chip stacked package structure, comprising: a substrate having an upper surface and a lower surface, wherein at least one recess is disposed on the upper surface of the substrate; a first crystal > The ground surface of the first wafer is oriented toward the bottom of the cavity and electrically connected to the substrate. 〇 一第二晶片’係設置於該基板之該上表面，其中該第二 晶片係覆蓋該凹穴且該第二晶片之主動面係朝向'該基Λ板: 該上表面並與該基板電性連接； 一第二晶月，係設置於該基板之該下表面其中該第三 曰曰片之主動面係朝向該基板之該下表面並與該基板 接；以及 複數個焊球，係設置於該基板之該下表面。 :如為請-求階：二述之覆晶堆4封裝结構’其… i如2所述之覆晶堆疊封|結構，更 ㊁於該階梯狀凹穴之第二層± ’其中該第一 以及該第四晶片之主動面係朝向該 八之第一層之該基板與該基板電性連接。 4.如請求項3所述之覆晶堆疊封 複數個導電凸塊設置於該第一晶片包： 第三晶片鱼嗲々士 4片該第一日日片、該 上之複數個^舳日日片之動面用以與設置在該基板 上之钹數個焊墊電性連接。 5. 種覆晶堆疊封裝方法’係、包含下列步驟 9 201036138 提供-基板’係具有一上表面與一下表面且至少—凹穴 设置於祕板之該上表面，其中複數個焊塾設置於該基板之 該上表面、該下表面與該凹穴底部上，且設置於該凹穴底部 之該些焊墊係環繞該凹穴底部之中心—黏著區域設置； 利用喷霧方式提供一助焊材料於該些焊墊上； 1置-第一晶片於該凹穴底部，其中第一晶片之主動面 係朝向該凹穴底部並與該些焊墊電性連接； 设置-第二晶月於該基板之該上表面，其中該第二晶片a second wafer is disposed on the upper surface of the substrate, wherein the second wafer covers the recess and the active surface of the second wafer faces the substrate: the upper surface and the substrate a second crystal moon is disposed on the lower surface of the substrate, wherein the active surface of the third die faces the lower surface of the substrate and is connected to the substrate; and a plurality of solder balls are provided On the lower surface of the substrate. : If the order is - please: the above-mentioned flip-chip stack 4 package structure 'its... i, as described in 2, the flip-chip stack seal | structure, and the second layer of the stepped cavity ± 'which is the first And the active surface of the fourth wafer is electrically connected to the substrate facing the first layer of the eighth layer. 4. The flip chip stack according to claim 3 is provided with a plurality of conductive bumps disposed on the first wafer package: the third wafer fish gentleman 4 pieces of the first day film, the plurality of times of the last day The moving surface of the day is used to electrically connect with a plurality of pads disposed on the substrate. 5. A flip chip stacked package method, comprising the following steps 9 201036138 provides a substrate having an upper surface and a lower surface and at least - a recess is disposed on the upper surface of the secret board, wherein the plurality of solder pads are disposed on the The upper surface of the substrate, the lower surface and the bottom of the recess, and the pads disposed at the bottom of the recess are disposed around the center of the bottom of the recess-adhesive region; a soldering material is provided by spraying The first wafer is disposed at the bottom of the recess, wherein the active surface of the first wafer faces the bottom of the recess and is electrically connected to the pads; and the second crystal is disposed on the substrate The upper surface, wherein the second wafer ，覆盍該凹穴且該第二晶片之主動面係朝向該基板之該上 表面並與該些焊墊電性連接； 认置第二晶片，於該基板之該下表面，其中該第三晶 動面係朝向該基板之該下表面並與該些焊墊電性連 接； 進行一覆晶底部填膠程序；以及 設置複數個焊球於該基板之該下表面的該些焊墊上。 ::请求g 5所述之覆晶堆疊封裝方法，其中該凹穴 係為一階梯狀凹穴。 如胃請^項5所述之覆晶堆疊封裝方法，於設置該第 一曰曰片月、】更包含設置一第四晶片於該階梯狀凹穴之第 層上’其中該第一晶片係設置於該階梯狀凹穴之底 曰’·而該第四晶片係覆蓋該第_晶片；以及該第四晶 之主動面係朝向該階梯狀凹穴之第二層之該基板與 5亥些焊墊電性連接。 8如請^項7所述之覆晶堆疊封裝方法，於設置該第 片前更包含一步驟，係提供一黏著材料於該第一 日日片之背面用以黏著該第四晶片。 201036138 9.如請求項5所述之覆晶堆疊封 一晶片前更包含一步驟，係提供 區域用以黏著該第一晶片於該凹 • 10.如請求項5所述之覆晶堆疊封 ' 二晶片前更包含一步驟，係提供 晶片背面用以黏著該第二晶片。 11. 如請求項5所述之覆晶堆疊封 三晶片前更包含一步驟，係提供 〇 之該下表面用以黏著該第三晶片 12. 如請求項5所述之覆晶堆疊封 晶底部填膠程序前更包含一回焊 ❹ 裝方法，於設置該第 一黏著材料於該黏著 穴底部。 裝方法，於設置該第 一黏著材料於該第一 裝方法，於設置該第 一黏者材料於該基板 〇 裝方法，於進行該覆 (reflow )程序。 11Covering the recess and the active surface of the second wafer faces the upper surface of the substrate and is electrically connected to the pads; the second wafer is recognized on the lower surface of the substrate, wherein the third surface The crystallographic surface faces the lower surface of the substrate and is electrically connected to the pads; a flip-chip underfill process is performed; and a plurality of solder balls are disposed on the pads of the lower surface of the substrate. The method of claim 51, wherein the recess is a stepped recess. The method of flip-chip stacking according to item 5, wherein the first wafer is set, further comprising: providing a fourth wafer on the first layer of the stepped recess; wherein the first wafer is The fourth wafer is disposed on the bottom surface of the stepped recess; and the fourth wafer is covered by the first wafer; and the active surface of the fourth crystal is oriented toward the second layer of the stepped recess. The pads are electrically connected. 8. The flip chip stacking method of claim 7, further comprising a step of providing an adhesive material on the back side of the first day wafer for bonding the fourth wafer. 201036138 9. The flip-chip stacking of the wafer of claim 5 further comprises a step of providing a region for adhering the first wafer to the recess. 10. The flip-chip stacking package as claimed in claim 5 The second wafer further includes a step of providing a back surface of the wafer for bonding the second wafer. 11. The flip-chip stacking of the three wafers according to claim 5 further comprises a step of providing the lower surface for bonding the third wafer 12. The flip-chip stacked crystal bottom as described in claim 5 The filling process further includes a re-welding method for setting the first adhesive material to the bottom of the adhesive cavity. And a method of mounting the first adhesive material in the first mounting method to set the first adhesive material to the substrate mounting method to perform the reflow process. 11
TW98108666A 2009-03-17 2009-03-17 Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure TWI469310B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW98108666A TWI469310B (en) 2009-03-17 2009-03-17 Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98108666A TWI469310B (en) 2009-03-17 2009-03-17 Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure

Publications (2)

Publication Number Publication Date
TW201036138A true TW201036138A (en) 2010-10-01
TWI469310B TWI469310B (en) 2015-01-11

Family

ID=44856126

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98108666A TWI469310B (en) 2009-03-17 2009-03-17 Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure

Country Status (1)

Country Link
TW (1) TWI469310B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI480989B (en) * 2012-10-02 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof
TWI501379B (en) * 2013-06-10 2015-09-21 Powertech Technology Inc Pop device with co-used encapsulant
TWI607531B (en) * 2015-07-28 2017-12-01 鈺橋半導體股份有限公司 Package-on-package semiconductor assembly having bottom device confined by dielectric recess
CN108987381A (en) * 2018-08-14 2018-12-11 苏州德林泰精工科技有限公司 A kind of stacked chip package structure based on special-shaped resin gasket
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
TWI771242B (en) * 2021-04-28 2022-07-11 南亞科技股份有限公司 Dual die semiconductor package and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW591767B (en) * 2003-01-02 2004-06-11 Orient Semiconductor Elect Ltd Multi-chip, multi-carrier stack packaging structure
US7919848B2 (en) * 2007-08-03 2011-04-05 Stats Chippac Ltd. Integrated circuit package system with multiple devices

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI480989B (en) * 2012-10-02 2015-04-11 矽品精密工業股份有限公司 Semiconductor package and fabrication method thereof
TWI501379B (en) * 2013-06-10 2015-09-21 Powertech Technology Inc Pop device with co-used encapsulant
TWI607531B (en) * 2015-07-28 2017-12-01 鈺橋半導體股份有限公司 Package-on-package semiconductor assembly having bottom device confined by dielectric recess
CN108987381A (en) * 2018-08-14 2018-12-11 苏州德林泰精工科技有限公司 A kind of stacked chip package structure based on special-shaped resin gasket
CN108987381B (en) * 2018-08-14 2024-01-02 苏州德林泰精工科技有限公司 Stacked chip packaging structure based on special-shaped resin gasket
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN111554672B (en) * 2020-05-14 2022-09-27 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
TWI771242B (en) * 2021-04-28 2022-07-11 南亞科技股份有限公司 Dual die semiconductor package and manufacturing method thereof
US11469219B1 (en) 2021-04-28 2022-10-11 Nanya Technology Corporation Dual die semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
TWI469310B (en) 2015-01-11

Similar Documents

Publication Publication Date Title
TW201209986A (en) Semiconductor package structure and manufacturing process thereof
TW502406B (en) Ultra-thin package having stacked die
TWI255532B (en) Flip-chip ball grid array semiconductor package with heat-dissipating device and method for fabricating the same
TWI541954B (en) Semiconductor package and manufacturing method thereof
US8860215B2 (en) Semiconductor device and method of manufacturing the same
TWI395317B (en) Stacked-chip packaging structure and fabrication method thereof
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
TW200950050A (en) Semiconductor package device, semiconductor package structure, and method for fabricating the same
JP2010245383A (en) Semiconductor device and method of manufacturing the same
US12002721B2 (en) Method of fabricating semiconductor structure
TW201036138A (en) Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure
TWI269419B (en) Method for forming wafer-level heat spreader structure and packaging structure thereof
TW200837915A (en) Semiconductor device package
TW201227916A (en) Multi-chip stack package structure and fabrication method thereof
TW201112385A (en) Package process and package structure
TW200529387A (en) Chip package structure
TW200527620A (en) Semiconductor package
TW200939451A (en) Stacked semiconductor package
TWI566364B (en) Semiconductor package and manufacturing method thereof
TWI362101B (en) Method of fabricating a stacked type chip package structure and a stacked type package structure
TW200828458A (en) Semiconductor package and fabrication method thereof and stack structure
JP2004228142A (en) Semiconductor element and multi-chip package
TWI491014B (en) Method of forming semiconductor stack unit and semiconductor package
JP2000294722A (en) Laminated chip semiconductor device
TWI381508B (en) Semiconductor package device, semiconductor package structure, and method for fabricating the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees