CN111554672A - Chip stacking structure and chip stacking method - Google Patents
Chip stacking structure and chip stacking method Download PDFInfo
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- CN111554672A CN111554672A CN202010406019.1A CN202010406019A CN111554672A CN 111554672 A CN111554672 A CN 111554672A CN 202010406019 A CN202010406019 A CN 202010406019A CN 111554672 A CN111554672 A CN 111554672A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention provides a chip stacking structure and a chip stacking method, which relate to the technical field of chip packaging, and the chip stacking structure comprises: a substrate; a substrate chip layer attached to the substrate; a plurality of first chip stacking layers stacked on the substrate chip layer by layer in a step shape and electrically connected with the substrate; an intermediate chip stacking layer stacked on the first chip stacking layer; a plurality of second chip stacking layers stacked on the intermediate chip stacking layer by layer in a step shape; the widths of the first chip stacking layers are increased layer by layer along the stacking direction, the widths of the second chip stacking layers are decreased layer by layer along the stacking direction, and the widths of the first chip stacking layers and the second chip stacking layers are smaller than the width of the middle chip stacking layer. Compared with the prior art, the chip stacking structure provided by the invention can greatly increase the stacking quantity and greatly reduce the packaging size and the packaging cost.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip stacking structure and a chip stacking method.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized more and more thinly to meet the requirements of users and product performance and memory are higher and higher, so that a semiconductor packaging structure adopts a multi-chip Stack-Die (Stack-Die) technology or a chip fow (flow over wire) stacking technology to Stack two or more chips in a single packaging structure, thereby realizing the reduction of the packaging volume of the product and the improvement of the product performance. Such stacked products (memory cards/cards) usually have 2 types of chips, memory chips and chips, and are packaged in the same substrate unit by stacking.
In the existing stacking technology, the problems that the size of a packaging structure is too large, the stacking quantity of chips is small, the packaging process is too much due to too high stacking of the chips, the packaging material is too much, the cost is high and the like exist.
Disclosure of Invention
The invention aims to provide a chip stacking structure which can greatly increase the stacking quantity and greatly reduce the packaging size and the packaging cost.
Another objective of the present invention is to provide a chip stacking method, which can greatly increase the number of stacked chips and greatly reduce the package size and the package cost.
The invention is realized by adopting the following technical scheme.
In one aspect, the present invention provides a chip stacking structure, including: a substrate; a substrate chip layer attached to the substrate; a plurality of first chip stacking layers stacked on the substrate chip layer by layer in a step shape and electrically connected with the substrate; an intermediate chip stacking layer stacked on the first chip stacking layer while being electrically connected to the substrate and the first chip stacking layer; a plurality of second chip stacking layers which are stacked on the intermediate chip stacking layer in a step-like manner layer by layer and are electrically connected with the intermediate chip stacking layer; the widths of the first chip stacking layers are increased layer by layer along the stacking direction, the widths of the second chip stacking layers are decreased layer by layer along the stacking direction, and the widths of the first chip stacking layers and the second chip stacking layers are smaller than the width of the middle chip stacking layer.
Further, each first chip stacking layer comprises a plurality of first chips, the first chips of each layer are arranged side by side, and the first chips of two adjacent layers are arranged in a staggered mode, so that each first chip is stacked on the substrate chip layer or the other two adjacent first chips.
Further, each second chip stacking layer comprises a plurality of second chips, the second chips of each layer are arranged side by side, and the plurality of second chips of two adjacent layers are arranged in a staggered manner, so that each second chip is stacked on the middle chip stacking layer or the other two adjacent second chips.
Further, the chip stacking structure further comprises an overhead chip stacked on the second chip stacking layer and electrically connected with the second chip stacking layer.
Furthermore, a groove is arranged on the substrate, and the substrate chip layer is accommodated in the groove.
Further, the thickness of the base chip layer is the same as the depth of the groove, and the first chip stacking layer is stacked on the base chip layer and the substrate.
Further, the substrate chip layer comprises a bottom chip and a control chip, the control chip is attached in the groove, the bottom chip is stacked on the control chip, and the first chip stacking layer is stacked on the bottom chip.
Further, the substrate chip layer further comprises an adhesive layer, the adhesive layer is filled in the groove and covers the bottom chip and the control chip, and the thickness of the adhesive layer is the same as the depth of the groove.
Further, the chip stacking structure further comprises a plastic package body, and the plastic package body is wrapped outside the substrate chip layer, the first chip stacking layer, the middle chip stacking layer and the second chip stacking layer.
In another aspect, the present invention provides a chip stacking method, including the steps of:
stacking a base chip layer on a substrate;
stacking a plurality of first chip stacking layers on a substrate chip layer by layer;
stacking the intermediate chip stack layer on the first chip stack layer;
stacking a plurality of second chip stacking layers on the middle chip stacking layer by layer;
the widths of the first chip stacking layers are increased layer by layer along the stacking direction, the widths of the second chip stacking layers are decreased layer by layer along the stacking direction, and the widths of the first chip stacking layers and the second chip stacking layers are smaller than the width of the middle chip stacking layer.
The invention has the following beneficial effects:
according to the chip stacking structure provided by the invention, the width of the plurality of first chip stacking layers is increased layer by layer, the width of the plurality of second chip stacking layers is reduced layer by layer, and the width of the first chip stacking layers and the width of the second chip stacking layers are smaller than the width of the middle chip stacking layers, so that the whole chip stacking structure is in a spindle shape with a small upper part and a large middle part, chips between adjacent layers can be arranged in a staggered mode, wire bonding and electric connection are realized, more chips can be stacked in a unit volume compared with the existing chip stacking structure, the stacking height is reduced, the packaging size is reduced, and the packaging material is saved. Compared with the prior art, the chip stacking structure provided by the invention can greatly increase the stacking quantity and greatly reduce the packaging size and the packaging cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic overall structure diagram of a chip stacking structure according to a first embodiment of the invention;
fig. 2 is a schematic partial structure diagram of a chip stacking structure according to a first embodiment of the invention;
fig. 3 is a block diagram illustrating steps of a chip stacking method according to a second embodiment of the present invention.
Icon: 100-chip stacking structure; 110-a substrate; 111-grooves; 130-a substrate chip layer; 131-a control chip; 133-bottom chip; 135-glue layer; 150-first chip stack layer; 151-first chip; 160-top chip; 170-intermediate chip stack layer; 171-intermediate chip; 180-plastic package body; 190-a second chip stack layer; 191 — a second chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships conventionally put on the products of the present invention when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," "mounted," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As disclosed in the background art, the inventor has investigated and found that there are several chip stacking methods in the prior art, 1, the chips are mounted obliquely by using the existing stack-die technology, the longer the chip wire bonding on the top layer is, the more difficult it is to control the chip wire bonding, the unstable wire bonding (bridging/breaking) is easily caused, and the product package size is large. 2. By adopting the existing FOW stacking technology, stacking is carried out through a FOW (on-line circulation) film, after the chips are stacked, when the chips are wire-bonded to the top stacked chips, the longer the wire-bonding is, the more difficult the control is, the instable the wire-bonding (bridging/wire breaking) is easily caused, and the product packaging size is large.
That is, the FOW stacking technology/stack-die technology adopted in the prior art leads to a large product package size, a small number of stacked chips in a unit volume, and unstable wire bonding. The multilayer chip stacking packaging structure provided by the invention can solve the problems, and has the advantages of large stacking quantity and small packaging size.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. Features in the embodiments described below may be combined with each other without conflict.
First embodiment
Referring to fig. 1 and fig. 2 in combination, the present embodiment provides a chip stacking structure 100, which can stack more chips as much as possible while ensuring stacking electrical connection by forming a spindle-shaped stacking structure, so as to greatly increase the stacking number, greatly reduce the package size and the package cost, and make wire bonding more stable.
The chip stacking structure 100 provided in this embodiment includes: a substrate 110; a substrate chip layer 130 attached to the substrate 110; a plurality of first chip stacking layers 150 stacked on the base chip layer 130 in a step-like manner and electrically connected to the substrate 110; an intermediate chip stack layer 170 stacked on the first chip stack layer 150 while being electrically connected to the substrate 110 and the first chip stack layer 150; a plurality of second chip stacking layers 190 stacked on the intermediate chip stacking layer 170 in a stepped manner and electrically connected to the intermediate chip stacking layer 170; and a plastic package body 180 wrapping outside the substrate chip layer 130, the first chip stacked layer 150, the middle chip stacked layer 170, and the second chip stacked layer 190. The widths of the first chip stacking layers 150 increase layer by layer along the stacking direction, the widths of the second chip stacking layers 190 decrease layer by layer along the stacking direction, and the widths of the first chip stacking layers 150 and the second chip stacking layers 190 are both smaller than the width of the middle chip stacking layer 170.
In the embodiment, the first chip stacking layer 150 is stacked on the base chip layer 130, the middle chip stacking layer 170 is stacked on the first chip stacking layer 150, the second chip stacking layer 190 is stacked on the middle chip stacking layer 170, the first chip stacking layers 150 are stacked step-shaped layer by layer, the second chip stacking layers 190 are stacked step-shaped layer by layer, in the direction from bottom to top, the width of the first chip stacking layer 150 increases layer by layer, the width of the second chip stacking layer 190 decreases layer by layer, and the width of the middle chip stacking layer 170 is the largest, so that a spindle-shaped structure with a small top and a large middle is formed, and both sides of the chip layers between two adjacent layers are step-shaped, so that a routing space is ensured, chips between adjacent layers can be staggered, routing electrical connection is realized, and more chips can be stacked in a unit volume compared with the existing chip stacking structure, and the stacking height is reduced, the packaging size is reduced, and packaging materials are saved.
It should be noted that, in the present embodiment, the width of the first chip stacked layer 150 and the width of the second chip stacked layer 190 are both smaller than the width of the middle chip stacked layer 170, which means that the widths of the plurality of first chip stacked layers 150 and the plurality of second chip stacked layers 190 are both smaller than the width of the middle chip stacked layer 170, that is, the width of the middle chip stacked layer 170 is the largest in the left-right direction.
In this embodiment, the plastic package body 180 is molded by a plastic package material, the stacked chip structure is protected by the plastic package body 180, and the stacked structure can be effectively protected by the plastic package body 180, so that stable support is provided, and subsequent packaging action is facilitated.
Further, the chip stacking structure 100 further includes a top-mounted chip 160, and the top-mounted chip 160 is stacked on the second chip stacking layer 190 and electrically connected to the second chip stacking layer 190. Specifically, the overhead chip 160 is stacked on the uppermost chip stack layer, thereby forming a tower tip structure.
It should be noted that the stacking direction mentioned in the present embodiment refers to a mounting order direction in actual stacking, and in the present embodiment refers to a direction from bottom to top in the drawing, that is, the first chip stacking layer 150 and the base chip layer 130 are in an inverted pyramid shape, the second chip stacking layer 190 and the top chip 160 are in a pyramid shape, and preferably, the pyramid shapes on the upper side and the lower side are symmetrically arranged.
It should be noted that, in the stacking process mentioned in this embodiment, all the stacking processes are performed by attaching the FOW film during actual stacking, so as to ensure the stability of the structure. Of course, the chips can be mounted by other methods such as silver paste or heat-resistant glue, but any mounting method that can realize the mutual bonding and fixation of the chips is within the protection scope of the present invention.
Each first chip stacked layer 150 includes a plurality of first chips 151, the first chips 151 of each layer are arranged side by side, and the plurality of first chips 151 of adjacent two layers are staggered such that each first chip 151 is stacked on the base chip layer 130 or the other two adjacent first chips 151. Specifically, the number of chips in the first chip stacking layer 150 sequentially increases from bottom to top, so that the width also sequentially increases, the bottom layer is two first chips 151, the top layer is three first chips 151, and so on. The bottom two first chips 151 are stacked side by side on the base chip layer 130.
In the present embodiment, two adjacent first chips 151 in the same layer are arranged side by side at intervals and stacked on the left and right sides of the first chip 151 in the lower layer, respectively; be dislocation set between two adjacent first chips 151 in the adjacent intraformational height, the first chip 151 that is located the upper strata piles up on the left side or the right side that is located the first chip 151 of lower floor, through this kind of mode of piling up, can greatly improve whole stack structure's stability to can leave the routing space, realize stabilizing the routing.
Each second chip stacked layer 190 includes a plurality of second chips 191, the second chips 191 of each layer are arranged side by side, and the plurality of second chips 191 of two adjacent layers are arranged alternately, so that each second chip 191 is stacked on the middle chip stacked layer 170 or the other two adjacent second chips 191. Specifically, the number of chips in the second chip stack layer 190 decreases from bottom to top in sequence, so that the width also decreases in sequence, the top layer is two second chips 191, the bottom layer of the top layer is three second chips 191, and so on. The plurality of first chips 151 of the bottom layer are stacked side by side on the middle chip stack layer 170, and the two first chips 151 of the top layer are stacked side by side on the three second chips 191.
In the present embodiment, two adjacent second chips 191 in the same layer are arranged side by side at intervals and stacked on the left and right sides of the second chip 191 in the lower layer, respectively; be dislocation set between two adjacent second chips 191 in the adjacent layer from top to bottom, the second chip 191 that is located the upper strata piles up on the left side or the right side that is located the second chip 191 of lower floor, through this kind of mode of piling up, can greatly improve whole stack structure's stability to can leave the routing space, realize stabilizing the routing.
The middle chip stacking layer 170 includes a plurality of middle chips 171 arranged side by side, a plurality of middle chips 171 and a plurality of first chips 151 on the top layer are stacked in a staggered manner, and a plurality of second chips 191 on the bottom layer and a plurality of middle chips 171 are stacked in a staggered manner, that is, every two adjacent middle chips 171 are stacked on at least one first chip 151 on the top layer, and at least one second chip 191 on the bottom layer is stacked on the top of every two adjacent middle chips 171.
Note that the width of the first chip stacked layer 150 refers to a distance between two first chips 151 spaced farthest apart in the left-right direction within the same layer, the width of the second chip stacked layer 190 refers to a distance between two second chips 191 spaced farthest apart in the left-right direction within the same layer, and the width of the middle chip stacked layer 170 refers to a distance between two middle chips 171 spaced farthest apart in the left-right direction.
It should be noted that the term "top layer, bottom layer, upper layer, lower layer, etc. in this embodiment refers to the relative positions of the layers, for example, the first chip 151 of the bottom layer refers to a layer of the first chip 151 near the middle chip stacking layer 170, and the first chip 151 of the bottom layer refers to a layer of the first chip 151 near the substrate chip layer 130.
It should be noted that, in the present embodiment, the left side and the right side refer to the left side and the right side in the drawings, which indicate a relative direction and do not indicate an absolute direction.
In the present embodiment, the first chip stack layer 150 has two layers, and the lower first chip stack layer 150 includes two first chips 151, and the two first chips 151 are stacked side by side on the left and right sides of the base chip layer 130. The upper first chip stacking layer 150 includes three first chips 151 stacked side by side, the three first chips 151 stacked on the upper layer are staggered and stacked on the two first chips 151 on the lower layer, the middle chip stacking layer 170 includes four middle chips 171 stacked side by side, the four middle chips 171 are staggered and stacked on the three first chips 151 on the upper layer and extend out to the left and right sides, two middle chips 171 are stacked on each first chip 151, the four middle chips 171, the three first chips 151 on the upper layer, the two first chips 151 on the lower layer and the base chip form an inverted pyramid structure together, and the structure is stable and can accommodate a large number of chips.
It should be noted that, the number of layers of the first chip stacked layer 150 and the second chip stacked layer 190 is only an example, when the number of layers of the first chip stacked layer 150/the second chip stacked layer 190 is increased, each additional layer increases the number of first chips 151 of the layer by one compared with the number of first chips 151 of the lower layer, and simultaneously increases the number of intermediate chips 171 of the intermediate chip stacked layer 170 by one, for example, if the number of layers of the first chip stacked layer 150 is three, the number of first chips 151 at the topmost layer is four, and the number of intermediate chips 171 of the intermediate chip stacked layer 170 is five, and the number of layers is not specifically limited herein, and can be designed according to actual requirements.
It is noted that the first chips 151, the first chips 151 and the base chips, and the intermediate chips 171 and the first chips 151 are electrically connected by a connecting wire, and the first chips 151 or the intermediate chips 171 on the left and right side edges are electrically connected to the substrate 110 by a connecting wire.
In the present embodiment, the second chip stack layer 190 has two layers, the lower second chip stack layer 190 includes three second chips 191 stacked side by side, the three second chips 191 of the lower layer are stacked on the four middle chips 171 in a staggered manner, and one second chip 191 is stacked between every two adjacent middle chips 171. The second stacked chip layer of the upper layer includes two second chips 191 stacked side by side, the two second chips 191 of the upper layer are stacked on the three second chips 191 of the lower layer in a staggered manner, and the top-mounted chip 160 is stacked on the two second chips 191 of the upper layer. The four middle chips 171, the three second chips 191 on the lower layer, the two second chips 191 on the upper layer and the top chip 160 together form a pyramid structure, which is stable in structure and large in accommodating quantity.
It is noted that the electrical connection between two adjacent second chips 191, between the adjacent second chip 191 and the top chip 160, and between the adjacent middle chip 171 and the second chip 191 is realized by the connection lines.
It should be noted that the connecting wires in this embodiment are conventional bonding wires, such as gold wires, copper wires, alloy wires, or the like.
In the present embodiment, a groove 111 is provided on the substrate 110, and the base chip layer 130 is stacked in the groove 111. Through digging a groove on the substrate 110 and mounting the substrate chip layer 130, the substrate chip layer 130 sinks, the distance between the whole chip structure and the substrate 110 is reduced, the routing distance of the chip is effectively reduced, the problem that routing is unstable due to the traditional lamination process is solved, and the product yield is improved.
In the present embodiment, the thickness of the base chip layer 130 is the same as the depth of the groove 111, and the first chip stacked layer 150 is stacked on the base chip layer 130 and the substrate 110. Specifically, the base chip layer 130 is stacked in the groove 111 and flush with the surface of the substrate 110 around the groove 111, the two first chips 151 at the bottom are stacked on the base chip layer 130 in a staggered manner, the left side of the first chip 151 at the left side is stacked on the surface of the substrate 110 around the groove 111, the right side of the first chip 151 at the left side is stacked on the left side of the base chip layer 130, the left side of the first chip 151 at the right side is stacked on the right side of the base chip layer 130, and the right side of the first chip 151 at the right side is stacked on the surface of the substrate 110 around the groove 111. By stacking the first chip 151 on the bottom layer on the surface of the base chip layer 130 and the substrate 110, respectively, the structural stability is improved, and a stable foundation is provided for the subsequent stacking of the first chip 151, the middle chip 171 and the second chip 191 on the upper layer.
The substrate chip layer 130 includes a bottom chip 133, a control chip 131, and a glue layer 135, the control chip 131 is mounted in the recess 111, the bottom chip 133 is stacked on the control chip 131, and the first chip stack layer 150 is stacked on the bottom chip 133. The glue layer 135 is filled in the groove 111 and covers the bottom chip 133 and the control chip 131, and the thickness of the glue layer 135 is the same as the depth of the groove 111. Specifically, the control chip 131 is stacked in the groove 111, and the groove 111 is filled with glue, after the glue is cured, a glue layer 135 is formed, and the glue layer 135 is flush with the surface of the substrate 110 and covers and protects the bottom chip 133 and the control chip 131.
In this embodiment, the bottom chip 133 and the control chip 131 are electrically connected to the substrate 110 through the connection line, and the adhesive layer 135 is disposed to protect the connection line, improve the strength of the connection line, and increase the stacking area of the bottom of the substrate 110, thereby providing a stable foundation for stacking chips on the substrate 110 and realizing stacking of chips with more numbers.
It should be noted that, in the present embodiment, the bottom chip 133, the first chip 151, the second chip 191, the middle chip 171, and the top chip 160 are all memory chips, and the whole stacking structure is used to increase the stacking number or reduce the stacking height, so as to reduce the package size, reduce the product packaging process, reduce the packaging material, and reduce the packaging cost. Of course, the chip may be other types of chips, such as a processor or an LED chip, and is not limited in detail herein.
In summary, according to the chip stacking structure 100 provided by the embodiment, the stacked base chip layer 130, the first chip stacking layer 150, the middle chip stacking layer 170, and the second chip stacking layer 190 make the whole chip stacking structure 100 in a spindle shape with a small top and a large middle, and chips between adjacent layers can be arranged in a staggered manner, so that wire bonding and electrical connection are realized, more chips can be stacked in a unit volume compared with the existing chip stacking structure, the stacking height is reduced, the package size is reduced, and the package material is saved. Meanwhile, the groove is formed in the substrate 110, so that the routing height is reduced, the routing distance is effectively reduced, the problem that the routing is unstable (bridging/breaking) easily caused by the traditional lamination process is solved, and the product yield is improved.
Second embodiment
Referring to fig. 3, the present embodiment provides a chip stacking method for stacking and forming the chip stacking structure 100 provided in the first embodiment, the method including the following steps:
s1: the substrate chip layer 130 is stacked on the substrate 110.
Specifically, the base chip layer 130 includes a control chip 131, an underlying chip 133 and a glue layer 135, the control chip 131 is attached to the groove 111 of the substrate 110 by using the FOW film, so that the wire bonding distance can be reduced, meanwhile, the underlying chip 133 is attached to the control chip 131 by using the FOW film, the stacking height of the underlying chip is consistent with the depth of the groove 111, glue is filled into the groove 111 after wire bonding, and the glue layer 135 wrapping the underlying chip 133 and the control chip 131 is formed after curing.
S2: a plurality of first chip stacked layers 150 are stacked on the base chip layer 130 layer by layer.
Specifically, the first chip stacked layer 150 is two layers, the lower first chip stacked layer 150 includes two first chips 151, and the two first chips 151 are stacked side by side on the left and right sides of the base chip layer 130, that is, the lower two first chips 151 are stacked on the left and right sides of the bottom chip 133, and then wire bonding is performed. The upper first stacked chip layer 150 includes three first chips 151 stacked side by side, and the upper three first chips 151 are stacked on the lower two first chips 151 in a staggered manner and then wire bonded.
S3: the intermediate chip stack layer 170 is stacked on the first chip stack layer 150.
Specifically, the middle chip stacking layer 170 includes four middle chips 171, and the four middle chips 171 are stacked on the three first chips 151 in the upper layer in a staggered manner, and then wire bonding is performed. Each first chip 151 is stacked with two middle chips 171, and the four middle chips 171, the upper three first chips 151, the lower two first chips 151 and the base chip form an inverted pyramid structure together, so that the structure is stable and the accommodating amount is large.
S4: a plurality of second chip stack layers 190 are stacked on the intermediate chip stack layer 170 layer by layer.
Specifically, the second chip stacking layer 190 is two layers, the lower second chip stacking layer 190 includes three second chips 191, the three second chips 191 are stacked on the four middle chips 171 side by side, that is, the three second chips 191 are stacked on the four middle chips 171 in a staggered manner, and then wire bonding is performed. The upper second chip stacking layer 190 includes two second chips 191, and the two second chips 191 are stacked on the three middle chips 171 side by side, that is, the two second chips 191 are stacked on the three second chips 191 in a staggered manner, and then wire bonding is performed.
In this embodiment, the widths of the first chip stack layers 150 increase layer by layer, the widths of the second chip stack layers 190 decrease layer by layer, and the widths of the first chip stack layers 150 and the second chip stack layers 190 are both smaller than the width of the middle chip stack layer 170.
As will be described in detail below, in the actual stacking process, the method includes wafer cutting-mounting the control chip 131, baking-wire bonding-mounting the bottom chip 133, wire bonding-dispensing-mounting the first chip 151, baking-wire bonding-mounting the intermediate chip 171, baking-wire bonding-mounting the second chip 191 and the top chip 160, baking-wire bonding-plastic sealing-printing-cutting-packaging as follows:
wafer cleavage: and cutting the whole wafer into single wafers along the cutting path by using laser/diamond, and attaching the FOW film to the back surface of the chip.
2. Mounting the control chip 131: the FOW film is used to attach the control chip 131 to the surface of the substrate 110, thereby reducing the chip wire bonding distance.
3. Baking: the FOW film is cured by baking to achieve the effect of fixing the chip on the surface of the substrate 110.
4. Routing: the copper wire/alloy wire/gold wire is used to achieve the effect of connecting the control chip 131 with the substrate 110 by wire bonding.
5. Mounting the bottom chip 133: the FOW film is stacked on the control chip 131 to form a chip stack, and the stack height of the chip stack is required to be consistent with the height of the groove 111 of the substrate 110.
6. Routing: the bottom chip 133 is connected to the substrate 110 by wire bonding.
7. Dispensing: and filling glue in the groove 111 of the substrate 110 to realize the consistency of the glue surface and the surface of the groove 111 of the substrate 110.
8. Baking: by baking, the glue is cured and a glue layer 135 is formed, protecting the wire arc and completing the surface mounting of the horizontal plane.
9. Mounting the first chip 151: two first chips 151 of a lower layer are respectively attached to the left and right sides of the bottom chip 133 by using the FOW film, and three first chips 151 of an upper layer are attached to two large first chips 151 of the lower layer side by side, so that the side-by-side attachment is realized.
10. Baking: by baking, the FOW film at the bottom of the first chip 151 is cured, and the effect of fixing the first chip 151 is achieved.
11. Routing: the first chips 151 on the edge are connected with the substrate 110 by wire bonding, and the adjacent first chips 151 are connected with each other by wire bonding.
12. Stacking the intermediate chip 171 upward: the intermediate chip 171 is mounted using the same method.
13. Baking: through the baking mode, the FOW film at the bottom of the middle chip 171 is cured, and the effect of fixing the middle chip 171 is achieved.
14. Routing: the middle chip 171 and the first chip 151 are electrically connected by wire bonding, and the middle chip 171 at the edge is electrically connected to the substrate 110 by wire bonding.
15. Stacking up the second chip 191 and the top-set chip 160: the second chip 191 and the top-mounted chip 160 are mounted using the same method.
16. Baking: by baking, the bottom FOW film of the second chip 191 and the top chip 160 is cured, so that the second chip 191 and the top chip 160 are fixed.
17. Routing: the second chip 191 and the middle chip 171, and the top chip 160 and the second chip 191 are electrically connected by wire bonding.
18. Plastic packaging: and protecting the stacked chips by using a plastic packaging material.
19. Printing: the required characters are engraved on the surface of the plastic package body 180 by using laser.
20. Cutting: and cutting the plastic-sealed product into single pieces by using a cutting knife.
Package: and (4) putting the cut single products into a tray, and packaging and delivering the products out of the warehouse.
The embodiment provides a chip stacking method, by means of the stacked base chip layer 130, the first chip stacking layer 150, the middle chip stacking layer 170 and the second chip stacking layer 190, the whole chip stacking structure 100 is in a spindle shape with a small top and a large middle, chips between adjacent levels can be arranged in a staggered mode, wire bonding and electrical connection are achieved, more chips can be stacked in a unit volume compared with the existing chip stacking structure, the stacking height is reduced, the packaging size is reduced, and packaging materials are saved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A chip stacking structure, comprising:
a substrate;
a substrate chip layer attached to the substrate;
a plurality of first chip stacking layers stacked on the substrate chip layer in a step shape and electrically connected with the substrate;
an intermediate chip stack layer stacked on the first chip stack layer while being electrically connected to the substrate and the first chip stack layer;
a plurality of second chip stacking layers which are stacked on the intermediate chip stacking layer in a step-like manner layer by layer and are electrically connected with the intermediate chip stacking layer;
the widths of the first chip stacking layers are increased layer by layer along the stacking direction, the widths of the second chip stacking layers are decreased layer by layer along the stacking direction, and the widths of the first chip stacking layers and the second chip stacking layers are smaller than the width of the middle chip stacking layer.
2. The chip stacking structure according to claim 1, wherein each of the first chip stacking layers comprises a plurality of first chips, the first chips of each layer are arranged side by side, and the plurality of first chips of two adjacent layers are arranged alternately, so that each of the first chips is stacked on the substrate chip layer or two other adjacent first chips.
3. The chip stacking structure according to claim 2, wherein each of the second chip stacking layers includes a plurality of second chips, the second chips of each layer are arranged side by side, and the plurality of second chips of two adjacent layers are arranged alternately, so that each of the second chips is stacked on the middle chip stacking layer or two other adjacent second chips.
4. The chip stacking structure of claim 1, further comprising an overhead chip stacked on and electrically connected to the second chip stacking layer.
5. The chip stacking structure of claim 1, wherein a groove is provided on the retractable substrate, and the substrate chip layer is stacked in the groove.
6. The chip stacking structure according to claim 5, wherein the thickness of the substrate chip layer is the same as the depth of the groove, and the first chip stack layer is stacked on the substrate chip layer and the substrate.
7. The chip stacking structure of claim 5, wherein the substrate chip layer comprises a bottom chip and a control chip, the control chip is mounted in the groove, the bottom chip is stacked on the control chip, and the first chip stacking layer is stacked on the bottom chip.
8. The chip stacking structure of claim 7, wherein the substrate chip layer further comprises a glue layer, the glue layer is filled in the groove and covers the bottom chip and the control chip, and the thickness of the glue layer is the same as the depth of the groove.
9. The chip stacking structure according to claim 1, further comprising a molding compound, wherein the molding compound covers the substrate chip layer, the first chip stacking layer, the middle chip stacking layer, and the second chip stacking layer.
10. A method of die stacking, comprising the steps of:
stacking a base chip layer on a substrate;
stacking a plurality of first chip stacking layers on the substrate chip layer one by one;
stacking an intermediate chip stack layer on the first chip stack layer;
stacking a plurality of second chip stacking layers on the middle chip stacking layer by layer;
the widths of the first chip stacking layers are increased layer by layer along the stacking direction, the widths of the second chip stacking layers are decreased layer by layer along the stacking direction, and the widths of the first chip stacking layers and the second chip stacking layers are smaller than the width of the middle chip stacking layer.
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