TW200917456A - Assembly including plural chips stacked as building blocks - Google Patents

Assembly including plural chips stacked as building blocks Download PDF

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Publication number
TW200917456A
TW200917456A TW96138574A TW96138574A TW200917456A TW 200917456 A TW200917456 A TW 200917456A TW 96138574 A TW96138574 A TW 96138574A TW 96138574 A TW96138574 A TW 96138574A TW 200917456 A TW200917456 A TW 200917456A
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Taiwan
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wafer
layer
substrate
wafers
pads
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TW96138574A
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Chinese (zh)
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TWI344203B (en
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Chih-Wei Wu
Hung-Hsin Hsu
Chien-Chi Chan
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Powertech Technology Inc
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Publication of TWI344203B publication Critical patent/TWI344203B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

Disclosed is an assembly including plural chips stacked as building blocks, where the chips are at least divided into three layers. A first chip in first layer is disposed on a substrate. A plurality of second chips in second layer are stacked on the first chip with overlapped and sharing a stacked surface of the first chip. At least a third chip in third layer is stacked on the second chips in a manner that the spacing between the second chips is located between the first and the third chips. Accordingly, the chips are firmly stacked as building blocks, stackable chip amount under a limited package thickness can be increased, and the lengths of bonding wires between the chips and the substrate can be shortened effectively to improve quality of electrical connections.

Description

200917456 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片堆疊技術，特別係有關 於一種多晶片積木式堆疊構造。 【先前技術】 在ic半導體晶片的封裝與組裝技術中，是希望可以 達到保護晶片並符合高速資料傳輸之要求。早期的積體 電路產品只有封裝一個晶片。若需要增加晶片數量，只 ί 能並列設置（side-by-side)於電路板上，而受限於電路板 之面積，所以並無法放置更多的晶片，因此其所能擺設 的晶片數量係有所限制。後來，為了不增加電路板之設 置空間，在同樣大小的電路板上設置更多的晶片，而發 展出多晶片堆疊構造，將多個具有相同或不相同功能的 晶片整合於同一微小元件内，與單晶片的1C元件相比 較之下，多晶片堆疊構造不但增加容量或/與功能，並 可縮短晶片之間的訊號傳遞路徑，故可提高整體的運作 I.-,: 效能。其内封之晶片可堆疊在晶片上的方式往上堆叠* 因此晶片之數量可以增加卻不會影響電路板上之黏晶 佔用面積。 如第ί圖所示，為習知多晶片堆疊構造之截面示意 圖。該多晶片堆疊構造1 0 0主要包含一基板11 0、以及 背對背堆疊之一第一晶片1 20與一第二晶片1 3 0。該基 板110係具有一上表面111、一下表面112及一打線槽 孔1 1 3，其中該基板1 1 0之複數個第一内接墊1 1 4與外 5 200917456 ife. -ifa* 11(" ^ 係位於該下表面1 1 2 ’複數個第二内接墊i i 5 係位於該上表面U1。該第一晶片120之第一主動面122 係形成有複數個第一銲墊121並朝向該基板n〇。並可 利用複數個打線形成之第一銲線141通過該打線槽孔 電陵連接該第一晶片1 2 0之第一銲墊！ 2 1與該基板 110之該些第一内接墊114。藉由一黏晶層1?〇之黏貼， 使該第二晶片130之第二背面133設置於該第一晶片 1 20之該第一背面i 23，以達成背對背晶片堆疊。其中， 該第二晶片130之第二主動面132形成有複數個第二銲 墊13 1，並可利用複數個打線形成之第二銲線丨42連接 s亥些第二銲墊至該基板11〇之第二内接墊115。複 數個銲球1 60係可設置於該基板丨丨〇之該些球墊丨〗6， 以供對外表面接合。此外，一封膠體丨5〇係形成於該基 板11 〇之該上表面1 1 1與該打線槽孔1 1 3，用以包覆該 些晶片120、130與該些銲線141、142。受限於上述第 一晶片1 2 0與第二晶片1 3 0之組合關係及其銲墊配置位 置’晶片堆疊數量會受到封裝厚度的限制，且該些第二 銲線142的長度明顯遠長於該些第一銲線ι41的長度， 導致連接第一晶片120與第二晶片130之傳輸速度不一 致，此外，該些第二銲線1 42容易受到該封膠體1 50形 成之模流影響而產生沖線問題。 另一種習知多晶片堆疊構造已被Haba等人所教示 於美國專利 US 6,376,904，名稱為「redistributed bond pads in stacked integrated circuit die package」，其係為 200917456 晶片非同心軸的偏移堆疊，當晶片的堆疊數量過多， 上層的晶片將越來越會往基板之一側邊偏斜，失去足 支樓，導致晶片堆疊之不穩定。 【發明内容】 本發明之主要目的係在於提供一種多晶片積木式 疊構造’能在一有限封裝厚度下增加晶片之可堆疊數 與晶片堆疊之穩定度，並能有效縮短晶片與基板間之 線距離’提高電性連接品質。 本發明之次一目的係在於提供一種多晶片積木式 疊構造，能有效縮短所使用電性連接晶片與基板之間 銲線長度’以提高電性連接品質，避免沖線。 本發明的目的及解決其技術問題是採用以下技術 案來實現的。依據本發明之一種多晶片積木式堆疊構 主要包含一基板、一第一層晶片、複數個第二層晶片以 一第三層晶片。該第一層晶片係設置於該基板並具有 數個第一銲墊與一疊晶表面。該些第二層晶片係局部 疊地設置於該第一層晶片，每一第二層晶片疊設於該 層晶片之該疊晶表面之面積係小於該疊晶表面之 分之一 ’每一第二層晶片係具有複數個第二銲墊，其 相鄰之該些第一層晶片之間係形成有一縫隙。該第二 晶片係疊覆於至少兩之該些第二層晶片，以使該些第 層晶片之間縫隙位於該第一層晶片與該第三層晶片 間。 本發明的目的及解決其技術問題還可採用以下技 越 夠 堆 量 銲 堆 之 方 造 及 複 重 第 中 層 之 術 7 200917456 措施進—步實現。 在㈤述的多晶片積木式堆疊構造中’該些第一銲墊與該 些第二鲜塾係可皆為中央型銲墊。 在削述的多晶片積木式堆疊構造中’該第一層晶片係可 具有相對於該疊晶表面之一第一主動面’其係朝向該基板。 在別述的多晶片積木式堆疊構造中，可另包含有複數個 第n以電性連接該m片之第—料至該基板， 並且該基板係具有一打線槽孔，以供該些第_銲線之通過。 。在别述的多晶片積木式堆疊構造中，每一第二層晶片係 可具有一遠離該基板之第二主動面。 在前述的多晶片積木式堆疊構造中，可另包含有複數個 第二銲線，以電性連接㈣二層晶片之第二銲塾至該基板。 在前述的多晶片積木式堆叠構造中，該第三層晶片係可 具有-遠離該基板之第三主動面並形成有複數個第三鮮塾。 在前述的多晶片積木式堆㈣造中，可另包含有複數個 第三銲線，以電性連接該第三層w之該些第三銲墊至該些 第二層晶片。 在前述的多晶片積木式堆疊構造中，該些第三銲墊係可 為中央型鲜塾。 在前述的多晶片積木式堆叠構造中，可另包含有一封膠 體，至少形成於該基板上，以密封該第一層晶片、該些第二 層晶片以及該第二層晶片。 在前述的多晶片積木式堆疊構造中，該封膠體更可填充 至該些第二層晶片之間縫隙。 200917456 在前述的多晶片積木式堆疊構造中，可另包含有複數個 外接端子’設置於該基板之一下表面。 在前述的多晶片積木式堆疊構造中，該些外接端子係可 包含複數個銲球。 在前述的多晶片積木式堆疊構造中，可另包含有複數個 支撐晶片，其係與該第一層晶片同層地設置於該基板並具有 複數個第四薛墊與一支樓表面。 . 在前述的多晶片積木式堆疊構造中，該些第二層晶片係 可更局部重疊地設置於該些支撐晶片之支撐表面。 在前述的多晶片積木式堆疊構造中，另包含有複數個第 二銲線，以電性連接該第二層晶片之第二銲墊至該些支撐晶 片之該些第四銲塾。 在前述的多晶片積木式堆疊構造中，可另包含有複數個 第三銲線與複數個第四銲線，該些第三銲線係電性連接該第 三層晶片之複數個第三銲墊至該些第二層晶片，該些第四銲 L 線係電丨生連接該些支#晶片之該些第四銲墊至該基板。 在前述的多晶片積木式堆疊構造中，該些第三銲墊與該 些第四銲墊係可皆為中央型銲墊。 【實施方式】 依據本發明之第一具體實施例，具體揭示一種多晶 片積木式堆疊構造。 α參閱第2圖所示，一種多晶片積木式堆疊構造2〇〇 包δ基板2 1 0、_第一層晶片22〇、複數個第二層晶 片230以及一第二層晶片240。該些晶片220、230與 200917456 240可為相同或不相同之晶片。在本實施例中，該些晶 片220、23 0與240係為實質相同之晶片，具有相同之 尺寸、電性功能與銲墊配置位置。 該基板210係具有一上表面211及一下表面212。 通常該基板2 1 0係為多層線路板，如印刷電路板或是陶 瓷基板。該基板2 1 0係更具有複數個第一内接墊2 1 4、 複數個第二内接墊2 1 5以及複數個外接墊2 1 6以及位於 該上表面211之複數個第二内接墊215，其中該些第一 内接墊2 1 4與該些外接墊2 1 6係位於該下表面2 1 2，該 些第二内接墊215係位於該上表面211。 該第一層晶片220係設置於該基板2 1 〇之上表面2 1 1 並具有複數個第一輝塾221與一疊晶表面222。其中該 疊晶表面222即為該第一層晶片220之晶片背面。該第 一層晶片220係另具有相對於該疊晶表面222之一第一 主動面223’其係朝向該基板210並形成有該些第一銲 墊 221。 §亥些第·—層晶片2 3 0 4系局部重疊地設置於該第一層 晶片220之疊晶表面222，每一第二層晶片230係具有 複數個第二銲墊231，其中相鄰之該些第二層晶片230 之間係形成有一縫隙232，該縫隙232可避免第二層晶 片2 3 0配置時之接合介面受到熱應力之作用而影響黏 晶強度。每一第二層晶片2 3 0疊設於該第—層晶片2 2 0 之該疊晶表面2 2 2之面積係小於該疊晶表面2 2 2之二分 之一，以供設置兩個第二層晶片2 3 0。 10 200917456 —層日日片24〇係疊覆於至少兩之該此 片230，以使該歧第-層日κ 23〇之門从二第一層曰日 第一層曰Η 一第一層曰曰片230之間鏠隙232位於該 中，該二層：:=“24°之間。在本實施例 對之背面二ΐ 一第三主動面243與-相 銲墊241。（苐二主動面243上形成有複數個第三 因此，該多晶片積木式堆疊構造2〇〇利用 合關係，可以洁5，… 剜用上述的組 達1丨隔層晶片（即第一層晶片220與第三 )之同〜軸堆疊，可以穩固多顆位 並列配置之日η r Pri你_ r間增且 日曰（P第一層晶片230)，在有限封裝厚度 下增加晶片之可堆疊數量與晶片堆疊之穩定度。並能有 效縮短日日日片與基板間之銲線距離，提高電性連接品質。 關於晶 + d 疋方法’每一上下晶片220、230與 240之間作可丄 '、 a蛛 ’、T精由一黏晶層將彼此黏貼固定，例如雙面 'S疋B产自黏膠（B_stage adhesive)皆可作為本案之 黏晶層’以固定該些晶片22〇、23〇、24〇。 ” 此外，關於晶片之電性連接方法可以利用打線形成 之銲線達成，該多晶片積木式堆疊構造2〇〇可另包含有 複數個第一銲線25 1，電性連接該第一層晶片22〇之第 一銲墊221至該基板210之該些第一内接墊214，並且 該基板2 1 0係具有一打線槽孔2丨3，以供該些第一銲線 251之通過。在本實施例中，該些第一銲墊221與該些 第二銲墊23 1係可皆為中央型銲墊。每一第二層晶片 230之第二主動面233係朝上而遠離該基板21〇。並利 200917456 用複數個第二銲線2 5 2，電性連接該第二層晶 第二銲墊231至該基板210之該些第二内接髮 樣地，該第三層晶片240之第三主動面243係 離該基板2 1 0，並以複數個第三銲線2 5 3電性 三層晶片240之該些第三銲墊241至該些第 230之該些第二鮮蟄231’再經由該些第二銲 性轉接至該基板2 1 0，故可以不需要長銲線。 三銲墊24 1係可同為中央型銲墊。 具體而言，該多晶片積木式堆疊構造200 有一封膠體260，至少形成於該基板210上， 第一層晶片220、該些第二層晶片230以及該 片240，以提供適當的封裝保護以防止電性短 污染。較佳地，該封膠體260更可填充至該些 片2 3 0之間縫隙2 3 2與該打線槽孔2 1 3。 此外’該多晶片積木式堆叠構造200可另 數個外接端子270，設置於該基板2 1 0之一下； 該些外接端子270係可包含複數個銲球、錫膏 或接觸針等等。在本實施例中，該些外接端子 銲球’藉以組成多晶片球格陣列封裝，並使載 片封裝構造200之該些晶片220、230及240 印刷電路板（printed circuit board, PCB)達成 關係。 在第二具體實施例中，揭示另一種多晶片 疊構造’如第3圖所示，該多晶片積木式堆邊 片230之 4 215 。同 朝上而遠 連接該第 一層晶片 線25 2電 而該些第 可另包含 以密封該 第三層晶 路與塵埃 第一層晶 包含有複 良面2 1 2 〇 、接觸墊 2 70係為 設於該晶 得與外部 電性連接 積木式堆 丨構造3〇〇 12 200917456 主要包含一基板310、一第一層晶片32〇、複數個 層晶片33〇、以及一第三層晶片34〇，與第一實施 之元件大體相同，故僅概述如下。在本實施例中， 晶片積木式堆疊構造300更包含有複數個支撐 380’與該第一層晶片320位於同一層。 該第一層晶片3 2 0係設置於該基板3 1 〇並具有 個第一輝塾321與一疊晶表面322。每一第二層晶片 係具有複數個第二銲墊3 3 1，其中相鄰之該些第二 片之間係形成有一縫隙3 3 2。該些第二層晶片3 3 0 部重疊地設置於該第一層晶片3 20，每一第二層 330疊設於該第一層晶片320之該疊晶表面322之 係小於該疊晶表面3 2 2之二分之一，以供設置兩個 層晶片330’並形成該縫隙332，避免該兩第二層 3 3 0做並列配置時易受熱應力之作用影響。該第三 片340係疊覆於至少兩之該些第二層晶片330，以 些第二層晶片3 3 0之間縫隙3 3 2位於該第一層晶片 與該第三層晶片340之間。該第三層晶片340係具 數個第三銲墊3 4 1。 該些支撐晶片3 8 0係與該第一層晶片3 2 0同層 置於該基板310並具有複數個第四銲塾381與一支 面3 82。該些第二層晶片；3 3 0係可更局部重疊地設 該些支撑晶片380之支撑表面382，藉以提供該些 層晶片3 3 0之黏晶支撐與打線支撑。其中，該支撑 3 82係可為該些支撐晶片380之主動面。並且相鄰 第二 例中 該多 晶片 複數 33 0 層晶 係局 晶片 面積 第二 晶片 層晶 使該 320 有複 地設 撐表 置於 第二 表面 之該 13 200917456 3 80亦形 第一層晶片3 2 0盥#於甘不/日^ /、位於其兩側之該些支撐晶片 成有一縫隙383。 該多晶片積木式堆疊構造3〇 J另包含有複數個第 一銲線351，電性連接該第一層曰 ^ 任忒弟層曰日片320之第一銲墊321 至該基板310。複數個第二銲線 弟杆琛352電性連接該些第二 層s日片330之第二銲墊331至該 ^ —叉擇晶片380之該些 第四銲墊381。具體而言，該多晶片 片積木式堆疊構造300 可另包含有複數個第三銲線353 興複數個第四銲線 3 5 4，該些第三銲線3 5 3係電性 逆接該第三層晶片340 之該些第三銲墊3 4 1至該些第二層晶片3 3 〇之第二銲塾 33卜該ϋ四料354係電性連接該些支擇晶片· 之該些第四銲墊381至該基板31〇 ’藉以層層堆疊晶片 之間形成打線連結之較短銲線，避#县 您光長鲜線之形成。 此外，該多晶片積木式堆疊構造3〇〇可另包含有一 封膠體360,至少形成於該基板31〇上， 層一、該些第二層晶片3 3 0、該第三 以及該些支撐晶片380,以提供適當的封裝保護以防止 電性短路與塵埃污染。較佳地，該封膠體36〇更可填充 至該些第二層晶片3 3 0之間縫隙23 2以及該第一晶片 2 2 0與該些支撐晶片3 8 0間之間缝隙3 8 3。 此外，該多晶片積木式堆疊構造300可另包含有複 數個外接端子370，設置於該基板310之下表面。在本 實施例中，該些外接端子37〇係可包含銲球，藉以形成 多晶片球格陣列封裝，並使載設於該晶片封裝構造3〇〇 14 200917456 内該些晶片320、330、340及380得與—外 板（printed circuit board, PCB)構成電性連接 因此，本發明之多晶片積木式堆疊構造 習知晶片堆疊不穩固或/與長銲線的問題， 限的封裝厚度增加晶片的堆疊數量。並能有 與基板間之銲線距離，提高電性連接品質。 以上所述’僅是本發明的較佳實施例而 本發明作任何形式上的限制，本發明技術方 所附申請專利範圍為準。任何熟悉本專業的 利用上述揭示的技術内容作出些許更動或3 變化的等效實施例，但凡是未脫離本發明技 容，依據本發明的技術實質對以上實施例所 單修改、等同變化與修飾，均仍屬於本發明 範圍内。 【圖式簡單說明】 第1圖：習知多晶片堆疊構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，一 木式堆疊構造之載面示意圖。 第3圖：依據本發明之第二具體實施例，另 積木式堆疊構造之截面示意圖。 【主要元件符號說明】 100多晶片堆疊構造 110基板 111上表面 1121 Π 3打線槽孔 11 4第一内接墊 11 5身 部印刷電路 關係。 ，可以解決 可以在一受 效縮短晶片 已，並非對 案範圍當依_ 技術人員可 ί多飾為等同 術方案的内 作的任何簡 技術方案的 種多晶片積 一種多晶片 •表面 $二内接墊 15 200917456 116 外接墊 120 第一晶片 121 第一銲墊 122 第—主動面 123 第一背面 130 第二晶片 131 第二銲墊 132 第二主動面 133 第二背面 141 第一銲線 142 第二銲線 150 封膠體 160 外接端子 170 黏晶層 200 多晶片積木式堆疊構造 210 基板 211 上表面 212 下表面 213 打線槽孔 214 第一内接整 215 第二内接墊 216 外接墊 220 第一層晶片 221 第一銲墊 222 疊晶表面 223 第一主動面 230 第二層晶片 231 第二銲塾 232 縫隙 233 第二主動面 240 第三層晶片 241 第三銲墊 242 背面 243 第三主動面 251 第一銲線 252 第二銲線 253 第三銲線 260 封膠體 270 外接端子 300 多晶片積木式堆疊構造 310 基板 320 第一層晶片 321 第一銲墊 322 疊晶表面 330 第二層晶片 331 第二銲墊 332 縫隙 340 第三層晶片 341 第三銲墊 16 200917456 3 5 1第一銲線 352第二銲線 353第三銲線 354第四銲線 360封膠體 370外接端子 380支撐晶片 3 83縫隙 381第四銲墊 382支撐表面 17BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stacking technique, and more particularly to a multi-wafer modular stacking configuration. [Prior Art] In the packaging and assembly technology of ic semiconductor wafers, it is desirable to achieve protection of the wafer and meet the requirements of high-speed data transmission. Early integrated circuit products only packaged one wafer. If you need to increase the number of wafers, you can only side-by-side on the board, but limited by the area of the board, so you can't place more chips, so the number of chips that can be placed is There are restrictions. Later, in order to increase the installation space of the board, more wafers were placed on the same size board, and a multi-wafer stack structure was developed to integrate a plurality of wafers having the same or different functions into the same minute component. Compared with the single-chip 1C component, the multi-wafer stack structure not only increases the capacity or/and function, but also shortens the signal transmission path between the wafers, thereby improving the overall operation I.-,: performance. The inner sealed wafers can be stacked on top of the wafer* so that the number of wafers can be increased without affecting the area occupied by the die on the board. As shown in the drawings, a cross-sectional schematic view of a conventional multi-wafer stack configuration is shown. The multi-wafer stack structure 100 mainly includes a substrate 110, and a first wafer 126 and a second wafer 1300 connected back to back. The substrate 110 has an upper surface 111, a lower surface 112 and a wire slot 1 1 3 , wherein the plurality of first inner pads 1 1 4 and outer 5 200917456 ife. -ifa* 11 of the substrate 110 " ^ is located on the lower surface 1 1 2 'the plurality of second inner pads ii 5 are located on the upper surface U1. The first active surface 122 of the first wafer 120 is formed with a plurality of first pads 121 and And facing the substrate n. The first bonding wire 141 formed by using a plurality of wires is electrically connected to the first pad of the first wafer 110 through the wire slot hole! An inner pad 114. The second back surface 133 of the second wafer 130 is disposed on the first back surface i 23 of the first wafer 110 by adhesion of a bonding layer 1 to achieve back-to-back wafer stacking. The second active surface 132 of the second wafer 130 is formed with a plurality of second pads 13 1 , and the second bonding pads 42 formed by using a plurality of wires are connected to the second pads to the substrate. a second inner pad 115 of 11. The plurality of solder balls 1 60 can be disposed on the substrate of the ball pad 丨6 for external appearance In addition, a glue layer 5 is formed on the upper surface 11 1 of the substrate 11 and the wire slot 1 1 3 for covering the wafers 120 and 130 and the bonding wires 141. 142. Restricted by the combination of the first wafer 120 and the second wafer 130 and its pad arrangement position 'the number of wafer stacks is limited by the package thickness, and the length of the second bonding wires 142 It is obviously longer than the length of the first bonding wires ι41, which causes the transmission speeds of the first wafer 120 and the second wafer 130 to be inconsistent. In addition, the second bonding wires 142 are easily subjected to the molding flow formed by the sealing body 150. A conventional multi-wafer stacking structure has been taught by Haba et al. in U.S. Patent No. 6,376,904, entitled "Redistributed Bond pads in stacked integrated circuit die package", which is a non-concentric axis of the 200917456 wafer. Offset stacking, when the number of stacked wafers is too much, the upper wafer will become more and more skewed toward one side of the substrate, losing the foot support, resulting in instability of the wafer stack. [Summary of the Invention] The object is to provide a multi-wafer modular stack structure that can increase the stackable number of wafers and the stability of the wafer stack in a limited package thickness, and can effectively shorten the line distance between the wafer and the substrate to improve the electrical connection quality. A second object of the present invention is to provide a multi-wafer modular stack structure, which can effectively shorten the length of the bonding wire between the electrically connected wafer and the substrate to improve the electrical connection quality and avoid the punching. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. A multi-wafer modular stack structure according to the present invention mainly comprises a substrate, a first layer wafer, and a plurality of second layer wafers as a third layer wafer. The first layer of wafer is disposed on the substrate and has a plurality of first pads and a stacked surface. The second layer of wafers are partially stacked on the first layer of wafers, and the area of each of the second layer of wafers stacked on the stacked surface of the layer of wafers is less than one of the surface of the stacked crystals. The second layer of the wafer has a plurality of second pads, and a gap is formed between the adjacent first layers of the wafers. The second wafer is overlaid on at least two of the second wafers such that a gap between the first wafers is between the first wafer and the third wafer. The object of the present invention and solving the technical problems thereof can also be achieved by the following techniques: the stacking of the welding stack and the re-weighting of the middle layer. In the multi-wafer modular stack structure described in (5), the first pads and the second fresh lines may all be central pads. In the illustrated multi-wafer modular stack configuration, the first layer of wafers can have a first active surface relative to the stacked surface that is oriented toward the substrate. In the multi-wafer modular stacking structure, the plurality of nth materials are electrically connected to the substrate, and the substrate has a wire slot for the first _The passage of the weld line. . In a multi-wafer modular stack configuration as described, each of the second wafer layers may have a second active surface remote from the substrate. In the foregoing multi-wafer modular stacking structure, a plurality of second bonding wires may be further included to electrically connect the second soldering pads of the (four) two-layer wafer to the substrate. In the foregoing multi-wafer modular stack configuration, the third layer wafer system can have a third active surface remote from the substrate and formed with a plurality of third fresh sputum. In the foregoing multi-wafer building block (4), a plurality of third bonding wires may be further included to electrically connect the third pads of the third layer w to the second layer wafers. In the aforementioned multi-wafer modular stack construction, the third pads may be central squid. In the foregoing multi-wafer modular stack configuration, a glue may be further included, at least formed on the substrate to seal the first layer wafer, the second layer wafer, and the second layer wafer. In the aforementioned multi-wafer modular stack construction, the encapsulant can be further filled into the gap between the second layer wafers. In the aforementioned multi-wafer modular stacking structure, a plurality of external terminals ' may be further disposed on a lower surface of the substrate. In the aforementioned multi-wafer modular stack construction, the external terminals may comprise a plurality of solder balls. In the foregoing multi-wafer modular stack configuration, a plurality of support wafers may be further disposed on the substrate in the same layer as the first layer wafer and have a plurality of fourth mats and a floor surface. In the aforementioned multi-wafer modular stack configuration, the second layer wafers may be disposed more partially overlapping the support surfaces of the support wafers. In the foregoing multi-wafer modular stacking structure, a plurality of second bonding wires are further included to electrically connect the second pads of the second layer of wafers to the fourth pads of the supporting wafers. In the foregoing multi-wafer modular stacking structure, a plurality of third bonding wires and a plurality of fourth bonding wires are further included, and the third bonding wires are electrically connected to the plurality of third bonding wires of the third layer wafer. Padding the second layer of wafers, the fourth plurality of wires are electrically connected to the fourth pads of the plurality of wafers to the substrate. In the above-mentioned multi-wafer building type stacking structure, the third bonding pads and the fourth bonding pads may all be central type pads. [Embodiment] According to a first embodiment of the present invention, a polycrystalline chip type stacked structure is specifically disclosed. As shown in Fig. 2, a multi-wafer modular stack structure 2 δ δ substrate 2 10 , a first layer wafer 22 〇, a plurality of second layer wafers 230 , and a second layer wafer 240 . The wafers 220, 230 and 200917456 240 may be the same or different wafers. In the present embodiment, the wafers 220, 230 and 240 are substantially identical wafers having the same dimensions, electrical functions and pad placement locations. The substrate 210 has an upper surface 211 and a lower surface 212. Usually, the substrate 210 is a multilayer wiring board such as a printed circuit board or a ceramic substrate. The substrate 210 includes a plurality of first interconnect pads 2 1 4 , a plurality of second interconnect pads 2 15 and a plurality of external pads 2 16 and a plurality of second inscribed interfaces on the upper surface 211 The pad 215, wherein the first inner pad 2 1 4 and the outer pad 2 16 are located on the lower surface 2 1 2 , and the second inner pads 215 are located on the upper surface 211 . The first layer of the wafer 220 is disposed on the surface 2 1 1 of the substrate 2 1 并 and has a plurality of first enamels 221 and a stacked surface 222 . The laminated surface 222 is the back side of the wafer of the first layer of wafer 220. The first layer of wafers 220 further has a first active surface 223' opposite to the stacked surface 222, which faces the substrate 210 and is formed with the first pads 221 . The plurality of layer-layer wafers 2 3 0 are partially overlapped on the stacked surface 222 of the first layer wafer 220, and each of the second layer wafers 230 has a plurality of second pads 231 adjacent to each other. A gap 232 is formed between the second layer wafers 230. The gap 232 prevents the bonding interface of the second layer of the wafer from being subjected to thermal stress and affects the die strength. The area of the stacked surface 2 2 2 of each of the second layer wafers 203 stacked on the first layer wafer 2 2 0 is less than one-half of the surface of the stacked crystal surface 2 2 The second layer of wafer 2 300. 10 200917456 - The layer of the Japanese film 24 is superimposed on at least two of the pieces 230 so that the door of the first layer of the layer is from the first layer of the first layer of the first layer The gap 232 between the cymbals 230 is located therein, and the two layers are:: = "24°. In the present embodiment, the back surface ΐ a third active surface 243 and the - phase pad 241. The active surface 243 is formed with a plurality of thirds. Therefore, the multi-wafer modular stacking structure can be used for cleaning, and the first layer of the wafer can be used. The third) is the same as the axis stack, which can stabilize the multi-bit side-by-side configuration of the day η r Pri and the 曰 r increase and the day 曰 (P first layer wafer 230), increase the stackable number of the wafer under the limited package thickness and The stability of the wafer stack can effectively shorten the wire distance between the day and the day and the substrate, and improve the electrical connection quality. About the crystal + d 疋 method 'between the upper and lower wafers 220, 230 and 240' , a spider ', T fine is adhered to each other by a layer of adhesive layer, for example, double-sided 'S疋B from B_stage adhesive) can be used The adhesive layer of the present invention is used to fix the wafers 22〇, 23〇, 24〇. ” In addition, the electrical connection method for the wafer can be achieved by using a wire formed by wire bonding, and the multi-chip building block structure can be Further comprising a plurality of first bonding wires 25 1 , electrically connecting the first pads 221 of the first layer of wafers 22 to the first interconnect pads 214 of the substrate 210 , and the substrate 2 1 0 has A plurality of slot holes 2 丨 3 are provided for the passage of the first bonding wires 251. In this embodiment, the first pads 221 and the second pads 23 1 may both be central pads. The second active surface 233 of each second layer of the wafer 230 is upwardly facing away from the substrate 21〇. And 200917456 is electrically connected to the second layer of the second bonding pad by using a plurality of second bonding wires 252. 231 to the second inscribed samples of the substrate 210, the third active surface 243 of the third layer wafer 240 is separated from the substrate 2 1 0, and the plurality of third bonding wires 2 5 3 are electrically three The third pads 241 of the layer wafer 240 to the second fresh slabs 231 ′ of the 230th portions are further transferred to the substrate 2 1 0 via the second solderability, so The three-pad 24 1 can be the same as the central solder pad. Specifically, the multi-chip modular stack structure 200 has a glue 260 formed on the substrate 210, the first wafer. 220. The second layer of the wafer 230 and the sheet 240 are provided to provide proper package protection to prevent short electrical contamination. Preferably, the encapsulant 260 is further filled into the gap between the sheets 2300. 2 and the wire slot 2 1 3. In addition, the multi-chip block stack structure 200 may have a plurality of external terminals 270 disposed under one of the substrates 2 1 0; the external terminals 270 may include a plurality of solder balls , solder paste or contact pins, etc. In this embodiment, the external terminal solder balls ' constitute a multi-chip ball grid array package, and the wafers 220, 230 and 240 printed circuit boards (PCBs) of the carrier package structure 200 are related. . In a second embodiment, another multi-wafer stack construction is disclosed as shown in Figure 3, which is 4 215 of the multi-wafer building block. The first layer of the wafer line 25 2 is electrically connected to the upper layer and the second layer of the crystal layer and the dust. The first layer of the crystal layer and the first layer of the dust are provided with the second layer of the surface layer 2 2 2 〇, the contact pad 2 70 The structure is provided on the substrate and the external electrical connection stacking structure 3〇〇12 200917456 mainly comprises a substrate 310, a first layer wafer 32, a plurality of layer wafers 33A, and a third layer wafer 34 That is, it is substantially the same as the components of the first embodiment, and therefore is only summarized as follows. In the present embodiment, the wafer building stack structure 300 further includes a plurality of supports 380' located in the same layer as the first layer wafer 320. The first layer of the wafer 300 is disposed on the substrate 3 1 〇 and has a first radiant 321 and a stacked surface 322. Each of the second layer wafers has a plurality of second pads 3 3 1 , and a gap 3 3 2 is formed between the adjacent second sheets. The second layer of wafers 3 3 0 are overlapped on the first layer of wafers 3 20 , and each of the second layers 330 is stacked on the stacked surface 322 of the first layer of wafers 320 is smaller than the stacked surface One-half of the 2 2 2 is used to set the two-layer wafer 330' and form the slit 332, so as to avoid the influence of thermal stress when the two second layers 330 are arranged side by side. The third piece 340 is overlaid on at least two of the second layer wafers 330, and the gap 3 3 2 between the second layer of wafers 300 is located between the first layer of wafers and the third layer of wafers 340 . The third wafer 340 is provided with a plurality of third pads 341. The support wafers are disposed on the substrate 310 in the same layer as the first layer of wafers 300 and have a plurality of fourth pads 381 and one surface 382. The second layer of wafers; the 3003 can be more partially overlapped with the support surfaces 382 of the support wafers 380, thereby providing the die bonding support and the wire bonding support of the layer wafers 300. The support 3 82 can be the active surface of the support wafers 380. And in the adjacent second example, the multi-wafer plurality of 33 0 layers of the wafer system area and the second wafer layer crystals are arranged on the second surface of the 320. The first layer of the wafer is also formed. 3 2 0盥#于甘不/日^ /, the support wafers on both sides thereof have a slit 383. The multi-wafer building block structure 3 〇 J further includes a plurality of first bonding wires 351 electrically connected to the first bonding pads 321 of the first layer 忒 忒 曰 曰 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 320 A plurality of second bonding wires 235 are electrically connected to the second pads 331 of the second layer s of the slabs 330 to the fourth pads 381 of the dicing wafers 380. Specifically, the multi-wafer chip stacking structure 300 may further include a plurality of third bonding wires 353 to reproduce a plurality of fourth bonding wires 3 5 4, and the third bonding wires 3 5 3 are electrically reversed. The third pads 341 of the three-layer wafer 340 to the second pads 33 of the second layer of wafers 346 are electrically connected to the plurality of the selected wafers The four pads 381 to the substrate 31〇' are formed by forming a short bonding wire between the stacked wafers and avoiding the formation of the light line of the county. In addition, the multi-wafer modular stack structure 3 can further include a glue body 360 formed on at least the substrate 31, the layer one, the second layer wafers 300, the third and the support wafers. 380 to provide proper package protection against electrical shorts and dust contamination. Preferably, the encapsulant 36 is further filled into the gap 23 2 between the second layer wafers 300 and the gap between the first wafer 220 and the supporting wafers 3 8 0 3 3 . In addition, the multi-wafer modular stack structure 300 may further include a plurality of external terminals 370 disposed on the lower surface of the substrate 310. In this embodiment, the external terminals 37 may include solder balls to form a multi-chip ball grid array package, and the chips 320, 330, 340 are disposed in the chip package structure 3〇〇14 200917456. And 380 can be electrically connected with a printed circuit board (PCB). Therefore, the multi-wafer modular stacking structure of the present invention has a problem that the wafer stack is unstable or/and the long bonding wire is limited, and the thickness of the package is increased. The number of stacks. And it can have the distance between the bonding wires and the substrate to improve the quality of electrical connection. The above description is only a preferred embodiment of the present invention and the present invention is to be limited in any form, and the scope of the patent application of the present invention is incorporated by reference. Any equivalent embodiments that are susceptible to the above-described teachings of the present invention may be modified, modified, and modified in accordance with the teachings of the present invention. All remain within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-wafer stack structure. Fig. 2 is a schematic view showing the surface of a wooden stacked structure in accordance with a first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a further stacking structure according to a second embodiment of the present invention. [Main component symbol description] 100 multi-chip stack structure 110 substrate 111 upper surface 1121 Π 3 wire slot hole 11 4 first inner pad 11 5 body printed circuit relationship. , can solve a multi-wafer that can be shortened on a wafer, not a scope of the case, or a technical solution that can be decorated as an equivalent solution. Pad 15 200917456 116 External pad 120 First wafer 121 First pad 122 First active surface 123 First back surface 130 Second wafer 131 Second solder pad 132 Second active surface 133 Second back surface 141 First bonding wire 142 Second bonding wire 150 sealing body 160 external terminal 170 bonding layer 200 multi-chip building block structure 210 substrate 211 upper surface 212 lower surface 213 wire slot 214 first inner 215 second inner pad 216 external pad 220 first Layer wafer 221 first pad 222 stacked surface 223 first active surface 230 second layer wafer 231 second pad 232 slit 233 second active surface 240 third layer wafer 241 third pad 242 back surface 243 third active surface 251 first bonding wire 252 second bonding wire 253 third bonding wire 260 sealing body 270 external terminal 300 multi-chip building block stacking structure 310 Plate 320 first layer wafer 321 first pad 322 laminated surface 330 second layer wafer 331 second pad 332 slot 340 third layer wafer 341 third pad 16 200917456 3 5 1 first wire 352 second welding Line 353 third bonding wire 354 fourth bonding wire 360 sealing body 370 external terminal 380 supporting wafer 3 83 slit 381 fourth bonding pad 382 supporting surface 17

Claims (1)

200917456 十、申請專利範圍： 1、一種多晶片積木式堆疊構造，包含： 一基板； 一第一層晶片，設置於該基板並具有複數個第一銲墊與 一疊晶表面； 複數個第二層晶#’局部重疊地設置於該第—層晶片， 母—第二層晶片疊設於該第一層晶片之該疊晶表面之 面積係小於該疊晶表面之二分之一，每一第二層晶片 係具有複數個第二銲墊，其中相鄰之該妆 .„ ^ 一乐一滑晶片 碼係形成有一縫隙；以及 二第三層晶片，疊覆於至少兩之該些第二層晶片，以使 5亥些第二層晶片之間縫隙位於該第-層晶片與該第： 層晶片之間。200917456 X. Patent Application Range: 1. A multi-wafer modular stack structure comprising: a substrate; a first layer of wafer disposed on the substrate and having a plurality of first pads and a stacked surface; a plurality of second The layered crystals are partially overlapped on the first layer wafer, and the area of the mother-second layer wafer stacked on the stacked surface of the first layer wafer is less than one-half of the surface of the stacked crystal, each of The second layer of the wafer has a plurality of second pads, wherein the adjacent one of the makeups is formed with a slit; and the second layer of the wafer is overlaid on at least two of the second The layer wafer is such that a gap between the second layer of wafers is between the first layer wafer and the first layer wafer. 2、如申請專利範圍第 其中該些第一銲 塾。 1項所述之多晶片積木式堆疊構造， 塾與該些第二銲墊係皆為中央型鲜 3、二請專利範圍f 1項所述之多晶片積木式堆叠構造， 八δ亥第一層晶片係具有相對於該疊晶表面之一第— 主動面，其係朝向該基板。 4如申5月專利範圍第3項所述之多晶片積木式堆疊構造， 另匕占有複數個第一銲線，以電性連接該第—層晶 :第-銲墊至該基板，並且該基板係具有—打線槽 ，以供該些第一銲線之通過。 s ^如申請專利範圍帛1項所述之多W積木0叠構造， 18 200917456 '、母一第二層晶片係具有一遠離該基板之第二主 面。 功 6、 如申請專利範圍第5項所述之多晶片積木式堆叠構造， 另包3有複數個第二銲線，以電性連接該第二層晶 之第二銲墊至該基板。 曰曰 7、 如申請專利範圍帛i項所述之多晶片積木式堆疊構造， 其中5玄第二層晶片係具有一遠離該基板之第三主動面 並形成有複數個第三銲墊。 8、 如申請專利範圍帛7項所述之多“積木式堆疊構造， 另包3有複數個第三薛線，以電性連接該第三層晶片 之該些第二銲墊至該些第二層晶片。 9、 如申請專利範圍第7項所述之多晶月積木式堆疊構造， 其中該些第三銲墊係為中央型銲墊。 1〇、如中請專利範圍第1項所述之多晶片積木式堆疊構 造，另包含有一封膠體，至少形成於該基板上以密 封該第一層晶片、該些第二層晶片以及該第三層晶片。 n、如申請專利範圍第10項所述之多晶只積木式堆疊構 造，其中該封膠體更填充至該些第二層晶片之間縫隙。 12、 如中請專㈣圍第i項所述之多晶片積木式堆疊構 造，另包含有複數個外接端子，設置於該基板之一下 表面。 13、 如申請專利範圍帛12項所述之多晶片積木式堆叠構 這’其中该些外接端子係包含複數個銲球。 14、 如申請專利範圍帛i項所述之多晶片積木式堆叠構 19 200917456 造，另包含有複數個支撑晶片，其係與該第一層晶片 冋層地設置於該基板並具有複數個第與 表面。 传 1 5、如申請專利範圍第14項所，+. 4々 喝所4之多晶片積木式堆疊構 造，其中該此第-屉S H你& 一 層θ曰片係更局部重疊地設置於該些 支撐晶片之支撐表面。 1 6、如申請專利範圍第15項戶 、 項所述之多晶片積木式堆疊構 造’另包含有複數個第-^曰& 1U弟一‘線，以電性連接該第二層 晶片之第二料至該些切晶片之該些第四鮮塾。 1 7、如申請專利範圍第1 6想&、+、 ^ ^ 項所述之多晶片積木式堆疊構 &另包含有複數個第三銲線與複數個第四鲜線，該 些第三銲線係電性連接該第三層晶片之複數個第三銲 墊至該些第二層晶片， Ά 5亥些第四銲線係電性連接該些 支撐晶片之該些第四銲墊至該基板。 申月專利乾圍第17項所述之多晶片積木式堆疊構 & ’其中@些第三銲塾與該些第四銲塾係皆為中央型 銲墊。 19、-種多日日日片積木式堆叠構造，包含—基板以及在該基 板上之複數層晶片，其中第一層與第三層晶片為同心軸 堆疊，至少兩倘第二層晶片係為並列配置並被爽設其間。 2〇、如申請專利範圍第19項所述之多晶片積木式堆叠構 造’其中該些層晶片係為實質相同之晶片。 2卜如巾請專利範圍第19項所述之多晶片積木式堆叠構 造’其中該些層晶片係皆具有複數個中央型辉墊。 20 200917456 2 2、如申請專利範圍第1 9項所述之多晶片積木式堆疊構 造，其中相鄰之該些第二層晶片之間係形成有一縫隙， 而該第一層與該第三層晶片之同心軸係對準於該縫隙。2. If the scope of the patent application is the first of these, the first welding 塾. The multi-wafer building block stacking structure described in the above paragraph, and the second soldering pad series are both the central type and the second type, and the multi-wafer building block type structure described in the patent range f1, The layer wafer has a first active surface with respect to the stacked surface facing the substrate. [4] The multi-wafer modular stacking structure described in claim 3 of the patent scope of the fifth aspect, further comprising a plurality of first bonding wires electrically connecting the first layer: the first bonding pad to the substrate, and The substrate has a wire slot for the passage of the first bonding wires. s ^ As claimed in the patent application 帛1, the multi-W building 0 stack structure, 18 200917456 ', the mother-second layer wafer has a second main surface away from the substrate. 6. The multi-wafer building block stacking structure of claim 5, wherein the plurality of second bonding wires are electrically connected to the second bonding pad of the second layer to the substrate. 7. The multi-wafer building block stacking structure of claim 1, wherein the fifth layer of the second layer has a third active surface away from the substrate and is formed with a plurality of third pads. 8. As claimed in the patent application 帛7 item, a plurality of "building block type stacking structures, and another package 3 having a plurality of third Xuexing lines electrically connecting the second pads of the third layer wafer to the first A two-layer wafer. 9. The polycrystalline monthly building block structure according to claim 7, wherein the third pads are central type pads. 1〇, as claimed in the first item of the patent scope The multi-wafer modular stack structure further includes a glue formed on the substrate to seal the first layer wafer, the second layer wafer, and the third layer wafer. n. The polycrystalline only building block stacking structure, wherein the encapsulant is further filled into the gap between the second layer of wafers. 12. The multi-wafer building block stacking structure described in item (i) Further, a plurality of external terminals are disposed on a lower surface of the substrate. 13. The multi-chip building block structure according to claim 12, wherein the external terminals comprise a plurality of solder balls. As stated in the scope of patent application 帛i The multi-wafer modular stack structure 19 200917456, further comprising a plurality of support wafers disposed on the substrate and having a plurality of first surfaces, and having a plurality of first surfaces. 14 items, +. 4 々 所 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 For example, the multi-wafer building block stacking structure described in the fifteenth item of the patent application section further includes a plurality of -1曰& 1U brother-one wires electrically connected to the second layer of the second layer wafer The fourth fresh squid of the cut wafers is obtained. 1 7. The multi-wafer building block structure & described in the <RTIgt; a third bonding wire and a plurality of fourth fresh wires, wherein the third bonding wires are electrically connected to the plurality of third bonding pads of the third layer wafer to the second layer wafers, and the fourth bonding wires are Electrically connecting the fourth pads of the support wafers to the substrate. The multi-wafer building block structure described in Item 17 of Liganwei & 'where @三等焊塾 and these fourth welding 塾 are central type pads. 19、- Multi-day and Japanese building blocks The stacked structure comprises a substrate and a plurality of layers of wafers on the substrate, wherein the first layer and the third layer of the wafer are concentrically stacked, at least two if the second layer of the wafer is in a side-by-side configuration and is refreshed therebetween. The multi-wafer modular stacking structure as described in claim 19, wherein the plurality of wafers are substantially identical wafers. 2, such as the multi-wafer modular stacking structure described in claim 19. Each of the layer wafer systems has a plurality of central type glow pads. The multi-wafer building block stacking structure of claim 19, wherein a gap is formed between the adjacent second layer wafers, and the first layer and the third layer are formed. The concentric shaft of the wafer is aligned with the gap. 21twenty one
TW96138574A 2007-10-15 2007-10-15 Assembly including plural chips stacked as building blocks TWI344203B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN115172310A (en) * 2022-09-05 2022-10-11 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN111554672B (en) * 2020-05-14 2022-09-27 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN115172310A (en) * 2022-09-05 2022-10-11 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof
CN115172310B (en) * 2022-09-05 2022-11-29 江苏长晶浦联功率半导体有限公司 Three-dimensional packaging structure and manufacturing method thereof

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