KR20160128709A - stacking method of thin type chip - Google Patents

stacking method of thin type chip Download PDF

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Publication number
KR20160128709A
KR20160128709A KR1020150060474A KR20150060474A KR20160128709A KR 20160128709 A KR20160128709 A KR 20160128709A KR 1020150060474 A KR1020150060474 A KR 1020150060474A KR 20150060474 A KR20150060474 A KR 20150060474A KR 20160128709 A KR20160128709 A KR 20160128709A
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KR
South Korea
Prior art keywords
thin
substrate
chips
thin chips
chip
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KR1020150060474A
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Korean (ko)
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KR101687706B1 (en
Inventor
유봉석
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주식회사 에스에프에이반도체
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Priority to KR1020150060474A priority Critical patent/KR101687706B1/en
Publication of KR20160128709A publication Critical patent/KR20160128709A/en
Application granted granted Critical
Publication of KR101687706B1 publication Critical patent/KR101687706B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a method of laminating a thin chip using a support rod capable of preventing warpage of a thin chip stacked on a top surface of a substrate, comprising the steps of: fixing a support rod having a predetermined height to one side of a top surface of the substrate; Placing the thin chips sequentially in an oblique direction on the upper surface of the substrate on which the support rods are fixed, so that the thin chips sequentially mounted in the oblique direction are brought into contact with the support rods; And wire bonding each of the thin chips and the substrate.

Description

[0001] The present invention relates to a stacking method of a thin type chip,

The present invention relates to a method of stacking thin chips, and more particularly, to a method of stacking thin chips that can prevent warpage of a thin chip stacked on a top surface of a substrate.

In the memory semiconductor packaging process, in order to integrate a larger amount of memory, thin chips are stacked on a standardized substrate in a high-temperature manner.

More specifically, there is an increasing number of cases in which the back surface of the wafer is ground, the back-ground wafer is cut, the chips obtained by cutting the wafer are superimposed on the substrate, and the laminated chip and the substrate are wire-bonded.

At this time, since the pattern layer of the surface is formed of various materials, the wafer has different coefficients of thermal expansion between layers and the degree of heat shrinkage of the respective interlayer adhesives, etc., and is bent easily due to plastic deformation due to frictional heat in the back grinding process.

For this reason, when the wafer is wheeled, there is a concern that the wafer is damaged. Therefore, the handling of the wafer must be more carefully performed, and the handling system must be elaborated.

1, the thin chip 30 is stacked in an oblique direction on the upper surface of the substrate 10, that is, the upper layer thin chip 30 A part of the upper layer thin chip 30 deviating from the lower layer thin chip 30 is caused to float in the air when one end of the lower layer thin chip 30 is stacked over one end of the lower layer thin chip 30, ) Is increased.

When the warpage of a thin chip stacked at a high stage is intensified in such a manner, damage is often caused, for example, by breaking or cracking of a thin chip in a subsequent molding process. In addition, So that the adhesion between the wire and the bonding pad deteriorates.

For the above reasons, in the field of the art, attempts have been made to develop a method of stacking thin chips to prevent warpage of a thin chip stacked on a substrate. However, up to now, satisfactory results have not been obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and provides a method of stacking thin chips that can solve the problem of damaging a thin chip due to warping of a thin chip when a thin chip is laminated on a substrate The purpose is to do.

The present invention also provides a method of stacking thin chips that can solve the problem that the adhesion force between the wires and the bonding pads is lowered as the bending portions of the thin chips move up and down when the thin chips are laminated on the substrate The purpose is to do.

According to another aspect of the present invention, there is provided a method of stacking thin chips using a support rod, the method comprising: fixing a support rod having a predetermined height to one side of a top surface of a substrate; Placing the thin chips sequentially in an oblique direction on the upper surface of the substrate on which the support rods are fixed, so that the thin chips sequentially mounted in the oblique direction are brought into contact with the support rods; And wire bonding each of the thin chips and the substrate.

The substrate is either a printed circuit board or a lead frame.

The support bar is formed to have a thickness that is thicker than the thickness of the thin chip.

The support bar is formed of a metal or hard synthetic resin.

The supporting rod has a seating surface having a larger cross-sectional area than the other portions at the upper and lower ends.

The support rods may be fixed to the substrate at a plurality of different heights.

According to another aspect of the present invention, there is provided a method of stacking thin chips using a support rod, the method comprising: fixing a support rod having a predetermined height to one side of a top surface of a substrate; Sequentially placing the thin chips in the oblique direction on the upper surface of the substrate on which the support rods are fixed, so that the thin chips sequentially mounted in the oblique direction are brought into contact with the support rods fixed to the substrate; Further securing another support rod to the end of the thin chip sequentially placed in the oblique direction; Sequentially placing other thin chips on the upper side of the thin chips sequentially mounted in the oblique direction in the direction of the longitudinal line so that the thin chips successively seated in the direction of the historical line are brought into contact with the further fixed support rods; And wire bonding each of the thin chips and the substrate.

The support rods may be additionally fixed in a plurality of different heights at the ends of the thin chips sequentially placed in the oblique direction.

In the method of laminating a thin chip according to the present invention, since a thin chip laminated at a high stage on the upper surface of a substrate is in contact with a support bar, the thin chip laminated at a high stage is supported by a support bar, There is an effect that warpage can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an exemplary view for explaining deflection of a thin chip laminated in a high-temperature state; Fig.
Fig. 2 is a process chart of a thin chip laminating method using a support rod according to the first embodiment of the present invention. Fig.
3 is an exemplary view for explaining fixing of a support bar in the first embodiment of the present invention.
4 is an exemplary view for explaining the seating of a thin chip in the first embodiment of the present invention.
5 is an exemplary view for explaining wire bonding in the first embodiment of the present invention.
6 is a process chart of a thin chip stacking method using a support rod according to the second embodiment of the present invention
Fig. 7 is an exemplary view for explaining the additional fixing of the support bars in the second embodiment of the present invention
8 is an exemplary view for explaining the additional seating of a thin chip in the second embodiment of the present invention
9 is an exemplary diagram for explaining wire bonding in the second embodiment of the present invention

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the method for laminating thin chips using the support rods according to the first embodiment of the present invention includes a step S1 for fixing the support rods, a step S2 for seating the thin chips, Step S3.

In the step S1, the support rod 20 having a predetermined height is fixed to one side of the upper surface of the substrate 10.

The substrate 10 may be either a printed circuit board or a lead frame.

The substrate 10 is a printed circuit board or a lead frame, so that the thin chip 30 is laminated on the upper surface of the printed circuit board or the thin chip 30 is laminated on the upper surface of the lead frame.

The support rods 20 may be thicker than the thin chips 30.

Since the support rods 20 are formed to have a thickness larger than the thickness of the thin chips 30, it is possible to stably support the thin chips 30 stacked at high speed through the support rods 20.

The support rods 20 are preferably formed of metal or hard synthetic resin.

Since the support rods 20 are formed of metal or hard synthetic resin, it is possible to stably support the thin chips 30, which are stacked at high speed through the support rods 20 due to their material properties.

The support rods 20 may be formed of wires.

The support rods 20 are formed of wires so that the support rods 20 are simply formed by cutting the wires to a predetermined length.

It is preferable that the support rods 20 have a seating surface 21 having a larger cross-sectional area than the other portions at the upper and lower ends.

The supporting surface of the supporting rod 20 is stabilized by applying or bonding an adhesive to the seating surface 21 by forming a seating surface 21 having a larger cross-sectional area than the other portions at the upper and lower ends of the supporting rod 20 .

The support rods 20 may be fixed to the substrate 10 at a plurality of different heights.

The plurality of support rods 20 are fixed to the substrate 10 at different heights so that the thin rods 30 can be supported by the support rods 20 through the support rods 20, The support of the thin chip 30 is stabilized.

In step S2, the thin chip 30 is sequentially placed in the oblique direction on the upper surface of the substrate 10 on which the support bar 20 is fixed, and the thin chip 30, which is sequentially placed in the oblique direction, So as to be brought into contact with the support rod 20.

In this step S2, the bottom of the uppermost layer of the thin chip 30, which is stacked in the oblique direction, is in contact with the upper end of the support bar 20.

The uppermost layer of the thin chip 30 stacked in the oblique direction on the upper end of the support bar 20 contacts the uppermost layer bottom in the step S2 so that the warpage of the uppermost layer of the thin chip 30 And the warpage of the lower layer located under the uppermost layer of the thin chip 30 is also prevented.

It goes without saying that the thin chips 30 are bonded to each other in the step S2.

When the uppermost layer of the thin chip 30 stacked in the diagonal direction by the support bar 20 is supported by the thin chips 30 bonded to each other in the step S2, It is also prevented.

Meanwhile, step S2 is characterized in that the thin chip 30, which is stacked at high speed in the oblique direction, is brought into contact with the support rod 20, except that the conventional thin chip mounting method is followed.

In step S3, the wires 40 are bonded to each of the thin chips 30 and the substrate 10.

The thin chip 30 and the substrate 10 are electrically connected to each other by wire 40 bonding each of the thin chips 30 and the substrate 10.

Meanwhile, the step (S3) follows the normal wire bonding method.

6, the method for laminating thin chips using the support rods according to the second embodiment of the present invention includes a step S1 'for fixing the support rods, a step S2' for seating the thin chips, (S4 ') of attaching a thin chip to the chip (S5'), and bonding the wire (S5 ').

The steps (S1 ') and (S2') are the same as the steps (S1) and (S2) in the first embodiment.

The step S3 'further fixes another support rod 20' on the end of the thin chip 30 which is sequentially placed in the oblique direction.

Here, the support rods 20 'may be additionally fixed to the ends of the thin chips 30, which are sequentially placed in the oblique direction, at different heights.

The support rods 20 'are additionally fixed to the ends of the thin chips 30 sequentially mounted in the oblique direction at different heights so that the support rods 20' are successively seated in each of the support rods 20 in the direction of the historical line described below The support of the thin chip 30 'is stabilized by the support bar 20' since the thin chip 30 'can be supported.

In step S4 ', the other thin chips 30' are sequentially placed on the upper side of the thin chips 30 which are sequentially placed in the oblique direction in the direction of the historical line, and the thin chips 30 ' 30 'are brought into contact with the support rods 20' which are further fixed.

In this step S4 ', the thin chips 30' are bonded to each other.

In the step S4 ', when the thin chips 30' are bonded to each other, any one layer of the thin chip 30 'stacked in the direction of the longitudinal direction by the support rods 20' is supported, Warpage of the lower layer joined to the lower portion is also prevented.

Meanwhile, in step S4 ', the thin chip 30' is sequentially placed on the upper side of the thin chip 30 sequentially placed in the oblique direction in the direction of the historical line, Except that the chip 30 'is brought into contact with the support rod 20' to which the chip 30 'is additionally fixed, except that the conventional thin chip mounting method is followed.

The step S5 'includes the step S3 of the first embodiment in which the bonding of the wire 40 is added between the thin chip 30' and the substrate 10, .

The lamination of the thin chips 30 through the method of laminating the thin chips using the support rods according to the first embodiment of the present invention will be described in detail as follows.

First, as shown in FIG. 3, the support rod 20 is fixed to one side of the upper surface of the substrate 10.

That is, step (S1) according to the first embodiment of the present invention is performed.

At this time, the support rod 20 has the seating surface 21 having a larger cross-sectional area than that of the other portions at the lower end thereof. By applying an adhesive between the seating surface 21 and the substrate 10, The support rod 20 can be fixed on the support base 20.

Next, as shown in FIG. 4, the thin chips 30 are sequentially placed on the upper surface of the substrate 10.

That is, the step (S2) according to the first embodiment of the present invention is carried out.

At this time, the thin chip 30 is seated in a diagonal direction, that is, one end of the upper layer is deviated from one end of the lower layer and faces the side of the support rod 20 in order to secure a bonding region of the individual wires 40, The thin chip 30 and the support bar 20 are brought into contact with each other.

The bottom surface of the thin chip 30 which is stacked at the high end by the support bar 20 is supported by the support member 20 so that the bottom deflection is blocked by the contact of the thin chip 30 with the high- The thin chip 30 is prevented from being warped.

Here, the support rod 20 is thicker than the thin chip 30, and is formed of metal or hard synthetic resin, so that the support of the thin chip 30 by the support rod 20 is stable .

Next, as shown in FIG. 5, each of the thin chips 30, which are stacked in a high-temperature state, and the substrate 10 are wire-bonded.

That is, the step (S3) according to the first embodiment of the present invention is carried out.

As each of the thin chips 30 stacked in a high-level is bonded to the substrate 10 by wires 40, the substrate 10 and the thin chips 30 stacked in a high-stage are electrically connected to each other.

The lamination of the thin chips 30 through the method of laminating the thin chips using the support rods according to the second embodiment of the present invention will now be described in detail.

First, the support rod 20 is fixed to one side of the upper surface of the substrate 10.

That is, step (S1 ') according to the second embodiment of the present invention is performed.

At this time, the support rod 20 has the seating surface 21 having a larger cross-sectional area than that of the other portions at the lower end thereof. By applying an adhesive between the seating surface 21 and the substrate 10, The support rod 20 can be fixed on the support base 20.

Next, the thin chips 30 are sequentially placed on the upper surface of the substrate 10.

That is, the step S2 'according to the second embodiment of the present invention is performed.

At this time, the thin chip 30 is seated in a diagonal direction, that is, one end of the upper layer is deviated from one end of the lower layer and faces the side of the support rod 20 in order to secure a bonding region of the individual wires 40, The thin chip 30 and the support bar 20 are brought into contact with each other.

The bottom surface of the thin chip 30 which is stacked at the high end by the support bar 20 is supported by the support member 20 so that the bottom deflection is blocked by the contact of the thin chip 30 with the high- The thin chip 30 is prevented from being warped.

Here, the support rod 20 is thicker than the thin chip 30, and is formed of metal or hard synthetic resin, so that the support of the thin chip 30 by the support rod 20 is stable .

Next, another support rod 20 'is further fixed to the end of the thin chip 30 which is seated in the oblique direction as shown in Fig.

That is, the step (S3 ') according to the second embodiment of the present invention is performed.

At this time, the support rod 20 'has the seating surface 21 having a larger cross-sectional area than that of the other portions at the lower end thereof, and an adhesive is applied between the seating surface 21 and the end of the thin chip 30 So that the support rod 20 'can be further fixed to the end of the thin chip 30.

Next, as shown in FIG. 8, other thin chips 30 'are sequentially seated on the thin chip 30.

That is, step (S4 ') according to the second embodiment of the present invention is performed.

At this time, the thin chip 30 'is seated in a state in which the one end of the upper layer is directed to the side of the support rod 20' which is further fixed away from one end of the lower layer in order to secure the bonding area of the individual wires 40 As the thin chip 30 'is further seated, the thin chip 30' and the support bar 20 'come into contact with each other.

The bottom surface of the thin chip 30 'to be additionally seated by the support bar 20' is supported by the support rod 20 'so that the bottom surface of the thin chip 30' This prevents warpage of the thin chip 30 'stacked at a high temperature.

Next, as shown in FIG. 9, each of the thin chips 30, which are stacked in a high-temperature state, and the substrate 10 are wire-bonded.

That is, the step S5 'according to the second embodiment of the present invention is performed.

Each of the thin chips 30 and 30 'stacked with the substrate 10 is electrically connected to the substrate 10 as the substrate 10 and the thin chips 30 and 30' do.

As described above, in the method for laminating thin chips according to the present invention, the thin chips 30 and 30 ', which are stacked in a high-level on the upper surface of the substrate 10, are in contact with the support rods 20 and 20' The chip 30 and 30 'are supported by the support rods 20 and 20' to prevent sagging to the lower portion. Thus, the thin chips 30 and 30 'can be prevented from being warped.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. And falls within the scope of protection of the invention.

10: substrate
20, 20 ': support bar
21: Seat face
30, 30 ': thin chip
40: wire
S1, S1 ': Step of fixing the support rod
S2, S2 ': Step of seating a thin chip
S3: Step of bonding wire
S3 ': step of further fixing the support rod
S4 ': step of further seating the thin chip
S5 ': Step of bonding wire

Claims (7)

Fixing a support rod having a predetermined height to one side of the upper surface of the substrate;
Placing the thin chips sequentially in an oblique direction on the upper surface of the substrate on which the support rods are fixed, so that the thin chips sequentially mounted in the oblique direction are brought into contact with the support rods;
Wire bonding each of the thin chips and the substrate;
Wherein the thin film is formed on the substrate.
Fixing a support rod having a predetermined height to one side of the upper surface of the substrate;
Sequentially placing the thin chips in the oblique direction on the upper surface of the substrate on which the support rods are fixed, so that the thin chips sequentially mounted in the oblique direction are brought into contact with the support rods fixed to the substrate;
Further securing another support rod to the end of the thin chip sequentially placed in the oblique direction;
Sequentially placing other thin chips on the upper side of the thin chips sequentially mounted in the oblique direction in the direction of the longitudinal line so that the thin chips successively seated in the direction of the historical line are brought into contact with the further fixed support rods;
Wire bonding each of the thin chips and the substrate;
Wherein the thin film is formed on the substrate.
3. The semiconductor device according to claim 1 or 2,
Being either a printed circuit board or a lead frame
A method of laminating thin chips using a supporting bar.
3. The apparatus according to claim 1 or 2,
A thinner thickness than the thin chip
A method of laminating thin chips using a supporting bar.
3. The apparatus according to claim 1 or 2,
The top and bottom of which have a larger cross-sectional area than other areas
A method of laminating thin chips using a supporting bar.
The apparatus as claimed in claim 1,
A plurality of which are fixed to the substrate at different heights
A method of laminating thin chips using a supporting bar.
The apparatus as claimed in claim 2,
A plurality of chips are fixed to the substrate and the thin chip at different heights
A method of laminating thin chips using a supporting bar.
KR1020150060474A 2015-04-29 2015-04-29 stacking method of thin type chip KR101687706B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN111739884A (en) * 2020-05-14 2020-10-02 甬矽电子(宁波)股份有限公司 Multilayer chip stacking packaging structure and multilayer chip stacking packaging method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060029925A (en) * 2004-10-04 2006-04-07 삼성전자주식회사 Multi-chip package and fabrication method thereof
KR20090043945A (en) * 2007-10-30 2009-05-07 주식회사 하이닉스반도체 Stack package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060029925A (en) * 2004-10-04 2006-04-07 삼성전자주식회사 Multi-chip package and fabrication method thereof
KR20090043945A (en) * 2007-10-30 2009-05-07 주식회사 하이닉스반도체 Stack package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554672A (en) * 2020-05-14 2020-08-18 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method
CN111739884A (en) * 2020-05-14 2020-10-02 甬矽电子(宁波)股份有限公司 Multilayer chip stacking packaging structure and multilayer chip stacking packaging method
CN111554672B (en) * 2020-05-14 2022-09-27 甬矽电子(宁波)股份有限公司 Chip stacking structure and chip stacking method

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