CN111816625B - Multilayer chip stacking structure and multilayer chip stacking method - Google Patents

Multilayer chip stacking structure and multilayer chip stacking method Download PDF

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CN111816625B
CN111816625B CN202010860570.3A CN202010860570A CN111816625B CN 111816625 B CN111816625 B CN 111816625B CN 202010860570 A CN202010860570 A CN 202010860570A CN 111816625 B CN111816625 B CN 111816625B
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chip
substrate
electrically connected
pad
step part
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CN111816625A (en
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何正鸿
孙杰
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Forehope Electronic Ningbo Co Ltd
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Forehope Electronic Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the invention provides a multilayer chip stacking structure and a multilayer chip stacking method, and relates to the technical field of chip stacking. The multilayer chip stacking structure comprises a substrate, a first type chip, a first plastic package body and a plurality of second type chips. The first type of chip is arranged on the substrate and electrically connected with the substrate, and the first type of chip is packaged by the first plastic package body. The first plastic package body is provided with a plurality of step parts, the plurality of second chips comprise a first chip and a second chip, each step part is at least provided with the first chip and the second chip in a stacking mode, the first chip is arranged on the step part, and the second chip is arranged on one side, far away from the step part, of the first chip; and each second type chip is electrically connected with the substrate. The multilayer chip stacking structure has the advantages of stable support, compact structure, small volume, easy routing and reliable connection.

Description

Multilayer chip stacking structure and multilayer chip stacking method
Technical Field
The invention relates to the technical field of chip stacking, in particular to a multilayer chip stacking structure and a multilayer chip stacking method.
Background
In the existing chip stacking technology, the FOW (flow over wire) stacking technology or Stack-Die (Stack-Die) technology is mostly adopted for stacking, and the higher the chip stacking is, the more difficult the wire bonding of the top chip is to control, which easily causes the instability of wire bonding; in addition, in the prior art, a staggered stacking process is adopted, the chips are stacked obliquely, the structure is unstable, and the chips are easy to collapse; and the existing stacking technology is adopted, the whole size of the packaging structure is larger, and the miniaturization design of electronic products is not facilitated.
Disclosure of Invention
The present invention provides a multilayer chip stacking structure and a multilayer chip stacking method, which are easy to wire, reliable in connection, compact and stable in structure, and small in size.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a multilayer chip stacking structure, including a substrate, a first type chip, a first plastic package body, and a plurality of second type chips;
the first type of chip is arranged on the substrate and electrically connected with the substrate, and the first plastic package body encapsulates the first type of chip;
the first plastic package body is provided with a step part, the plurality of second chips comprise a first chip and a second chip, the first chip and the second chip are stacked on the step part, the first chip is arranged on the step part, and the second chip is arranged on one side, far away from the step part, of the first chip; and the first chip and the second chip are both electrically connected to the substrate.
In an optional embodiment, the first chip is flip-chip mounted, the step portion is provided with a conductive pillar penetrating through the step portion, one end of the conductive pillar is electrically connected to the substrate, and the other end of the conductive pillar is exposed out of the step portion and electrically connected to the first chip.
In an optional embodiment, a first pad and a second pad are disposed on the first chip, the first pad is electrically connected to the substrate through the conductive pillar, and the second pad is electrically connected to the substrate through the conductive pillar, or the second pad is connected to the second chip on the step portion of the next layer.
In an alternative embodiment, the second chip is disposed on a side of the first chip away from the step portion in a face-up manner.
In an optional embodiment, a third pad, a fourth pad and a fifth pad are arranged on one side of the second chip away from the first chip, and the third pad is electrically connected with the substrate through a wire, or the third pad is electrically connected with the second chip on the step part of the next layer through a wire;
the fourth bonding pad is electrically connected with the second chip on the step part of the previous layer through a wire, and the fifth bonding pad is electrically connected with the first chip on the step part of the previous layer.
In an optional embodiment, a third chip is further disposed on the substrate, the third chip is disposed on the periphery of the first plastic package body, the first chip on the step portion adjacent to the substrate is flip-chip disposed on the step portion and the third chip, and the third chip is electrically connected to the substrate through a wire.
In an optional embodiment, the chip package further includes a second plastic package body, where the second plastic package body is disposed on the substrate and is used to package the first plastic package body and the second type of chip.
In a second aspect, an embodiment of the present invention provides a multilayer chip stacking method, including:
mounting a first type chip on a substrate;
forming a first plastic package body for plastically packaging the first type of chips;
arranging a step part on the first plastic package body;
and mounting a second chip on the step part.
Wherein the second type of chip comprises a first chip and a second chip; the first chip and the second chip are stacked on the step part, the first chip is arranged on the step part in a flip-chip mode, and the second chip is arranged on one side, far away from the step part, of the first chip in a normal mode; the second chip is electrically connected with the substrate through a lead.
In an optional embodiment, the method further includes forming a second plastic package body which plastically packages the second type chip and the first plastic package body.
In an optional embodiment, the step of providing a step on the first plastic package body includes:
a through hole is formed in the step part;
and filling a conductive material in the through hole to form a conductive column so that the second type of chip on the step part is electrically connected with the substrate through the conductive column.
In an alternative embodiment, the step of mounting the second type chip on the step portion includes:
the first chip is arranged in a flip-chip mode, and the second chip is arranged in a forward mounting mode;
a first bonding pad and a second bonding pad are arranged on the first chip, the first bonding pad is electrically connected with the substrate through the conductive column, the second bonding pad is electrically connected with the substrate through the conductive column, or the second bonding pad is connected with the second chip on the step part of the next layer;
a third bonding pad, a fourth bonding pad and a fifth bonding pad are arranged on one side, far away from the first chip, of the second chip, and the third bonding pad is electrically connected with the substrate through a wire, or the third bonding pad is electrically connected with the second chip on the step part of the next layer through a wire;
the fourth bonding pad is electrically connected with the second chip on the step part of the previous layer through a wire, and the fifth bonding pad is electrically connected with the first chip on the step part of the previous layer.
The beneficial effects of the embodiment of the invention include, for example:
the multilayer chip stacking structure is formed by plastically packaging a first type of chip on a substrate to form a first plastic package body. Set up step portion on first plastic-sealed body, through range upon range of first chip and the second chip of setting up on step portion, step portion plays the supporting role to first chip, and first chip and second chip all are connected with the base plate electricity, and compact structure piles up back product size little, and the routing is easy, stable in structure, difficult collapse.
The multilayer chip stacking method is characterized in that a first type of chip is arranged on a substrate, a first plastic package body for packaging the first type of chip is formed, the first plastic package body is used as a support, and a step portion is arranged on the first plastic package body and used for stacking a second type of chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic cross-sectional view of a stacked structure of a multi-layered chip stack structure according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of another stacking method of a multi-layered chip stacking structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first plastic package body with a multi-layer chip stacking structure according to an embodiment of the invention;
FIG. 4 is a diagram illustrating a stacking structure of a first type and a second type of chips in a multi-layered chip stacking structure according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a second type of chip stacking structure of a multi-layered chip stacking structure according to an embodiment of the invention;
FIG. 6 is a block diagram illustrating steps of a method for stacking multiple chips according to an embodiment of the present invention;
FIG. 7 is a first process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
FIG. 8 is a second process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
FIG. 9 is a third process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
FIG. 10 is a fourth process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
FIG. 11 is a fifth process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
FIG. 12 is a sixth process diagram illustrating a multi-layer chip stacking method according to an embodiment of the present invention;
fig. 13 is a seventh process diagram illustrating a multi-layer chip stacking method according to an embodiment of the invention.
Icon: 100-a multi-layer chip stack structure; 110-a substrate; 120-first type chips; 130-a first plastic package body; 131-conductive posts; 133-a step portion; 1301-a boss; 135-a mounting surface; 136-a top surface; 137-bottom surface; 138-outer peripheral surface; 140-chips of the second type; 141-a first chip; 142-a second chip; 145-a third chip; 146-a wire; 150-a second plastic package body; 160-solder ball; 151-first pads; 152-a second pad; 153-third pad; 154-fourth pad; 155-fifth pad; 161-protective film.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
With the rapid development of the semiconductor industry, the requirements of users on electronic products are higher and higher, and the miniaturization and thinning design of the electronic products are desired, and the product performance and the memory are also desired to be higher and higher. Therefore, the semiconductor packaging structure adopts a plurality of chips to be stacked, and two or more chips are stacked in a single packaging structure, so that the packaging volume of the product is reduced, the functional integration level is improved, and the product performance is improved.
The current stacking technology mainly includes the following:
the chip stacking-Die technology (Stack-Die) is used for obliquely mounting chips, the higher the chip stacking is, the longer the routing of the top chip is, the routing is difficult to control, the routing is easy to be unstable, bridging or breaking occurs, and the packaging size of a product is larger.
The flow over wire technology (FOW) is adopted, and the stacking mode is that after the chips are stacked, when the chips are wire-bonded to the top end of the stacked chips, the longer the wire-bonding is, the more difficult the control is, the instable the wire-bonding is easily caused, bridging or wire breaking occurs, and the packaging size of the whole product is larger.
Whether a Stack-Die technology (Stack-Die) or a FOW stacking technology is adopted, the higher the chip stacking is, the larger the product packaging size is; the higher the stack of chips, the more packaging processes, the more material used in the packaging process, and the higher the cost. In addition, the prior art also adopts the dislocation lamination packaging technology, and the chips are obliquely mounted left and right in the mode, so that the chips are stacked higher, the inclination of the left and right chips is larger, and the bottom layer structure of the chips is more unstable, thereby causing the structure of the stacked chips to collapse or collapse and damaging the product.
In order to overcome at least one defect in the prior art, the embodiment of the invention provides a multilayer chip stacking structure 100 and a multilayer chip stacking method, so that the product structure is stable, the product structure is not easy to collapse, the wire bonding is easy, the cost is saved, and the packaging size is reduced.
Referring to fig. 1, an embodiment of the invention provides a multilayer chip stack structure 100, which includes a substrate 110, a first type chip 120, a first plastic package body 130, and a plurality of second type chips 140. The first chip 120 refers to a memory chip or a memory chip, and may be collectively referred to as a control chip; the second type of chip 140 may be various types of functional chips, including but not limited to an image recognition chip, a fingerprint recognition chip, or other chips, and the multi-layer chip stack structure 100 may be suitable for stacked products, including but not limited to a memory card or a memory card, and the like, and is not limited herein.
The first type chip 120 is disposed on the substrate 110 and electrically connected to the substrate 110, and the first plastic package body 130 is disposed on a side of the substrate 110 close to the first type chip 120 for packaging the first type chip 120. The first plastic package body 130 is provided with one or more step portions 133, where fig. 1 shows one step portion 133, fig. 2 shows two step portions 133, and of course, the number of step portions 133 may also be three, four or more, and is not limited herein. The plurality of second chips 140 include a first chip 141 and a second chip 142, the first chip 141 and the second chip 142 are stacked on each step portion 133, the first chip 141 is disposed on the step portion 133, and the second chip 142 is disposed on a side of the first chip 141 away from the step portion 133; note that, the stacked arrangement here should be understood as the lower surface of the second chip 142 being attached to the upper surface of the first chip 141. The first chip 141 is arranged in an inverted manner, and the second chip 142 is arranged in a forward-mounted manner, that is, the first chip 141 is an inverted chip, and the second chip 142 is a forward-mounted chip; and each of the first chip 141 and the second chip 142 is electrically connected to the substrate 110, which may mean a direct electrical connection or an indirect electrical connection. Therefore, the first plastic package body 130 has a stable supporting effect on the second type chip 140, and the whole structure is stable and is not easy to collapse or collapse; and through setting up step portion 133, reduce the difference in height of two adjacent two-layer second class chip 140 of piling up, the routing is easier, and electric connection is stable, and whole encapsulation size is less, compact structure, small, practices thrift the encapsulation raw and other materials, reduce cost. It should be noted that the electrical connection herein may be a direct electrical connection or an indirect electrical connection.
Referring to fig. 3, referring to fig. 1, the first plastic package body 130 includes a top surface 136, a bottom surface 137 and an outer peripheral surface 138 located between the top surface 136 and the bottom surface 137, the bottom surface 137 is connected to the substrate 110, the top surface 136 and the bottom surface 137 are oppositely disposed, the outer peripheral surface 138 is provided with a plurality of steps 133, the plurality of steps 133 may be circumferentially disposed, but not limited to front, rear, left and right side surfaces, in order to improve chip integration, the steps 133 may be disposed in a plurality of layers between the top surface 136 and the bottom surface 137 of the first plastic package body 130, and the plurality of layers have corresponding height differences, so as to shorten a wire bonding distance of the normal chip, make wire bonding easier, and make connection more reliable. Fig. 3 shows only one step 133, and of course, the second type chip 140 may be stacked on the top surface 136, so the top surface 136 may be regarded as one step 133. It should be noted that the step 133 in the same layer at the same height may be a continuous annular boss, or may be one boss or a plurality of bosses arranged at intervals in the circumferential direction. If the annular boss is a continuous annular boss, a set of stacked first chips 141 and second chips 142 may be disposed thereon, or a plurality of sets of stacked first chips 141 and second chips 142 may be disposed at intervals. In the case of one pad, one or more sets of the first chip 141 and the second chip 142 may be stacked on the pad. If the plurality of bosses are provided at intervals in the circumferential direction, a set of stacked first core pieces 141 and second core pieces 142 may be provided on each boss, respectively, and this is not particularly limited. In this embodiment, it can be understood that two bosses 1301 are disposed on the same step portion 133, and are respectively located on the left and right sides of the first plastic package body 130. A set of stacked first chips 141 and second chips 142 are respectively disposed on each of the bosses 1301 on both sides, and the first chips 141 and the second chips 142 on both sides are mounted in a similar manner. Optionally, the first chip 141 and the second chip 142 may also be disposed in a normal mounting manner, and are electrically connected to the substrate 110 in a wire bonding manner.
Optionally, each step portion 133 is provided with a conductive pillar 131 penetrating through the step portion 133, one end of the conductive pillar 131 is electrically connected to the substrate 110, and the other end of the conductive pillar is exposed out of the step portion 133 and electrically connected to the first chip 141. In order to shorten the length of the conductive post 131, the conductive post 131 is disposed perpendicular to the substrate 110 as much as possible. Optionally, the mounting surface 135 of each step 133 on which the first chip 141 is mounted is a plane, so as to improve the mounting stability of the first chip 141, and the mounting surface 135 is substantially parallel to the substrate 110, so that the height of the conductive pillar 131 is substantially equal to the distance from the mounting surface 135 to the substrate 110. Therefore, the stability of the first chip 141 in mounting is facilitated, the stability of the electrical connection between the first chip 141 and the substrate 110 is improved, and the reduction of the whole package size is facilitated.
Referring to fig. 4, in the present embodiment, the first chip 141 is a flip chip, the first chip 141 is provided with a first pad 151 and a second pad 152, the first pad 151 is relatively close to the center of the first plastic package body 130, and the second pad 152 is relatively close to the edge of the first plastic package body 130. The first pads 151 are electrically connected to the substrate 110 through the conductive pillars 131, and the second pads 152 are electrically connected to the substrate 110 through the conductive pillars 131; alternatively, when the number of the step parts 133 is plural, the second pad 152 on the step part 133 of the upper layer is connected to the second chip 142 on the step part 133 of the adjacent lower layer. Optionally, the first pad 151 and the second pad 152 are disposed in a bump, similar to a metal solder ball, and the bump structure is connected to the conductive pillar 131 by using the eutectic soldering principle, and the material of the bump structure may include, but is not limited to, a gold ball, a solder ball, an alloy ball, a copper ball, etc., as long as the eutectic soldering principle is satisfied. The transmission rate and the transmitted signal quality of the chip can be greatly improved through the salient point structure, so that the influence of wire bonding on the chip and the transmission of the wire arc on the signal and the rate is solved under the condition of the same chip.
The second chip 142 is a front chip, and the second chip 142 is provided with a third pad 153, a fourth pad 154 and a fifth pad 155 at intervals, wherein the fourth pad 154 is disposed between the third pad 153 and the fifth pad 155, and the third pad 153 is further away from the center of the first plastic package body 130 relative to the fifth pad 155, that is, the third pad 153 is disposed on the outer side of the step portion 133 relative to the fifth pad 155, that is, on the side away from the center of the first plastic package body 130. The third pad 153 is electrically connected to the substrate 110 by the wire 146, or, when the number of the step parts 133 is multiple, the third pad 153 on the step part 133 of the upper layer is electrically connected to the fourth pad 154 of the second chip 142 on the step part 133 of the adjacent lower layer by the wire 146. The fourth pad 154 is electrically connected to the third pad 153 of the second chip 142 on the step 133 of the adjacent upper layer by the wire 146, and the fifth pad 155 is soldered to the second pad 152 of the first chip 141 on the step 133 of the upper layer. It is understood that the flip chip in this embodiment is provided with two pads, i.e., a first pad 151 and a second pad 152; the front mounted chip in this embodiment is provided with three pads, i.e., a third pad 153, a fourth pad 154, and a fifth pad 155.
In this embodiment, the top surface 136 can be a step 133 on which two sets of the second type chips 140, i.e., two sets of the first chip 141 and the second chip 142, which are stacked, are disposed. In other alternative embodiments, if the number of the second chips 140 to be plastically packaged is small, only one set of stacked first chips 141 and second chips 142 may be disposed on the top surface 136 according to actual needs; alternatively, the two sets of the first chip 141 and the second chip 142 on the top surface 136 may be omitted. Correspondingly, if the number of the second chips 140 to be plastically packaged in the actual product is large, three, four or more groups of the first chips 141 and the second chips 142 may be arranged on the top surface 136; alternatively, on the basis of fig. 4, a first chip 141 may be further flip-chip mounted on the top surface 136, and the first pads 151 and the second pads 152 of the first chip 141 are respectively connected to the substrate 110 through the conductive pillars 131, as shown in fig. 5, which is not limited in this respect.
Further, in order to integrate more chips on one substrate 110, a third chip 145 is further disposed on the periphery of the first plastic package body 130 on the substrate 110, with reference to fig. 1, the third chip 145 is attached to the substrate 110 in a normal mounting manner, which is equivalent to a normal mounting chip, a third pad 153, a fourth pad 154 and a fifth pad 155 are disposed at an interval on one side of the third chip 145 away from the substrate 110, the third pad 153 of the third chip 145 is connected to the substrate 110 by a wire bonding manner, and the wire 146 used for wire bonding includes, but is not limited to, a gold wire, a copper wire, a silver wire or an alloy wire, and the like, which is not specifically limited herein. Alternatively, after the third chip 145 is mounted, a surface of the third chip 145 away from the substrate 110 is flush with the mounting surface 135 of the step 133 of the layer adjacent to the substrate 110, and the first chip 141 on the step 133 of the layer adjacent to the substrate 110 is flip-mounted on the step 133 and the third chip 145 at the same time. The first pads 151 of the first chip 141 on the one-level step 133 adjacent to the substrate 110 are electrically connected to the substrate 110 through the conductive posts 131, and the second pads 152 are soldered to the fifth pads 155 of the third chip 145. The second chip 142 on the step 133 of the layer adjacent to the substrate 110 is mounted on the first chip 141 at a side away from the step 133 of the layer, and the third pad 153 of the second chip 142 and the fourth pad 154 of the third chip 145 are electrically connected by a wire 146 in a wire bonding manner. This realizes the connection between the second chip 140 and the third chip 145 on the step 133 adjacent to the substrate 110.
It should be noted that, if the step 133 adjacent to the substrate 110 is defined as a first step and faces upward in the direction away from the substrate 110, there may be a second step, a third step, a fourth step, etc. stacked upward in this order, and each step is provided with a flip chip and a normal chip. Therefore, the height of each routing is only the height difference between the step of the upper layer and the step of the lower layer, and routing is easy and connection is reliable. In the conventional stacking technology, wire bonding needs to be performed between the top chip and the substrate 110, which is high in wire bonding height and difficulty, and bridging or wire breaking is likely to occur in connection. The "upper step" and "lower step" in the present specification can be understood as, for example, the upper step of the second layer is the third step, and the lower step of the fourth layer is the third step. In addition, the first chip 141, the second chip 142, and the third chip 145 mentioned in this embodiment may be the same chip or different chips, and for convenience of description, they are classified as "first, second, third", and the like, and are not specifically limited herein.
Further, a second plastic package body 150 is disposed on a side of the substrate 110 close to the first type chip 120, and the second plastic package body 150 is disposed on the substrate 110, and is used for encapsulating the first plastic package body 130 and the second type chip 140, and protecting the second type chip 140 and the first plastic package body 130. In addition, solder balls 160 are disposed on a side of the substrate 110 away from the second plastic package body 150 for electrically connecting with other circuit boards.
In the multilayer chip stacking structure 100 provided by the embodiment of the invention, the first plastic package body 130 is used as a support, and one or more layers of step parts 133 are arranged on the first plastic package body 130 to stack a plurality of second chips 140, so that the chip integration level is improved. Adopt the flip-chip to set up first chip 141 and just adorn the mode and set up second chip 142 on every layer of step portion 133 respectively, the structure is compacter, and the whole encapsulation size of product is little, and the routing is easier, stable in structure, reduction encapsulation cost.
Referring to fig. 6, an embodiment of the invention provides a method for manufacturing the multilayer chip stack structure 100, which mainly includes the following steps:
s100: the first type chip 120 is mounted on the substrate 110. Referring to fig. 7, a wafer (wafer) is diced along dicing streets by a laser or a diamond to form individual first type chips 120, i.e., control chips, a linear flowable film (FOW film) is attached to the back surfaces of the control chips, the control chips are attached to the surface of the substrate 110 by silver paste, and the FOW film is cured by baking to fix the control chips on the surface of the substrate 110. The control chip is connected to the substrate 110 by wire bonding using wires 146 such as copper wires, alloy wires, or gold wires.
S200: a first molding compound 130 for molding the first type of chip 120 is formed. The connected control chip is protected by a plastic packaging machine, and a first plastic packaging body 130 is formed on one side of the substrate 110 close to the control chip. The first plastic package body 130 can be formed by injection molding or printing filling, and is not limited in this respect.
S300: a step portion 133 is disposed on the first plastic package body 130. Referring to fig. 8 and 9, a step portion 133 is disposed on the first plastic package body 130 by a laser grooving method. In detail, the protective film 161 is used to protect the surface of the substrate 110 on the side where the control chip is disposed, so as to prevent the surface of the substrate 110 from being contaminated during the groove opening process, and then the laser is used to open the groove on the first plastic package 130 to form the step 133. Then, a through hole is formed in the mounting surface 135 of the step portion 133, the through hole penetrates from the mounting surface 135 of the step portion 133 to the surface of the substrate 110 to expose a solder joint on the surface of the substrate 110, and the conductive post 131 is formed by filling a conductive material, such as conductive paste, gold, silver paste, copper paste, or tin, in the through hole, so that the conductive post 131 is connected to the solder joint on the surface of the substrate 110. Finally, the protective film 161 is removed. It should be noted that the number and size of the stepped portions 133 are determined according to the number and size of the second type chips 140 to be mounted actually, a through hole is formed in the mounting surface 135 of each stepped portion 133, and a conductive material is filled in the through hole to form the conductive pillar 131, so that one end of the conductive pillar 131 is electrically connected to the substrate 110 by a solder joint, and the other end of the conductive pillar 131 is used for electrically connecting to a flip chip (one of the second type chips 140) mounted on the stepped portion 133.
S400: the second type chip 140 is mounted on the step 133. Referring to fig. 10, in the present embodiment, the second type chip 140 includes a first chip 141 and a second chip 142, and a third chip 145 is further disposed on the substrate 110; the first chip 141 is a flip chip, and the second chip 142 and the third chip 145 are normal chips. The bottom of the flip chip is provided with first pads 151 and second pads 152, and the top of the front mounted chip is provided with third pads 153, fourth pads 154, and fifth pads 155.
Alternatively, the third chip 145 is first attached to the surface of the substrate 110 by using a silver paste, and the third chip 145 is fixed on the substrate 110 by baking the silver paste; the third pad 153 of the third chip 145 is electrically connected to the substrate 110 by wire bonding.
Referring to fig. 11, a first chip 141 and a second chip 142 are mounted on a step 133 (first step) adjacent to the substrate 110. The first chip 141 is in a flip-chip manner, and the first pads 151 of the first chip 141 are soldered to the conductive pillars 131 and electrically connected to the substrate 110 through the conductive pillars 131; the second pad 152 of the first chip 141 is soldered to the fifth pad 155 of the third chip 145, and is electrically connected to the substrate 110 through the third chip 145. The second chip 142 is mounted on the first chip 141 in a normal mounting manner, the second chip 142 is stacked and attached to one side of the first chip 141, which is far away from the step portion 133, the second chip 142 is fixed on the first chip 141 by baking silver paste, and the third pad 153 of the second chip 142 is electrically connected with the fourth pad 154 of the third chip 145 in a routing manner. In this way, the mounting of the first chip 141 and the second chip 142 on the step 133 of the layer adjacent to the substrate 110 is completed.
The first chip 141 and the second chip 142 are successively stacked on the adjacent upper step 133 (second step). Referring to fig. 12, if the step 133 adjacent to the substrate 110 is regarded as a first step, the step above the first step is regarded as a second step, and in the structure shown in fig. 12, since only one step 133 is shown, the top surface 136 of the first plastic package body 130 can be regarded as the second step, that is, the first chip 141 is flip-chip mounted on the top surface 136 of the first plastic package body 130, and the first pad 151 of the first chip 141 is soldered to the conductive pillar 131 and electrically connected to the substrate 110 through the conductive pillar 131; the second pad 152 of the first chip 141 is soldered to the fifth pad 155 of the second chip 142 on the step 133 of the next layer, and is electrically connected to the substrate 110 through the second chip 142 of the next layer. The second chip 142 on the top surface 136 is mounted on the first chip 141 on the layer far from the first plastic package body 130 by a front mounting method using silver paste, the second chip 142 is fixed on the first chip 141 by baking the silver paste, and the third bonding pad 153 of the second chip 142 on the top surface 136 is electrically connected with the fourth bonding pad 154 of the second chip 142 on the next layer by a wire bonding method.
If the step 133 has multiple layers, similarly, the first chip 141 and the second chip 142 are sequentially stacked on the step 133 on the upper layer, and in the first chip 141 on the upper layer, i.e., the flip chip, the first pad 151 is electrically connected to the substrate 110 through the conductive pillar 131, and the second pad 152 is connected to the fifth pad 155 of the second chip 142 on the lower layer. In the second chip 142, i.e., the normal chip, the third pad 153 is electrically connected to the fourth pad 154 of the next second chip 142 by wire bonding, the fourth pad 154 is electrically connected to the third pad 153 of the previous second chip 142 by wire bonding, and the fifth pad 155 is soldered to the second pad 152 of the previous first chip 141. The stacking manner of each layer is the same as the above steps, and detailed description thereof is omitted.
S500: a second plastic package body 150 is formed which plastically packages the second type chip 140 and the first plastic package body 130. Referring to fig. 13, a second molding compound 150 is disposed on a side of the substrate 110 where the second type chips 140 are disposed, so as to protect the stacked second type chips 140. The second plastic package body 150 can be formed by injection molding or printing and filling, and is not limited in this respect.
Finally, solder balls 160 are implanted on the back side of the substrate 110, i.e., the side of the substrate 110 away from the first plastic package body 130 and the second plastic package body 150. Printing characters on the second plastic package body 150, and engraving required characters on the surface of the second plastic package body 150 by using laser; cutting the plastic-packaged product into single pieces by using a cutting knife; and then putting the cut single products into a tray, and packaging and delivering the products out of the warehouse.
In the multilayer chip stacking method provided by the embodiment of the invention, the first type of chip 120 is mounted on the substrate 110, and the first plastic package body 130 for protecting the first type of chip 120 is formed; a step part 133 is arranged on the first plastic package body 130 and used for mounting a second type chip 140; each step 133 is provided with a conductive column 131 connected with the substrate 110, each step 133 is provided with a forward-mounted chip and a flip chip, the bottom of the flip chip is provided with a first pad 151 and a second pad 152, the first pad 151 is used for being connected with the substrate 110 through the conductive column 131, and the second pad 152 is used for being connected with a forward-mounted chip on the next layer; the front chip is provided with a third bonding pad 153, a fourth bonding pad 154 and a fifth bonding pad 155, wherein the third bonding pad 153 is used for wire bonding with the substrate 110 or the front chip on the next layer, the fourth bonding pad 154 is used for wire bonding with the front chip on the previous layer, and the fifth bonding pad 155 is used for connecting with the flip chip on the previous layer. The structure is compact and stable, the routing is easy, the electric connection is reliable, fewer packaging materials are used, the cost is reduced, the overall packaging size of the product is smaller, and the chip integration level is high.
In summary, the multilayer chip stacking structure 100 and the multilayer chip stacking method provided by the embodiment of the invention have the following beneficial effects:
according to the multilayer chip stacking structure 100 and the multilayer chip stacking method, the first plastic package body 130 is used for supporting, the chip stacking strength is improved, the step part 133 is formed on the first plastic package body 130, the arrangement position and the number of the step part 133 are determined according to actual conditions, the stacking of more chips can be achieved, and the overall packaging size of a product is reduced. The conductive posts 131 are formed by opening through holes on the first plastic package body 130 and filling conductive material in the through holes, so as to electrically connect the flip chip and the substrate 110. The first pad 151 and the second pad 152 of flip chip bottom adopt the bump structure, utilize the eutectic welding principle, reach flip chip and lead electrical pillar 131 and link to each other, can promote chip transmission rate and signal transmission quality by a wide margin. The novel multilayer chip stacking structure and the stacking method adopted in the embodiment can realize the integration of multiple chips on one substrate 110, improve the chip integration level, reduce the packaging process, reduce the required packaging materials and reduce the packaging cost.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (8)

1. A multilayer chip stacking structure is characterized by comprising a substrate, a first type chip, a first plastic package body and a plurality of second type chips;
the first type of chip is arranged on the substrate and electrically connected with the substrate, and the first plastic package body encapsulates the first type of chip;
the first plastic package body is provided with a step part, the plurality of second chips comprise a first chip and a second chip, the first chip and the second chip are stacked on each step part, the first chip is arranged on the step part, and the second chip is arranged on one side, far away from the step part, of the first chip in a forward mounting mode; and the first chip and the second chip are both electrically connected with the substrate;
a third bonding pad, a fourth bonding pad and a fifth bonding pad are arranged on one side, far away from the first chip, of the second chip, and the third bonding pad is electrically connected with the substrate through a wire, or the third bonding pad is electrically connected with the second chip on the step part of the next layer through a wire;
the fourth bonding pad is electrically connected with the second chip on the step part of the previous layer through a wire, and the fifth bonding pad is electrically connected with the first chip on the step part of the previous layer.
2. The stacked multilayer chip structure according to claim 1, wherein the first chip is flipped, and the step portion has a conductive pillar penetrating through the step portion, one end of the conductive pillar is electrically connected to the substrate, and the other end of the conductive pillar is exposed out of the step portion and electrically connected to the first chip.
3. The multi-layered chip stacked structure according to claim 2, wherein a first pad and a second pad are provided on the first chip, the first pad is electrically connected to the substrate through the conductive post, and the second pad is electrically connected to the substrate through the conductive post, or the second pad is connected to the second chip on the step portion of the next layer.
4. The multi-layered chip stacking structure of claim 1, wherein a third chip is further disposed on the substrate, and the third chip is located at an outer periphery of the first molding compound; and the first chip on the step part of the layer adjacent to the substrate is reversely arranged on the step part and the third chip, and the third chip is electrically connected with the substrate through a wire.
5. The stacked multilayer chip structure according to any one of claims 1 to 4, further comprising a second molding compound disposed on the substrate for encapsulating the first molding compound and the second type of chip.
6. A method of stacking a plurality of chips, comprising:
mounting a first type chip on a substrate;
forming a first plastic package body for plastically packaging the first type of chips;
arranging a step part on the first plastic package body;
mounting a second chip on the step part; wherein the second type of chip comprises a first chip and a second chip; the first chip and the second chip are stacked on the step part, the first chip is arranged on the step part, and the second chip is arranged on one side, far away from the step part, of the first chip in a forward mounting mode; the second chip is electrically connected with the substrate through a lead;
a third bonding pad, a fourth bonding pad and a fifth bonding pad are arranged on one side, far away from the first chip, of the second chip, and the third bonding pad is electrically connected with the substrate through a wire, or the third bonding pad is electrically connected with the second chip on the step part of the next layer through a wire;
the fourth bonding pad is electrically connected with the second chip on the step part of the previous layer through a wire, and the fifth bonding pad is electrically connected with the first chip on the step part of the previous layer.
7. The method of claim 6, wherein the step of providing a step on the first plastic package body comprises:
a through hole is formed in the step part;
and filling a conductive material in the through hole to form a conductive column so that the second type of chip on the step part is electrically connected with the substrate through the conductive column.
8. The method of claim 7, wherein the step of mounting a second type of die on the step comprises:
the first chip is arranged in a flip-chip manner;
the first chip is provided with a first bonding pad and a second bonding pad, the first bonding pad is electrically connected with the substrate through the conductive column, and the second bonding pad is electrically connected with the substrate through the conductive column, or the second bonding pad is connected with the second chip on the step part of the next layer.
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