201005885 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種封裝結構及其方法’特別是有關於—種將多個晶 粒堆疊在凹槽之基板内之封装結構及其封裝方法。 【先前技術】 在各種應用中，將多個晶粒封裝在單一一個積體電路結構内是值得需 Φ $考量的—種封裝結構。此種封裝結構會關元件在兩個晶粒上的完整 性。此種晶粒料關係由電子元件是否能夠封裝成單——個封裝結^所 引起。此外，此種晶粒堆#的關也會造舰子元倾封裝結構不相容性 提高Μ物’在兩個不同尺寸大小之晶粒上狀件可齡產生不同電壓的 須求。 另外’將兩個尺寸大小相同的晶粒封裝在一個封裝結構且兩個晶粒經 由共用的設置與外界連接…般來說，晶粒之上表面包含複數個連接端點 用以與外部凡件電性連接。當複數個晶粒封裝成一個封裝結構時，每一個 自粒可以只接觸到晶粒的—面，因此將多個錄封裝在—個封裝結構令是 _ 一項很重要的課題。 【發明内容】 蓉於以上的_，轉_主要目的在於_具有凹槽之基板進行多 晶粒之堆疊藉以縮小封裝結構之尺寸。 本發明之另—目的在於個基油之導電柱做為m連接元件，用以 電性連接多數個封裝結構，以形成一多重堆叠結構。 一根據上述^目的’本發關露—種半導體堆疊結構包括基板，具 及#面且具有一凹槽設置在基板之正面内及複數個貫孔在基板 201005885 之兩側；一導電層，設置在複數個貫孔内以形成複數個導電柱；一第一晶 粒’具有-主動面及-背面，且將主動面朝上並藉由第—黏著層將第一晶 粒之背面固接在基板之凹槽之一表面上；複數條第一導線，係用以電性連 接第-晶粒及基板之凹槽之表面；一第二黏著層，係包覆駿第一導線及 第一晶粒；第二晶粒，具有一主動面及一背面，且將主動面朝上並藉由第 二黏著層與第一晶粒連接，且第二黏著層係包覆部份第一導線；複數條第 二導線，用以電性連接第二晶粒及基板之凹槽之表面；一封裝體，用以包 覆第一晶粒、第二晶粒、複數條第一導線、複數條第二導線及基板之部份 Φ 正面；及複數個導電元件，係設置在曝露於基板之正面之複數個導電柱之 一表面上。 根據上述之半導體堆疊結構，本發明還揭露一種形成半導體堆疊結構 之方法，其包括:提供一基板，具有一正面及一背面且於正面上具有一凹槽 及於基板之兩側内具有複數個貫孔；形成一導電層在複數個貫孔内以形成 複數個導電柱；貼附一第一晶粒在基板之凹槽内，係將第一晶粒之主動面 朝上，且藉由第一黏著層固接在凹槽之部份表面上；形成複數個第一導線， 係電性連接第一晶粒之主動面及基板之凹槽之表面；貼附一第二晶粒，係 藝將第二晶粒之主動面朝上且藉由第二黏著層與第一晶粒固接，其中第二黏 著層用以包覆部份第一導線及第一晶粒之主動面；形成複數條第二導線， 係電性連接第二晶粒之主動面及基板之凹槽之表面；形成一封裝體，係用 以包覆第一晶粒、第二晶粒、複數條第一導線、複數條第二導線及基板之 部份正面；及形成複數個導電元件在基板之正面之已曝露之複數個導電柱 之一表面上。 本發明另外揭露一種多重堆疊結構，其包括:一基板，具有一正面及一 背面且於正面上具有一凹槽及複數個貫孔在基板之兩側内；一導電層，設 置在複數個貫孔内以形成複個導電柱；一第一晶粒，具有一主動面及一背 面，且將主動面朝上並藉由第一黏著層將第一晶粒之背面固接在基板之凹 7 201005885 槽之-表面上；複數條第一導線，係用以電性連接第一晶粒及基板之凹槽 •之表面；-第二黏著層’係包覆部份H線及第—晶粒；第二晶粒，具 有-主動面及-背面，且將主動面朝上並藉由第二黏著層與第一晶粒連 接，且第二黏著層聽覆部份第一導線；複數條第二導線，制以電性連 接第二晶粒及基板之該凹槽之表面；—封裝體，用以包覆第—晶粒、第二 晶粒、複祕第-導線、複數條第二導線及基板之部份正面；複數個導電 元件，係設置在曝露於基板之正面之複數個導電柱之一表面上以形成一第 -半導趙封裝結構；及-堆叠結構，係將與第—晶粒堆疊結構具有相同一 〇 、结構之一第二晶粒堆墨結構之複數個導電元件電性連接至第-晶粒堆曼結 構之複數個導電柱之一導電端點上。 根據上述之彡重堆叠結構，本發明另揭露—郷成彡重堆要結構之方 法，其包括：提供一基板’具有一正面及一背面，且於正面上具有一凹槽及 在基板之兩側具有複數個貫孔；形成一導電層在複數個貫孔内以形成複數 個導電柱，貼附-第-晶粒在基板之凹槽内，係將第一晶粒之一主動面朝 上且藉由-第-黏著層固接在凹槽之部份表面上；形成複數條第一導線， 係電性連接第-晶粒之主動面及基板之凹槽之表面；貼附一第二晶粒係 將第二晶粒之-主動面朝上且藉由一第二黏著層與第一晶粒固接，其中第 二黏著利吨覆部份複數條第-導線及第—晶粒之絲面；形成複數條 第二導線’係電性連接第二晶粒之主動面及基板之凹槽之表面；形成一封 裝體，係用以包覆第-晶粒、第二晶粒、複數條[導線、複數條第二導 線及基板之雜正面；形毅數料電树在基板之正蚊㈣露之複數 個導電柱之-表面上’以形成-第一晶粒堆叠結構；及堆叠與第一封裝結 構具有相同結構之-第二晶粒堆叠結構，係將第二晶粒堆叠結構之複數個 導電元件電性連接至第一晶粒堆疊結構之複數個導電柱之一導電端點上。 有關本發_賴與實作，賊合圖轉最佳實細詳細說明如下。 (為使對本發_目的、構造、特徵、及其功能有進—步的瞭解，兹配合 8 201005885 實施例詳細說明如下。） 【實施方式】 ，本發明在此雌討的方向為—種雖賴及其封裝方法 ，將多數個晶 粒形成在基板之-凹槽以降低封裝結構之尺寸大小，然後進行封裝的方 法為了月b徹底地瞭解本發明’將在下列的描述中提出詳盡的步驟及其組 成=二也本發明的施行並未限定晶粒封褒的方式之技藝者所熟習的特 殊細節。另-方面’眾所周知的晶粒形成方式以及晶粒薄化等後段製程之 參系細步驟並未描述於細節中，以避免造成本發明不必要之限制。然而，對 於本發明峨佳實則會詳細描述如下，然而除了這些詳細描述之外， 本發明還心廣魏贿在無的實關巾，且本發_侧不受限定， 其以之後的專利範圍為準。 第1圖至第7圖係根據本發明所揭露之技術，表示形成晶粒堆叠之封 裝結構之各步驟示意圖。首先，請參考第1圖，係提供具有一凹槽Η之一 基板10 ’其中凹槽12的形成方法係顧__般半導體製程，其包括先提供 具有-正面(未在圖中表示)及一背面(未在圖中表示)之基板ι〇 ;接著，形成 ❷—圖案化之光阻層(未在圖中表示）；織，執行-顯影及_步驟，係移除 部份基板ίο ’使得在基板10之鄰近於中央部份形成一凹槽12。在此，基 板10之材料可以是已經酉己置好線路佈局之PCB電路板或是金屬基ai foil)。 接著，再將另-圖案化之光阻層(未在圖中表示)形成在具有凹槽i2之 基板10上；然後進行顯影及餘刻，使得在基板10之具有凹槽12之兩側形 成複數個貫穿孔102,如第2圖所示；緊接著，在剝除圖案化之光阻層之後， 在每-貫穿孔1G2内’選擇適當的導電材料_成導電柱2()，其導電柱π 形成的方法包括將導電材料，以電鍍(plating)的方式填充入複數個貫穿孔 102内，並使每-導電柱20之上、下表面裸露於封裝體上、下表面的兩端， 9 201005885 分別形成第-導電端點2〇2及第三導電端點2〇4，如第3圖所示。 _ 接著請參考第4圖，絲示將一第一晶粒形成在基板之凹槽上之示意 圖。在第4圖t ’係提供—第―晶粒4()，其具有—主動面及—背面，且在 主動面上有複數個焊塾402 ;接著，將第一晶粒4〇之主動面朝上並藉由形 成在基板ίο之凹槽12表面上之第一黏著層％，將第一晶粒3〇之背面固著 在基板10之凹槽12之表面上。在另一實施例中，第一黏著層3〇可先形成 在第曰曰粒40之背面，然後再貼附至基板1〇之凹槽之表面上使得第 明粒4〇藉由第_黏著層％固著在基板1()上。在此實施例中第一黏著 層30的材料係為二階段熱固卵，φ然後，利用打線接合㈣_㈣ 的方式，將複數條第-導線5〇的—端形成在第—晶粒⑽的主動面之複數 個;墊402上其複數條第一導線5〇之另一端係形成在基板之凹槽η 之表面上，用以電性連接基板10與第一晶粒40。 緊接著’請參考第5 ®，係表示將第二晶粒堆叠在第一晶粒上之示意 圖。在第5圖中，係先提供—第二晶粒42，其具有一主動面及一背面且 於主動面上具有複數個焊塾似2 ;接著，第二晶粒幻之主動面朝上，並藉 由第一黏著層32貼附在第一晶粒*上，以形成一晶粒堆要結構，在此 參 第二黏著層32同時包與第-晶粒40電性連接之部份複數條第一導線 50以及覆蓋住第一晶粒4〇之主動面。在此，第二黏著層32之材料可以是 FOW。同樣繼續參考第5圖，係打線接合的方式將複數條第二導線 52之端形成在第二晶粒42之主動面之複數個谭塾上以及另一端係形 成在基板1G之具有凹槽12之表面上，且與軸在基板10之凹槽12表面 f之複數條第-導線4G電性分離。在此實施例中，其第—晶粒奶與第二 晶粒42可叹具有相同尺寸及魏之晶粒’或者是具有不同尺寸及功能之 晶粒。 緊接著’參考第6圖’係表示形成一封裝體以包覆晶粒堆疊結構之示 意圖。在第6圖中，係將一高分子材料(未在圖中表示)注入至基板1〇之凹 201005885 槽12内。接著’對高分子材料進行一烘烤程序(bake p叫使高分子材 料固化以形成-封裝體60叫覆住第—黏著層3q、第—晶粒⑽、第二黏 著層32、第二晶粒42、複數條第一導線5〇以及複數條第二導線52，且覆 蓋在部份的基板H)之正面r在此實施射，高分子娜可以是轉、環 氧樹脂、丙稀酸（acrylic)、及苯環丁烯（BCB)等材料。201005885 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure and a method thereof, and more particularly to a package structure and package for stacking a plurality of crystal grains in a substrate of a groove method. [Prior Art] In various applications, it is worthwhile to package a plurality of dies in a single integrated circuit structure. This package structure will shut down the integrity of the component on both dies. This kind of grain material relationship is caused by whether the electronic component can be packaged into a single package. In addition, the closeness of such a grain stack # also creates a ship's sub-package structure incompatibility, which increases the requirement for different voltages in the two different sizes of the die. In addition, 'two sizes of the same size die are packaged in one package structure and the two crystal grains are connected to the outside through a common arrangement... Generally, the upper surface of the die includes a plurality of connection terminals for external parts. Electrical connection. When a plurality of dies are packaged into a package structure, each self-grain can only contact the face-to-face of the die, so packaging a plurality of packages in a package structure is an important issue. SUMMARY OF THE INVENTION The above-mentioned _, _ _ main purpose is to _ grooved substrate for multi-die stack to reduce the size of the package structure. Another object of the present invention is to provide a conductive member of a base oil as an m-connecting member for electrically connecting a plurality of package structures to form a multi-stack structure. According to the above-mentioned object, the semiconductor stack structure comprises a substrate having a #-plane and a recess disposed in the front surface of the substrate and a plurality of through-holes on both sides of the substrate 201005885; a conductive layer disposed Forming a plurality of conductive pillars in a plurality of through holes; a first die 'having an active face and a back face, and bringing the active face up and fixing the back surface of the first die by the first adhesive layer a surface of one of the grooves of the substrate; a plurality of first wires for electrically connecting the surfaces of the first die and the groove of the substrate; and a second adhesive layer covering the first wire and the first crystal a second die having an active surface and a back surface, and having an active surface facing upward and connected to the first die by a second adhesive layer, and the second adhesive layer coating a portion of the first wire; a second wire for electrically connecting the surface of the second die and the groove of the substrate; a package for covering the first die, the second die, the plurality of first wires, and the plurality of second a portion of the wire and the substrate Φ front side; and a plurality of conductive elements are disposed on the exposed One of a plurality of conductive columns on the front side of the substrate. According to the above semiconductor stack structure, the present invention also discloses a method of forming a semiconductor stacked structure, comprising: providing a substrate having a front surface and a back surface and having a recess on the front surface and having a plurality of sides on the substrate a through hole; forming a conductive layer in the plurality of through holes to form a plurality of conductive columns; attaching a first die in the groove of the substrate, the active face of the first die facing upward, and by An adhesive layer is fixed on a part of the surface of the groove; a plurality of first wires are electrically connected to the active surface of the first die and the surface of the groove of the substrate; and a second die is attached The active surface of the second die is facing upward and is fixed to the first die by the second adhesive layer, wherein the second adhesive layer is used to cover a portion of the first wire and the active surface of the first die; a second wire electrically connecting the active surface of the second die and the surface of the groove of the substrate; forming a package for covering the first die, the second die, the plurality of first wires, a plurality of second wires and a portion of the front surface of the substrate; and forming a complex Conductive elements of the front board has a plurality of exposed surfaces on one of the conductive posts. The present invention further discloses a multi-stack structure comprising: a substrate having a front surface and a back surface and having a recess and a plurality of through holes on the front side of the substrate; a conductive layer disposed in the plurality of layers Forming a plurality of conductive pillars in the hole; a first die having an active surface and a back surface, and having the active surface facing upward and fixing the back surface of the first die to the recess of the substrate by the first adhesive layer 201005885 The groove-surface; a plurality of first wires are used to electrically connect the first die and the surface of the substrate; the second adhesive layer is a portion of the H-line and the first die a second die having an active surface and a back surface, and having an active surface facing upward and connected to the first die by a second adhesive layer, and the second adhesive layer audibly covering a portion of the first wire; a second wire electrically connected to the surface of the second die and the groove of the substrate; the package body for covering the first die, the second die, the secretive first wire, and the plurality of second wires And a portion of the front surface of the substrate; the plurality of conductive elements are disposed on the front side of the substrate a plurality of conductive pillars on a surface thereof to form a first-semiconductor package structure; and a stack structure having the same structure as the first-grain stack structure and a second crystal grain stacking structure The conductive elements are electrically connected to one of the plurality of conductive pillars of the first-grain stack structure. According to the above-described stacking structure, the present invention further discloses a method for constructing a structure, comprising: providing a substrate having a front surface and a back surface, and having a recess on the front surface and two on the substrate The side has a plurality of through holes; forming a conductive layer in the plurality of through holes to form a plurality of conductive columns, and attaching the -first grains in the grooves of the substrate, the active side of the first die facing upward And fixing a plurality of first wires by the first-adhesive layer; forming a plurality of first wires electrically connected to the active surface of the first die and the surface of the groove of the substrate; attaching a second The die attaches the active surface of the second die upward and is fixed to the first die by a second adhesive layer, wherein the second adhesive portion covers a plurality of the first wire and the first die a plurality of second wires are electrically connected to the active surface of the second die and a surface of the groove of the substrate; forming a package for coating the first die, the second die, and the plurality Strips [wires, multiple strips of wires and the front side of the substrate; the shape of the electric tree on the substrate of the positive mosquito (four) dew a plurality of conductive pillars on the surface to form a first die stack structure; and stacking a second die stack structure having the same structure as the first package structure, which is a plurality of second die stack structures The conductive element is electrically connected to one of the plurality of conductive pillars of the first die stack structure. Regarding the hair _ Lai and the implementation, the thief map is best described in detail below. (In order to make the understanding of the purpose, structure, features, and functions of the present invention, the following is a detailed description of the embodiment of the present invention.) [Embodiment] The present invention is in the direction of the female Lay and its packaging method, a plurality of grains are formed on the substrate-groove to reduce the size of the package structure, and then the method of packaging is thoroughly understood for the month b. Detailed steps will be presented in the following description. And its composition = two also the specific details of the practice of the present invention that are not familiar to those skilled in the art of grain sealing. The details of the well-known methods of grain formation and the subsequent steps of the grain thinning process are not described in detail to avoid unnecessarily limiting the invention. However, the present invention will be described in detail below, but in addition to these detailed descriptions, the present invention is also in the interest of a solid cover towel, and the present invention is not limited, and its subsequent patent scope Prevail. Figures 1 through 7 are schematic views showing the steps of forming a package structure for a die stack in accordance with the teachings of the present invention. First, please refer to FIG. 1 , which provides a substrate 10 ′ having a recess 其中 wherein the method of forming the recess 12 is a semiconductor process, which includes providing a front surface (not shown) and a backside (not shown) substrate ι; subsequently, a germanium-patterned photoresist layer (not shown); woven, perform-develop and _steps, removing portions of the substrate ίο ' A groove 12 is formed adjacent to the central portion of the substrate 10. Here, the material of the substrate 10 may be a PCB circuit board or a metal-based ai foil which has been placed in a circuit layout. Next, a further patterned photoresist layer (not shown) is formed on the substrate 10 having the recess i2; then development and engraving are performed so as to form on both sides of the substrate 10 having the recesses 12. a plurality of through holes 102, as shown in FIG. 2; next, after stripping the patterned photoresist layer, 'selecting a suitable conductive material _ into a conductive pillar 2 () in each of the through holes 1G2, which is electrically conductive The method of forming the pillar π includes filling a conductive material into a plurality of through holes 102 by plating, and exposing the upper and lower surfaces of each of the conductive pillars 20 to the upper and lower surfaces of the package. 9 201005885 Form the first conductive terminal 2〇2 and the third conductive terminal 2〇4, respectively, as shown in FIG. _ Next, please refer to Fig. 4, which shows a schematic diagram of forming a first die on the groove of the substrate. In Fig. 4, t' is provided - a first die 4 () having an active face and a back face, and having a plurality of solder fillets 402 on the active face; and then, the active face of the first die 4 The back surface of the first die 3 is fixed on the surface of the recess 12 of the substrate 10 by the first adhesive layer % formed on the surface of the recess 12 of the substrate. In another embodiment, the first adhesive layer 3 can be formed on the back surface of the second particle 40 and then attached to the surface of the groove of the substrate 1 such that the first particle is adhered to by the first adhesive. The layer % is fixed on the substrate 1 (). In this embodiment, the material of the first adhesive layer 30 is a two-stage thermosetting egg, and then φ, by means of wire bonding (4)_(4), the end of the plurality of first-wire 5 turns is formed on the first die (10). The other ends of the plurality of first wires 5 are formed on the surface of the recess η of the substrate to electrically connect the substrate 10 and the first die 40. Next, please refer to Section 5 for a schematic diagram of stacking the second die on the first die. In FIG. 5, a second die 42 is provided, which has an active surface and a back surface and has a plurality of solder bumps on the active surface like 2; then, the second die has an active face up, And attaching to the first die* by the first adhesive layer 32 to form a die stack structure, where the second adhesive layer 32 is simultaneously electrically connected to the first die 40. The first wire 50 and the active surface covering the first die 4〇. Here, the material of the second adhesive layer 32 may be FOW. Similarly, referring to FIG. 5, the ends of the plurality of second wires 52 are formed on a plurality of tantalums of the active surface of the second die 42 and the other end is formed on the substrate 1G having the recesses 12 in a wire bonding manner. On the surface, and electrically separated from the plurality of first-wires 4G whose axes are on the surface f of the recess 12 of the substrate 10. In this embodiment, the first grain of the grain and the second grain 42 are sighed by the same size and grain of the grain or by grains having different sizes and functions. Immediately after reference to Fig. 6, there is shown the intention of forming a package to cover the die stack structure. In Fig. 6, a polymer material (not shown) is injected into the recess 1210 of the substrate 1〇. Then, a baking process is performed on the polymer material (bake p is called to cure the polymer material to form - the package 60 is covered with the first adhesive layer 3q, the first die (10), the second adhesive layer 32, and the second crystal The particle 42, the plurality of first wires 5〇, and the plurality of second wires 52, and the front surface r of the portion of the substrate H) is irradiated thereon, and the polymer nano may be a rotating epoxy resin or an acrylic acid ( Acrylic), and benzocyclobutene (BCB) and other materials.
接著’參考第7圖’係表示將複數個導電元件形成在導電柱之一端點 上以完成-縣結構之示意圖在曝露之複數解電柱2q之上表面之第一 端點2〇2以陣列排列方式形成複數個導電元件？〇,例如金屬凸塊㈣^ b㈣) 或是錫球(solder ball)，即完成晶粒堆疊之封裝結構。 此外’於另-實施例中，係、可以將複數個晶粒堆叠之封裝結構彼此堆 叠’如第8圖所示。在第8时，係將與第—晶粒堆叠結構具有相同結構 之第二晶_疊職堆# ’使得第二晶粒堆疊結構之複數料電元件冗與 第-晶粒堆叠結構之導電柱2〇之第二導電端點2〇4電性連接，在此，在導 電柱20之第二導電端.點2〇4與第二晶粒堆疊結構之複數個導電元件^之 間更包含複數轉墊8G ’藉此可職__多重堆疊結構。 雖然本發伽前狀健實施_絲上，财輕㈣限定本發 明’任何熟習相像技藝者，在不脫離本發明之精神和範圍内，當可作些許 之更動與潤飾’因此本發明之專利保護範圍須視本說明書所附之^利 範圍所界定者為準。 【圖式簡單說明】 第1圖至帛7關姆本發麵财之赫’表神成晶轉疊之封 裝結構之各步驟示意圖；及 第8圖係根據本發明所揭露之技術，表示形成多重堆疊結構之示意圖。 201005885 【主要元件符號說明】 - 10基板 102貫孔 12凹槽 20 導電柱 202第一導電端點 204第二導電端點 30第一黏著層 32第二黏著層 40 第一晶粒 402焊墊 ❹ 42第二晶粒 422焊墊 50 第一導線 52 第二導線 60封裝體 70導電元件 80焊墊Next, 'refer to FIG. 7' shows a schematic diagram of forming a plurality of conductive elements on one end of the conductive post to complete the - county structure. The first end point 2〇2 of the surface above the exposed complex electric column 2q is arranged in an array. How do you form a plurality of conductive elements? For example, a metal bump (four) ^ b (four)) or a solder ball, that is, a package structure for completing a die stack. Further, in another embodiment, a plurality of die-stacked package structures may be stacked on each other as shown in Fig. 8. At the 8th, the second crystal _ stack is the same structure as the first-grain stack structure, so that the plurality of electrical components of the second die stack structure are redundant with the conductive pillars of the first-die stack structure. The second conductive terminal 2〇4 is electrically connected, and here, the second conductive end of the conductive pillar 20, the point 2〇4 and the plurality of conductive elements of the second die stack structure further comprise a plurality Rotary pad 8G 'by this __ multi-stack structure. Although the present invention has been implemented on the basis of the present invention, it is possible to make some modifications and refinements when the invention is not limited to the spirit and scope of the present invention. The scope of protection shall be subject to the definition of the scope of the benefits attached to this manual. [Simplified Schematic Description] Fig. 1 to Fig. 7 are schematic diagrams showing the steps of the package structure of the body of the invention; and Fig. 8 shows the formation according to the technique disclosed in the present invention. Schematic diagram of multiple stacking structures. 201005885 [Main component symbol description] - 10 substrate 102 through hole 12 recess 20 conductive post 202 first conductive end 204 second conductive end point 30 first adhesive layer 32 second adhesive layer 40 first die 402 pad ❹ 42 second die 422 pad 50 first wire 52 second wire 60 package 70 conductive element 80 pad
1212