CN102931102B - 多芯片晶圆级封装的方法 - Google Patents

多芯片晶圆级封装的方法 Download PDF

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Publication number
CN102931102B
CN102931102B CN201210010835.6A CN201210010835A CN102931102B CN 102931102 B CN102931102 B CN 102931102B CN 201210010835 A CN201210010835 A CN 201210010835A CN 102931102 B CN102931102 B CN 102931102B
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wafer
semiconductor element
material layer
photosensitive material
group
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CN102931102A (zh
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董志航
余俊辉
余振华
史达元
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种多芯片晶圆级封装的方法，该方法包括：使用多个感光材料层形成重配置晶圆。在感光材料层中嵌入多个半导体芯片和晶圆。而且，在感光材料层中形成多种组件通孔。嵌入感光材料层中的每个半导体芯片均通过由组件通孔形成的连接路径连接至输入/输出焊盘。

Description

多芯片晶圆级封装的方法
技术领域
本发明涉及半导体技术领域，更具体地说，涉及多芯片晶圆级封装的方法。
背景技术
由于多种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进，导致半导体工业经历了快速的成长。对于大部分来说，集成密度的该改进来自最小特征尺寸的重复减小，这允许更多部件被集成到给定区域中。随着最近甚至更小的电子器件的要求的增长，需要更小的半导体管芯和半导体管芯的更有创造性的封装技术。
随着半导体技术的发展，基于多芯片晶圆级封装的半导体器件已经出现，作为进一步减小半导体芯片的物理尺寸有效的选择。在基于晶圆级封装的半导体器件中，有源电路(诸如，逻辑电路、存储器、处理器电路等)在不同晶圆上制造，并且每个晶圆管芯都使用拾取与放置技术被堆叠在另一晶圆管芯的顶部上。可以通过采用多芯片半导体器件实现更高密度。而且，多芯片半导体器件可以实现更小的形状系数(form factor)、成本效率、增加的性能和更低的功率消耗。
多芯片半导体器件可以包括：顶部有源电路层、底部有源电路层和多个中间层(inter layer)。在多芯片半导体器件中，两个管芯(die)通过多个微凸块被接合到一起并且通过多个硅通孔相互电连接。微凸块和硅通孔提供在多芯片半导体器件的垂直轴上的电互连。结果，两个半导体管芯之间的信号路径比传统多芯片器件中的更短，传统多芯片器件中，不同管芯使用互连技术(诸如，基于线接合的芯片堆叠封装)被接合到一起。多芯片半导体器件可以包括堆叠在一起的多种半导体管芯。多个半导体管芯在晶圆被切割之前被封装。晶圆级封装技术具有一些优点。在晶圆级封装多个半导体管芯的一个有益特征是多芯片晶圆级封装技术可以降低制造成本。基于晶圆级封装的多芯片半导体器件的另一有益特征在于，通过采用微凸块和硅通孔减少寄生损失。
发明内容
根据本发明，提供一种方法，包括：在晶圆的顶面上附着第一半导体管芯；在所述第一半导体管芯上附着第二半导体管芯；通过将所述第一半导体管芯和所述第二半导体管芯嵌入第一感光材料层，形成重配置晶圆；以及在所述第一感光材料层中形成第一组组件通孔。
优选地，该方法进一步包括：使用粘着层在底层上附着所述晶圆；以及将所述底层与所述晶圆分离。
优选地，该方法进一步包括：使用第一粘着层将所述第二半导体芯片附着至所述第一半导体管芯；使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆；在所述第一感光材料层的顶部上形成第一重分配层；以及在所述第一重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块以正面对正面的方式将所述第二半导体管芯附着至所述第一半导体管芯；以及使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
优选地，该方法进一步包括：在所述第二半导体管芯的一侧和所述第一感光材料层的正面之间形成第一组开口；在所述第一半导体管芯的一侧和所述第一感光材料层的所述正面之间形成第二组开口；以及在所述晶圆的一侧和所述第一感光材料层的所述正面之间形成第三组开口。
优选地，该方法进一步包括：在所述第一组开口中电镀导电材料；在所述第二组开口中电镀导电材料；以及在所述第三组开口中电镀导电材料。
优选地，该方法进一步包括：将所述重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
根据本发明的另一方面，提供一种方法，包括：在第二晶圆的顶面上附着半导体管芯；通过将所述第二晶圆和所述半导体管芯嵌入到第一感光材料层中，形成第一重配置晶圆；将所述第一重配置晶圆切割为多个多管芯结构；在第一晶圆的顶面上附着所述多个多管芯结构；通过将所述多个多管芯结构嵌入到第二感光材料层中，形成第二重配置晶圆；以及在所述第二感光材料层中形成第一组组件通孔。
优选地，该方法进一步包括：使用第一粘着层在第一底层上附着所述第一晶圆；以及使所述第一底层与所述第一晶圆分离。
优选地，该方法进一步包括：使用第三粘着层将所述半导体管芯附着至所述第二晶圆；使用第四粘着层以背面对正面的方式将所述多个多管芯结构附着至所述第一晶圆；在所述第一感光材料层的顶部上形成第一重分配层；在所述第二感光材料层的顶部上形成第二重分配层；以及在所述第二重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块以正面对正面的方式将所述半导体管芯附着至所述第二晶圆；使用多个金属凸块以正面对正面的方式将所述多个多管芯结构附着至所述第一晶圆。
优选地，该方法进一步包括：在所述半导体管芯的一侧和所述第一感光材料层的正面之前形成第一组开口；在所述第二晶圆的一侧和所述第一感光材料层的所述正面之间形成第二组开口；在所述第一晶圆的一侧和所述第二感光材料层的正面之间形成第三组开口；以及在所述第二感光材料层的所述正面和所述第一感光材料层的所述正面之间形成第四组开口。
优选地，该方法进一步包括：在所述第一组开口中电镀导电材料；在所述第二组开口中电镀导电材料；在所述第三组开口中电镀导电材料；以及在所述第四组开口中电镀导电材料。
优选地，该方法进一步包括：将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
根据本发明的再一方面，提供一种方法，包括：在晶圆的顶面上附着第一半导体管芯；通过将所述第一半导体管芯嵌入第一感光材料层中，形成第一重配置晶圆；在所述第一感光材料层中形成第一组组件通孔；在所述第一感光材料层上附着第二半导体管芯；在所述第一感光材料层的顶部上形成第二感光材料层，其中，所述第二半导体管芯被嵌入所述第二感光材料层中；以及在所述第二感光材料层中形成第二组组件通孔。
优选地，该方法进一步包括：在第一底层上附着所述晶圆。
优选地，该方法进一步包括：使用第一粘着层将所述第二半导体管芯附着至所述第一半导体管芯；使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆；在所述第一感光材料层的顶部上形成第一重分配层；在所述第二感光材料层的顶部上形成第二重分配层；以及在所述第二重分配层的顶部上形成多个焊球。
优选地，该方法进一步包括：使用多个金属凸块将所述第二半导体管芯的顶面附着至所述第一重分配层；以及使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
优选地，该方法进一步包括：使所述第一组组件通孔和所述第二组组件通孔互连。
优选地，该方法进一步包括：通过将所述第一重配置晶圆和所述第二半导体管芯嵌入到所述第二感光材料层中，形成第二重配置晶圆；以及将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
附图说明
为了更完整地理解本发明及其优点，现在结合附图对以下说明作出参考。
图1是根据一实施例的多芯片半导体器件的横截面图；
图2A-图2E是根据一实施例的在制造多芯片半导体器件中的中间阶段的横截面图；
图3A-图3I是根据另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图；以及
图4A-图4H是根据还有的另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。
除非另外指出，不同附图中的相应数字和符号通常是指相应部件。附图被绘制以清楚地示出多种实施例的相关方面，并且不必须按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本披露将关于特定上下文中的实施例(多芯片晶圆级半导体封装)描述。然而，实施例还可以应用至多种半导体器件。
首先参考图1，示出根据一实施例的多芯片半导体器件的横截面图。多芯片半导体器件100包括第一半导体管芯131、第二半导体管芯132和第三半导体管芯133。如图1中所示，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133被堆叠在一起，以形成多芯片半导体器件100。更特别地，第二半导体管芯132的背面使用第一粘着层126附着至第一半导体管芯131的正面。类似地，第三半导体管芯133的背面使用第二粘着层124附着至感光材料层108。
多芯片半导体器件100进一步包括多个焊球110，作为使用多个凸块下金属化(UBM)结构112装配在多芯片半导体器件100的顶部上的输入/输出(I/O)焊盘。为了给出多个实施例发明角度的基本理解，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133不被详细地绘制。然而，应该注意，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133可以包括基本半导体层，诸如，有源电路层、基板层、层间电介质(ILD)层和金属间电介质(IMD)层(未示出)。
根据一实施例，第一半导体管芯131可以包括多个逻辑电路，诸如，中央处理单元(CPU)、图形处理单元(GPU)等。第二半导体管芯132和第三半导体管芯133可以包括多个存储器电路，诸如，静态随机存取存储器(SRAM)和动态随机存取存储器(DRAM)等。应该注意，第一半导体管芯131、第二半导体管芯132和第三半导体管芯133可以具有多个实施例，其也在本披露的范围内。
多芯片半导体器件100可以包括两个感光材料层106和108。感光材料层106形成在感光材料层108的顶部上。如图1中所示，第二半导体管芯132被嵌入感光材料层108中。第三半导体管芯133被嵌入感光材料层106中。感光材料层106可以进一步包括多个组件通孔(TAV，throughassembly via)102、104和116。应该注意，如图1中所示，TAV 104和TAV116都形成在感光材料层106中。然而，TAV 116形成在第三半导体管芯133和多芯片半导体器件100的焊球侧之间。相反地，TAV 104形成穿过感光材料层106，并且进一步连接至形成在感光材料层108的顶部上的第二重分配层134。同样地，TAV 102形成穿过感光材料层106，并且进一步连接至形成在感光材料层108中的TAV。以下参考图2-图4详细地描述感光材料层106、108和在每层中的各个TAV的形成处理。
第一半导体管芯131的有源电路层(未示出)通过多个TAV 102、104和重分配层114和134连接至焊球110。更特别地，第二重分配层134、TAV102、TAV 104和第一重分配层114可以形成多种连接路径，使得第一半导体管芯131的有源电路可以与焊球110连接。类似地，第一重分配层114、第二重分配层134和TAV 104、116可以形成多种连接路径，使得第二半导体管芯132和第三半导体管芯133的有源电路(未示出)可以与焊球110连接。
多芯片半导体器件100可以包括形成在第一半导体管芯131的背面上的底平面底层120。底平面底层120可以由导电材料形成，诸如，铜、银、金、钨、铝、其结合等。可替换地，底平面底层120可以由多种材料形成，诸如，玻璃、硅、陶瓷、聚合体等。根据一实施例，底平面底层120可以通过粘合剂122(诸如，包括环氧树脂等的热界面材料)粘合在半导体管芯131的背面上。
如在图1中所示，底层120邻近第一半导体管芯131直接形成。从而，底层120可以帮助消散从第一半导体管芯131产生的热。结果，底层120可以帮助减小第一半导体管芯131的结温温度(junction temperature)。与不具有底层的半导体管芯相比，第一半导体管芯131受益于来自底层120的散热，使得第一半导体管芯131的可靠性和性能可以被改进。根据一实施例，底层120的厚度在5um至50um的范围内。应该注意，底层的厚度的范围被选择纯粹用于演示目的，并且不旨在将本披露的多种实施例限制到任何特定厚度。本领域技术人员将认识到多种改变、替换和修改。
将进一步注意，本领域技术人员将认识到多管芯半导体器件100的堆叠结构可以具有多种改变、替换和修改。例如，第二半导体管芯132可以使用多个金属凸块(未示出)被面对面地附着至第一半导体管芯131。类似地，第三半导体管芯133可以被翻转(flip)。结果，在第三半导体管芯133和第二半导体管芯132之间存在面对面堆叠结构。
图2A-图2E是根据一实施例的制造多芯片半导体器件的中间阶段的横截面图。图2A示出晶圆平面141的横截面图。如图2A中所示，晶圆平面141可以进一步包括多个金属焊盘204，其连接件通过重分配层202被重新分配。晶圆平面141可以包括多个第一半导体管芯，诸如131。而且，每个第一半导体管芯131都可以包括有源电路层、基板层、ILD层和IMD层(未示出)。金属焊盘204和重分配层202提供用于晶圆平面41的有源电路层的多种连接路径。
图2B示出在晶圆平面141的顶部上堆叠第二半导体管芯132和第三半导体管芯133的处理。第二半导体管芯132的背面通过采用第一粘合剂126(诸如，环氧树脂、热界面材料等)附着至晶圆平面141的顶部。类似地，第三半导体管芯133的背面通过采用第二粘合剂124附着至第二半导体管芯132的顶部。注意，第二粘合剂124可以与第一粘合剂126相同。可替换地，第二粘合剂124可以与第一粘合剂126不同。
图2C示出感光材料层106的横截面图。感光材料层106形成在晶圆平面141的顶部上。如图2C中所示，第二半导体管芯132和第三半导体管芯133被嵌入感光材料层106中。感光材料层可以包括聚苯并噁唑(PBO)、SU-8感光环氧树脂、薄膜型聚合体材料等。
图2C进一步示出在感光材料层106中形成多个开口的横截面图。考虑电和热的需求，感光材料层106的选择区域被曝光。结果，被曝光的感光区域的物理特性改变。根据一实施例，被曝光区域的物理特性的改变将导致，当显影剂溶液被应用至感光材料层106时，暴光区域被蚀刻掉。结果，形成多种开口252。在感光材料层106中形成开口252涉及光刻操作(其已知)，并且从而在此不进一步详细地论述。
图2D示出多个TAV和重分配层的形成。如图2D中所示，导电材料使用电化学镀处理填充开口252(未示出，但是在图2C中示出)。结果，多个TAV 102、104和116形成在感光材料层106中。导电材料可以是铜，但是可以是任何合适导电材料，诸如，铜合金、铝、钨、银及其结合。为了重新分配与TAV 102、104和116的电连接，第一重分配层114可以形成在感光材料层106的顶部上。第一重分配层114可以通过电化学镀方法形成。应该注意，第一重分配层114可以与TAV 102、104和116同时形成。可替换地，第一重分配层114可以在形成TAV 102、104和116之后形成。
图2E示出多个UBM结构和互连焊盘的形成。多个UBM结构112形成在重分配层114的顶部。UBM结构112可以帮助防止多芯片半导体器件的焊球和集成电路之间的扩散，同时提供低阻抗电连接。互连焊盘提供连接多芯片半导体器件与外部电路(未示出)的有效方式。互连焊盘是多芯片半导体器件的I/O焊盘。根据一实施例，互连焊盘可以是多个焊球110。可替换地，互连焊盘可以是多个接点栅格阵列(LGA)焊盘。图2E进一步示出使用切割处理将重配置晶圆分为多个多管芯结构的处理。切割处理在本领域中已知，并且从而在此不再详细地论述。
图3A-图3I是根据另一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。图3A示出放置晶圆平面142的横截面图。如图3A中所示，晶圆平面142可以进一步包括多个金属焊盘304，其连接件通过重分配层302被重新分配。晶圆平面142可以进一步包括多个第二半导体管芯132。图3B示出在晶圆平面142的顶部上堆叠第三半导体管芯133的处理。第三半导体管芯133的背面通过采用第二粘合剂124被粘合在晶圆平面142的顶部上。
图3C示出感光材料层108的横截面图。感光材料层108形成在晶圆平面142的顶部上。如图3C中所示，第三半导体管芯133被嵌入感光材料层108中。感光材料可以包括聚苯并噁唑(PBO)、SU-8感光环氧树脂、薄膜型聚合体材料等。图3C进一步示出在感光材料层108中形成多个开口352的横截面图。感光材料层108中的开口352的形成类似于图2C中所示的开口252的形成，从而不再进一步详细地描述以避免重复。
图3D示出多个TAV和重分配层的形成。如图3D中所示，TAV 104、116和重分配层134可以通过电化学镀处理形成，其以上已经参考图2D被描述，从而不再重复。图3D进一步示出使用切割处理将重配置晶圆分为多个多管芯结构302的处理。切割处理在本领域中已知，从而在此不再详细地论述。
图3E示出晶圆平面141的横截面图。如图3E中所示，晶圆平面141可以进一步包括多个金属焊盘204，其连接件通过重分配层202被重新分配。晶圆平面141可以进一步包括多个第一半导体管芯131。图3F示出在晶圆平面141的顶部上堆叠多管芯结构302的处理。多管芯结构302的形成已经关于图3D在以上描述了。如图3D所示，多管芯结构302使得顶部具有感光层，其中，第三半导体管芯133被嵌入感光层中。多管芯结构302的背面通过采用第一粘合剂126被粘合在晶圆平面141的顶部上。
图3G示出感光材料层106的横截面图。感光材料层106形成在晶圆平面141的顶部上。如图3G中所示，第二半导体管芯132和第三半导体管芯133被嵌入感光材料层106中。图3G进一步示出在感光材料层106中形成多个开口的横截面图。形成感光材料层和感光材料层中的多个开口的处理已经关于图2C在以上描述，从而在此不再详细地论述以避免重复。
图3H示出感光材料层106中的多个TAV和感光材料层106的顶部上的重分配层的形成。在感光层中形成多个TAV和重分配层的处理在以上关于图2D进行了描述，并且从而不再进一步详细地描述。图3I示出多个UBM结构和互连焊盘的形成。图3I进一步示出使用切割处理形成多管芯结构312。形成UBM结构和互连焊盘并且将重配置晶圆分为多个多管芯结构312的处理类似于图2E。
图4A-图4H是根据又一实施例的在制造多芯片半导体器件中的中间阶段的横截面图。图4A示出晶圆平面141的横截面图，其类似于图2A。图4B示出在晶圆平面141的顶部上堆叠第二半导体管芯132的处理。第二半导体管芯132的背面通过采用第一粘合剂126被粘合到第一半导体管芯131的顶部上。
图4C示出感光材料层108的横截面图。感光材料层108形成在晶圆平面141的顶部上。如图4C中所示，第二半导体管芯132被嵌入感光材料层108中。图4C进一步示出在感光材料层108中形成多个开口452的横截面图。形成多个开口452的处理类似于图2C中所示的形成开口252的处理，并且从而在此不再进一步详细地论述。
图4D示出多个TAV和第二重分配层的形成。类似于图2D中所示的处理，多个TAV 102、104和第二重分配层134通过电化学镀方法形成。图4E示出在感光材料层108的顶部上堆叠第三半导体管芯13的处理。第三半导体管芯133的背面通过采用第二粘合剂124被粘合在感光材料层108的顶部上。
图4F示出感光材料层106的横截面图。感光材料层106形成在感光材料层108的顶部上。如图4F中所示，第三半导体管芯133被嵌入感光材料层106中。形成感光材料层和开口的处理以上关于图2C进行了描述，从而不再详细地论述以避免重复。图4G示出在感光材料层106中形成多个TAV的横截面图。形成TAV 102、104、106的处理类似于图2D中所示的处理。
图4H示出多个UBM结构和互连焊盘的形成。多个UBM结构形成在重分配层114和焊球110之间。图4H进一步示出使用切割处理将重配置晶圆分为多个多管芯结构412的处理。切割处理在本领域中已知，并且从而在此不再详细地论述。
虽然已经详细地描述了本披露的实施例及其优点，但是在不脱离由所附权利要求限定的本披露的精神和范围的情况下，在此可以做出多种改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (19)

1.一种多芯片晶圆级封装的方法，包括：
在晶圆的顶面上附着第一半导体管芯；
在所述第一半导体管芯上附着第二半导体管芯；
通过将所述第一半导体管芯和所述第二半导体管芯嵌入第一感光材料层，形成重配置晶圆，其中，所述晶圆未嵌入所述第一感光材料层中；
在所述第一感光材料层中形成第一组组件通孔，其中，通过使所述第一感光材料层曝光和显影而形成所述第一组组件通孔的开口；
在所述第二半导体管芯的一侧和所述第一感光材料层的正面之间形成第一组开口；
在所述第一半导体管芯的一侧和所述第一感光材料层的所述正面之间形成第二组开口；
在所述晶圆的一侧和所述第一感光材料层的所述正面之间形成第三组开口；
在所述第一感光材料层的顶部上形成第一重分配层，以提供多种连接路径，其中，所述第一重分配层与所述第一组组件通孔同时形成；以及
在所述第一重分配层的顶部上形成多个焊球。
2.根据权利要求1所述的方法，进一步包括：
使用粘着层在底层上附着所述晶圆；以及
将所述底层与所述晶圆分离。
3.根据权利要求1所述的方法，进一步包括：
使用第一粘着层将所述第二半导体芯片附着至所述第一半导体管芯；
使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆。
4.根据权利要求1所述的方法，进一步包括：
使用多个金属凸块以正面对正面的方式将所述第二半导体管芯附着至所述第一半导体管芯；以及
使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
5.根据权利要求1所述的方法，进一步包括：
在所述第一组开口中电镀导电材料；
在所述第二组开口中电镀导电材料；以及
在所述第三组开口中电镀导电材料。
6.根据权利要求1所述的方法，进一步包括：
将所述重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
7.一种多芯片晶圆级封装的方法，包括：
在第二晶圆的顶面上附着半导体管芯；
通过将所述第二晶圆和所述半导体管芯嵌入到第一感光材料层中，形成第一重配置晶圆；
将所述第一重配置晶圆切割为多个多管芯结构；
在第一晶圆的顶面上附着所述多个多管芯结构；
通过将所述多个多管芯结构嵌入到第二感光材料层中，形成第二重配置晶圆；
在所述第二感光材料层中形成第一组组件通孔；
在所述第一感光材料层的顶部上形成第一重分配层，以提供多种连接路径；
在所述第二感光材料层的顶部上形成第二重分配层，以提供多种连接路径；以及
在所述第二重分配层的顶部上形成多个焊球。
8.根据权利要求7所述的方法，进一步包括：
使用第一粘着层在第一底层上附着所述第一晶圆；以及
使所述第一底层与所述第一晶圆分离。
9.根据权利要求7所述的方法，进一步包括：
使用第三粘着层将所述半导体管芯附着至所述第二晶圆；
使用第四粘着层以背面对正面的方式将所述多个多管芯结构附着至所述第一晶圆。
10.根据权利要求7所述的方法，进一步包括：
使用多个金属凸块以正面对正面的方式将所述半导体管芯附着至所述第二晶圆；
使用多个金属凸块以正面对正面的方式将所述多个多管芯结构附着至所述第一晶圆。
11.根据权利要求7所述的方法，进一步包括：
在所述半导体管芯的一侧和所述第一感光材料层的正面之前形成第一组开口；
在所述第二晶圆的一侧和所述第一感光材料层的所述正面之间形成第二组开口；
在所述第一晶圆的一侧和所述第二感光材料层的正面之间形成第三组开口；以及
在所述第二感光材料层的所述正面和所述第一感光材料层的所述正面之间形成第四组开口。
12.根据权利要求11所述的方法，进一步包括：
在所述第一组开口中电镀导电材料；
在所述第二组开口中电镀导电材料；
在所述第三组开口中电镀导电材料；以及
在所述第四组开口中电镀导电材料。
13.根据权利要求7所述的方法，进一步包括：
将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
14.一种多芯片晶圆级封装的方法，包括：
在晶圆的顶面上附着第一半导体管芯；
通过将所述第一半导体管芯嵌入第一感光材料层中，形成第一重配置晶圆；
在所述第一感光材料层中形成第一组组件通孔；
在所述第一感光材料层上附着第二半导体管芯；
在所述第一感光材料层的顶部上形成第二感光材料层，其中，所述第二半导体管芯被嵌入所述第二感光材料层中；
在所述第二感光材料层中形成第二组组件通孔，其中，所述第一组组件通孔和所述第二组组件通孔通过重分配层形成垂直于所述第一半导体管芯和所述第二半导体管芯的电互连；
在所述第一感光材料层的顶部上形成第一重分配层，以提供多种连接路径；
在所述第二感光材料层的顶部上形成第二重分配层，以提供多种连接路径；以及
在所述第二重分配层的顶部上形成多个焊球。
15.根据权利要求14所述的方法，进一步包括：
在第一底层上附着所述晶圆。
16.根据权利要求14所述的方法，进一步包括：
使用第一粘着层将所述第二半导体管芯附着至所述第一半导体管芯；
使用第二粘着层以背面对正面的方式将所述第一半导体管芯附着至所述晶圆。
17.根据权利要求16所述的方法，进一步包括：
使用多个金属凸块将所述第二半导体管芯的顶面附着至所述第一重分配层；以及
使用多个金属凸块以正面对正面的方式将所述第一半导体管芯附着至所述晶圆。
18.根据权利要求14所述的方法，进一步包括：使所述第一组组件通孔和所述第二组组件通孔互连。
19.根据权利要求14所述的方法，进一步包括：
通过将所述第一重配置晶圆和所述第二半导体管芯嵌入到所述第二感光材料层中，形成第二重配置晶圆；以及
将所述第二重配置晶圆切割为多个封装件，其中，每个封装件都包括多个半导体管芯。
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