CN105097736B - 利用后通孔工艺的3d衬底上晶圆上芯片结构 - Google Patents
利用后通孔工艺的3d衬底上晶圆上芯片结构 Download PDFInfo
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- CN105097736B CN105097736B CN201510232485.1A CN201510232485A CN105097736B CN 105097736 B CN105097736 B CN 105097736B CN 201510232485 A CN201510232485 A CN 201510232485A CN 105097736 B CN105097736 B CN 105097736B
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Classifications
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Abstract
本发明公开了一种封装件,其包括设置在第一半导体衬底的第一侧上的第一重分布层(RDL)和设置在第二半导体衬底上的第二RDL,其中,第一RDL接合至第二RDL。第一导电元件设置在第一RDL和第二RDL中。第一通孔从一个或多个第一导电元件延伸穿过第一半导体衬底至与第一侧相对的第一半导体衬底的第二侧。第一间隔件插入在第一半导体衬底和第一通孔之间并且每个第一间隔件从相应的一个第一导电元件延伸穿过第一半导体衬底。本发明涉及利用后通孔工艺的3D衬底上晶圆上芯片结构。
Description
优先权声明和交叉引用
本申请要求于2014年5月9日提交的标题为“利用后通孔工艺的3D衬底上晶圆上芯片结构”的美国临时申请第61/991,287号的优先权,其全部内容通过引用结合于此作为参考。
技术领域
本发明涉及利用后通孔工艺的3D衬底上晶圆上芯片结构。
背景技术
由于各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成度不断提高,半导体产业经历了快速的发展。在大多数情况下,这种集成度的提高源自最小部件尺寸的不断减小(例如,将半导体工艺节点朝着亚20nm节点缩减),这使得更多的部件集成在给定的区域内。随着近来对微型化、更高速度、更大带宽以及更低功耗和延迟的需求增长,也产生了对于半导体管芯的更小和更具创造性的半导体管芯的封装技术的需要。
随着半导体技术的进一步发展,堆叠式半导体器件(例如,3D集成电路(3DIC))已作为有效替代物而出现以进一步减小半导体器件的物理尺寸。在堆叠式半导体器件中,在不同的半导体晶圆上制造有源电路(诸如逻辑电路、存储器电路、处理器电路等)。两个或多个半导体晶圆可以安装在彼此的顶部上以进一步减小半导体器件的形状因数。
通过合适的接合技术可将两个半导体晶圆或管芯接合在一起。常用的接合技术包括直接接合、化学活化接合、等离子体活化接合、阳极接合、共晶接合、玻璃熔融接合、粘合接合、热压接合、反应接合等。可在堆叠式半导体晶圆之间提供电连接。堆叠的半导体器件可以提供更高的密度和更小的形状因数并且允许增加的性能和更低的功耗。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种封装件,包括:第一重分布层(RDL),设置在第一半导体衬底的第一侧上;第二RDL,设置在第二半导体衬底上,其中,所述第一RDL接合至所述第二RDL;第一导电元件,设置在所述第一RDL和所述第二RDL中;第一通孔,从一个或多个所述第一导电元件延伸穿过所述第一半导体衬底至与所述第一侧相对的所述第一半导体衬底的第二侧;以及第一间隔件,插入在所述第一半导体衬底和所述第一通孔之间,并且每个所述第一间隔件从相应的一个所述第一导电元件延伸穿过所述第一半导体衬底。
在上述封装件中,所述第一通孔的至少第一个与设置在所述第一RDL中的一个所述第一导电元件接触,并且其中,所述第一通孔的至少第二个与设置在所述第二RDL中的一个所述第一导电元件的接触。
在上述封装件中,所述第一通孔的至少一个与所述第一RDL中的所述第一导电元件的第一个以及所述第二RDL中的所述第一导电元件的第二个均接触。
在上述封装件中,还包括:模塑料,设置在所述第二RDL上方以及所述第一RDL和所述第一衬底周围。
在上述封装件中,还包括:第二通孔,邻近所述第一衬底并且从一个或多个所述第一导电元件延伸穿过所述模塑料。
在上述封装件中,所述第一通孔延伸穿过所述第一RDL的至少一部分,并且其中,所述第二通孔延伸穿过所述第二RDL的至少一部分。
在上述封装件中,还包括:顶部RDL,形成在所述第一衬底的所述第二侧上方,所述顶部RDL具有设置在一个或多个介电层中的第二导电元件,并且其中,所述第一通孔的每个均与所述第二导电元件的相应一个电接触。
在上述封装件中,所述模塑料的第一部分在所述第一衬底的所述第二侧上方延伸,并且其中,所述第一通孔延伸穿过所述模塑料的第一部分。
根据本发明的另一方面,还提供了一种封装件,包括:第一衬底,具有设置在所述第一衬底的第一侧上的第一重分布层(RDL),所述第一RDL具有设置在所述第一RDL中的一个或多个第一导电元件;管芯,具有第二衬底和设置在所述第二衬底的第一侧上的第二RDL,所述第二RDL具有设置在所述第二RDL中的一个或多个第二导电元件,其中,所述第一RDL接合至所述第二RDL;模塑料,设置在所述第一RDL上方和所述管芯上方,所述模塑料的第一部分在所述第二衬底的与所述第一侧相对的第二侧上方延伸;间隔件,设置在所述第二衬底中,每个所述间隔件从所述第二衬底的至少所述第一侧延伸穿过所述模塑料的第一部分;以及通孔,延伸穿过所述模塑料的第一部分并且延伸穿过所述第二衬底,每个所述通孔与所述一个或多个第一导电元件或者所述一个或多个第二导电元件的至少一个接触,每个所述通孔通过所述间隔件的相应一个与所述第二衬底电绝缘。
在上述封装件中,每个所述通孔的下部延伸穿过所述第二RDL的一部分并且延伸穿过所述第二衬底至所述模塑料的第一部分内;其中,每个所述通孔的上部设置在所述模塑料的第一部分中;以及其中,每个所述通孔的上部具有大于所述通孔的相应一个的所述下部的宽度。
在上述封装件中,还包括:第三RDL,设置在所述模塑料上,所述第三RDL具有设置在所述第三RDL中的第二导电元件,每个所述第二导电元件与所述通孔的相应一个电接触。
在上述封装件中,所述间隔件的第一间隔件设置在邻近所述通孔的相应一个的顶部的所述模塑料的第一部分中。
在上述封装件中,一个或多个所述间隔件设置在所述第二RDL中。
在上述封装件中,至少一个所述通孔与所述第一导电元件的一个以及所述第二导电元件的至少一个接触。
根据本发明的又一方面,还提供了一种方法,包括:提供第一衬底,所述第一衬底具有设置在所述第一衬底上的第一重分布层(RDL),其中,导电元件设置在所述第一RDL中;提供第二衬底,所述第二衬底具有设置在所述第二衬底上的第二RDL,所述第一RDL接合至所述第二RDL,其中,导电元件设置在所述第二RDL中;穿过至少所述第一衬底蚀刻出第一通孔开口;在所述第一衬底上方形成延伸至所述第一通孔开口内的隔离层;蚀刻所述隔离层,所述蚀刻在所述第一通孔开口的侧壁上形成间隔件,至少一个所述间隔件延伸穿过所述第一衬底并且具有设置在至少一个所述导电元件上的底面;以及在所述第一通孔开口中形成电连接至至少一个所述导电元件的第一通孔;其中,所述第一通孔从一个所述导电元件延伸穿过所述第一衬底至所述第一衬底的与所述第一RDL相对的至少顶侧;以及其中,一个或多个所述间隔件插入在所述第一衬底和所述第一通孔之间,并且将所述第一通孔与所述第一衬底电绝缘。
在上述方法中,还包括:在所述第二RDL上方形成模塑料,从而使得所述第二RDL设置在所述模塑料和所述第二衬底之间;穿过至少所述模塑料蚀刻出第二通孔开口;以及在所述第二通孔开口中形成电连接至至少一个所述导电元件的第二通孔;其中,在所述第一衬底周围形成所述模塑料;以及其中,在同一工艺步骤中形成所述第一通孔和所述第二通孔。
在上述方法中,所述模塑料的第一部分在所述第一衬底上方延伸,并且其中,所述第一通孔延伸穿过所述模塑料的第一部分。
在上述方法中,还包括:蚀刻至所述第一RDL内以使所述第一通孔开口延伸穿过所述第一RDL的至少一部分;其中,蚀刻出所述第一RDL开口包括蚀刻所述模塑料的第一部分以形成所述第一通孔开口的上部,所述第一通孔开口的上部比所述第一通孔开口的下部具有更大的宽度;以及其中,在蚀刻所述第一RDL之后,实施形成所述隔离层。
在上述方法中,蚀刻所述隔离层在所述第一通孔开口的上部中形成所述间隔件的至少第一个,所述间隔件的至少第一个与所述第一通孔开口的下部中的所述间隔件的第二个间隔开。
在上述方法中,还包括:在所述模塑料上形成第三RDL;以及在所述第三RDL上形成连接件,所述连接件通过所述第三RDL电连接至所述第一通孔。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图15示出了根据实施例的在使用后通孔工艺形成晶圆上芯片结构中的中间处理步骤的截面图。
图16至图20示出了根据另一实施例的在使用后通孔工艺形成晶圆上芯片结构中的中间处理步骤的截面图。
图21至图30示出了根据实施例的在使用双镶嵌后通孔工艺形成晶圆上芯片结构中的中间处理步骤的截面图。
图31A至图31C是根据一些实施例的示出形成晶圆上芯片结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
半导体器件接合在一起以形成具有各种功能的封装件。在一些工艺中,管芯、晶圆或管芯与晶圆的组合使用直接表面接合(诸如氧化物至氧化物接合)通过混合接合而接合在一起。已经发现,可以使用后通孔工艺提供接合的晶圆之间的互连。在后通孔工艺中,在已经接合管芯之后,穿过管芯中的一个形成通孔以提供管芯之间的电连接,和提供管芯和外部连接件之间的电源和数据连接。已进一步发现,通过使用位于通孔开口的侧壁上的自对准绝缘间隔件,穿过一个或多个管芯的衬底形成的导电通孔可以与衬底绝缘。侧壁上的自对准间隔件允许更窄、更高的通孔并且将通孔的高宽比提高至约3和约10之间。提高的高宽比导致更紧密布置的通孔阵列。
图1示出了根据实施例的在接合之前的晶圆104和管芯102的截面图。管芯102包括诸如具有形成在其中的一个或多个有源器件的半导体的管芯衬底106。管芯重分布层(RDL)108设置在管芯衬底106上。管芯RDL 108包括具有设置在介电层中的导电元件110的一个或多个介电层。管芯RDL108形成在具有有源器件的衬底的一侧上方,其中,导电元件110连接至位于管芯衬底106上的有源器件。
晶圆104具有设置在晶圆衬底112上方的晶圆RDL 114。在一些实施例中,晶圆衬底112是其中形成有一个或多个有源器件的半导体。晶圆RDL114形成在晶圆衬底112中的有源器件上方并且具有设置在介电层中的一个或多个导电元件110。
图2示出了根据实施例的用于接合晶圆的处理步骤的截面图。在RDL108和114的顶面处接合管芯102和晶圆104,从而形成接合界面202。管芯102和晶圆104用作封装件的基础,封装件具有用于将封装件安装至外部器件、衬底等的连接件。在一些实施例中,例如,管芯102通过直接表面接合、金属至金属接合、混合接合或其他接合工艺接合至晶圆104。直接表面接合工艺通过清洗和/或表面活化工艺,然后对连接的表面施加压力、热量和/或其他接合工艺步骤来生成氧化物至氧化物接合或衬底至衬底接合。在一些实施例中,通过使得暴露在RDL 108和114的表面处的诸如金属接合焊盘的导电元件110融合来实现通过金属至金属接合来接合管芯102和晶圆104。在其他实施例中,混合接合用于通过直接表面接合和金属至金属接合的组合来接合管芯102和晶圆104,其中,RDL 108和114的表面以及暴露在RDL 108和114的表面处的金属接合焊盘的表面均被接合。在一些实施例中,对接合的管芯进行烘烤、退火、施压或以其他方式处理以加强或完成该接合。
图3是根据实施例的在封装件上方形成模塑料302的截面图。模塑料302形成在管芯102周围以及晶圆RDL114上。在一些实施例中,当应用模塑料302时,使用例如模具(未示出)来成形或模制模塑料302,模具可以具有用于保持模塑料302的边界或其他部件。这样的模具可以用于对管芯102周围的模塑料302进行加压模制以迫使模塑料302进入开口和凹槽内,消除模塑料302中的鼓泡等。在实施例中,模塑料302是非导电或介电材料,诸如环氧树脂、树脂、诸如PBO的可模制聚合物或其他可模制材料。例如,模塑料302是通过化学反应或通过干燥固化的环氧树脂或树脂。在另一实施例中,模塑料302是紫外线(UV)固化的聚合物。在其他实施例中,在封装件上方形成包括氧化物、氮化物等的介电或绝缘膜。在这样的实施例中,模塑料302由绝缘膜代替。然而,为了简单起见,模塑料302的实施例在本文中称为包括介电或绝缘膜。在一些实施例中,氧化物或氮化物绝缘膜是氮化硅、氧化硅、氮氧化硅或其他介电材料并且是通过化学汽相沉积(CVD)、等离子体增强CVD(PECVD)或其他工艺形成的。
在管芯102和晶圆104上方形成模塑料302之后,例如,通过研磨、化学机械抛光(CMP)、蚀刻或其他工艺来降低或平坦化模塑料302。例如,当模塑料302是诸如氧化物或氮化物的绝缘膜时,干蚀刻或CMP用于降低或平坦化模塑料302的顶面。在一些实施例中,在平坦化后,模塑料302延伸在管芯102上方,并且在其他实施例中,降低模塑料302,从而使得管芯102暴露为具有与模塑料302的顶面基本上平齐的顶面。在一些实施例中,管芯衬底106与模塑料在相同工艺中被减薄或降低,从而导致管芯102的背侧表面与模塑料表面基本上平齐。
图4是根据实施例的将封装件安装至载体402的截面图。反转封装件以允许接近晶圆衬底112和通过晶圆衬底112进行处理。例如,管芯102和模塑料302的表面接合至玻璃载体,或其他处理衬底。封装件使用管芯附接膜(DAF)、粘合剂等附接至载体402。在其他实施例中,封装件附接至载体402,其中,晶圆衬底112位于载体402上,从而允许通过封装件的管芯侧处理封装件。在一些实施例中,通过研磨、CMP、蚀刻或其他工艺来减薄或降低晶圆衬底112。
图5是根据实施例的掩蔽晶圆衬底112的截面图。蚀刻停止层502形成在晶圆衬底112上,并且由与晶圆衬底112的材料相比具有高蚀刻选择性的材料形成。此外,蚀刻停止层502与晶圆RDL 114和管芯RDL 108相比具有高蚀刻选择性。在一些实施例中,其中,例如,晶圆衬底112是硅并且RDL 114和108是氧化硅,蚀刻停止层502是诸如氮化硅(SiN)的氮化物、诸如碳化硅(SiC)的碳化物或诸如氮氧化硅(SiON)的氧氮化物或其他蚀刻停止材料。在这样的实施例中,通过使用CVD、PECVD、物理汽相沉积(PVD)、外延、旋涂工艺或其他沉积工艺来沉积蚀刻停止层。
掩模504形成在蚀刻停止层502上方并且被图案化以形成暴露蚀刻停止层502的部分的开口506。在一些实施例中,掩模504是被沉积、曝光和显影的光刻胶。掩模504中的开口506在RDL 108和114中的导电元件110上方对准。
图6是根据实施例的示出蚀刻停止层502的蚀刻的截面图。对蚀刻停止层502进行蚀刻以暴露晶圆衬底112。在一些实施例中,利用干等离子体蚀刻(诸如利用诸如四氟化碳(CF4)或六氟化硫(SF6)的氟基蚀刻剂的氧或氮等离子体)来蚀刻蚀刻停止层502。在其他实施例中,例如,使用硫酸(H2SO4)、热磷酸(H3PO4)等通过湿蚀刻来蚀刻蚀刻停止层502。
图7是根据实施例的示出晶圆衬底112的蚀刻的截面图。各向异性地蚀刻晶圆衬底112以形成具有基本上垂直壁的通孔开口702。在一些实施例中,在与蚀刻蚀刻停止层502不同的工艺步骤中蚀刻晶圆衬底112,从而允许蚀刻停止层502用作用于蚀刻晶圆衬底112的硬掩模。例如,当晶圆衬底112是硅时,利用诸如氯气(Cl2)的氯基蚀刻剂对晶圆衬底112进行干等离子体蚀刻或利用氢氧化钾(KOH)或硝酸/氢氟酸(HNO3/HF)混合物对晶圆衬底112进行湿蚀刻。此外,选择性地蚀刻晶圆衬底112,其中,蚀刻停止在晶圆RDL 114处。
图8是示出RDL 108和114的氧化物层的蚀刻的截面图。在实施例中,使用包括氟化铵(NH4F)和氢氟酸的缓冲氧化物蚀刻(BOE)来蚀刻氧化物层。RDL 108和114的氧化物层中的导电元件110用作蚀刻停止层,从而允许将RDL 108和114蚀刻至不同的深度。蚀刻氧化物层将通孔开口702延伸至RDL 108和114中的导电元件110。在一些实施例中,通孔开口702延伸穿过上部导电元件110中的开口并且暴露下部导电元件110的表面。因此,单个通孔开口702可以暴露多个导电元件110的表面。此外,在一些实施例中,通孔开口702暴露管芯RDL108和晶圆RDL 114中的导电元件110。
图9是根据实施例的示出形成隔离层902的截面图。去除掩模504(见图7),并且在蚀刻停止层502上方形成共形的介电隔离层902。隔离层902延伸到每个通孔开口702内并且覆盖通孔开口702的侧壁,包括覆盖暴露在通孔开口702中的部分的晶圆衬底112。
在实施例中,例如,隔离层902是使用CVD或PECVD工艺由氮化硅形成的。在其他实施例中,隔离层902是由氧化物、另一氮化物、碳化物、氮氧化物、旋涂玻璃(SOG)或其他介电或绝缘材料形成的。隔离层902的厚度部分由将形成在通孔开口702中的通孔上的预定电压确定的。已经确定,在介于约500埃和约5000埃之间的厚度将提供导致大于约3.8伏的击穿电压的厚度。
图10是根据实施例的示出自对准间隔件1002的形成的截面图。例如,使用干等离子体蚀刻来蚀刻隔离层902(见图9),干等离子体蚀刻利用在氩气(Ar)、氦气(He)或其他环境中的氯气、六氟化硫、六氟化碳、氯气或其他蚀刻剂。在一些实施例中,例如,蚀刻剂提供为具有氧气(O2)、氮气(N2)或其他工艺气体以增大该蚀刻的选择性。在这样的蚀刻中,环境维持在介于约25℃和约150℃之间的温度下以及介于约10毫托和约200毫托之间的压力下。在一些实施例中,蚀刻是各向异性的,从而去除垂直方向上的材料。因此,该蚀刻从封装件的水平表面去除隔离层902的材料,从而留下位于封装件的侧壁表面上的间隔件1002。例如,设置在蚀刻停止层502上的隔离层902的部分被去除,而设置在通孔开口702的侧壁上的隔离层902的部分保留。这是由于隔离层902在垂直方向上的侧壁处的厚度大于在水平表面上的厚度。此外,导电元件110的顶面的部分在该蚀刻期间暴露。这是因为隔离层902的定向蚀刻降低了隔离层902的顶面,消除了隔离层902的横向部分,并且留下了垂直部分导致基本上从顶部方向去除隔离材料。
已经发现,自对准间隔件1002可以形成在通孔开口702内,并且间隔件1002的自对准特征使得间隔件1002形成在通孔开口702的侧壁上。间隔件1002将形成通孔开口702的侧壁的材料与形成在通孔开口702中的通孔绝缘。具体地,间隔件1002形成在通孔开口702的侧壁上,其中,通孔开口702穿过晶圆衬底112,其中,间隔件1002的外表面设置在通孔开口702的侧壁上,并且间隔件1002的内表面朝向通孔开口702的内部。间隔件1002允许导电通孔将形成在通孔开口702中,同时避免与晶圆衬底112和RDL 108和114的垂直表面的电接触。在一些实施例中,间隔件1002延伸至下面的导电部件110,将通孔开口702与通孔开口702的所有的侧壁屏蔽。此外,间隔件1002使导电元件110的横向表面的部分暴露在通孔开口702中,从而使得随后形成的通孔可以与导电元件110电接触。因此,一些间隔件延伸至晶圆衬底112的最底面下方并且进入到RDL108和114内,其中,间隔件1002的内表面从导电元件110连续地延伸至晶圆衬底112的顶面,或延伸在晶圆衬底的顶面上方。
在一些实施例中,当通孔开口702形成在上部导电元件110上方或穿过上部导电元件110至下部导电元件110时,通孔开口702具有上部,上部的宽度宽于通孔开口702的下部的宽度。在这样的实施例中,单独的间隔件1002形成在通孔开口702的上部和下部的侧壁上,其中,上部间隔件1002和下部间隔件1002横向间隔开以暴露上部导电元件110的横向表面。
图11是根据实施例的示出通孔开口702中的通孔1102的形成的截面图。由于在将管芯102接合到晶圆104之后形成通孔1102,因此,该工艺被称为后通孔工艺。在一些实施例中,延伸穿过诸如晶圆衬底112的衬底的通孔1102被称为衬底通孔(TSV)或者可选地被称为硅通孔(由于通孔延伸穿过硅衬底)。延伸穿过模塑料302的通孔702被称为介电通孔(TDV)。
在一些实施例中,在通孔开口702中形成阻挡层(为了清楚的原因未示出),其中,例如,通过CVD、PECVD或另一沉积工艺由钴(Co)、钽、钨、氮化钽(TaN)、氮化钛(TiN)等形成阻挡层。通过用诸如铜(Cu)、铝(Al)、铝铜合金(AlCu)、金、钛、钴、合金、或其他导电材料的导电材料填充通孔开口702来生成通孔1102。在一些实施例中,例如,通过电化学镀(ECP)、电镀、无电镀或其他工艺形成通孔。在这样的实施例中,在阻挡层上方或在间隔件和导电元件110上方通过例如原子层沉积来形成晶种层(未示出)。晶种层提供用于镀工艺的成核位点和增大形成通孔1102的镀的材料的均匀性。在一些实施例中,通孔1102的导电材料延伸在通孔开口702上方。例如,使用这种过填充以确保开口702被完全填充。通过研磨、CMP、抛光,蚀刻或其他降低工艺去除过量的材料。在形成通孔1102之后,通孔1102的顶面与蚀刻停止层502的顶面基本上平齐。在一些实施例中,研磨工艺去除蚀刻停止层502或降低晶圆衬底112的顶面。通孔1102延伸穿过晶圆衬底112以接触一个或多个导电元件110。间隔件1002将通孔1102与晶圆衬底112电绝缘,从而使得通过通孔1102发送的电信号不干扰晶圆衬底112中的有源器件。在一些实施例中,通孔1102延伸穿过晶圆衬底112、晶圆RDL 114和接合界面202以接触管芯RDL 108中的导电元件110。在这样的实施例中,位于管芯RDL 108上的导电元件110通过管芯RDL108电连接至管芯衬底106。因此,管芯衬底106和外部器件之间的连接或连接可以由封装件的晶圆侧形成。同样,在一些实施例中,通孔1102延伸穿过晶圆衬底112并且接触晶圆RDL 114中的导电元件110,晶圆RDL 114中的导电元件110电连接至晶圆衬底112。由此,电源或数据连接可以从管芯102或晶圆104通过晶圆衬底112提供至外部器件。
此外,在一些实施例中,晶圆104可以使用后通孔工艺电连接至管芯102。例如,晶圆RDL 114中的第一导电元件110可以通过通孔1102与管芯RDL 108中的第二导电元件110连接,通孔1102接触第一和第二导电元件110。因此,即使RDL108和114位于管芯102和晶圆104之间,可以在无需将管芯102接合至晶圆104之前形成诸如微凸块或焊球的离散连接件的情况下,提供外部电连接和管芯至晶圆连接。此外,后通孔工艺消除了在管芯至晶圆接合工艺过程中用于将晶圆与管芯对准的需求。
已经发现间隔件1002为晶圆上芯片结构提供更低成本和更简单的结构。此外,间隔件1002允许通孔的高宽比介于3和约10之间,从而增大了芯片间连接的密度。已经进一步发现,由于通孔1102延伸穿过晶圆衬底112,通孔1102可以布置为更规则地穿过封装件并且提供更异质的芯片堆叠件。通孔1102的规则布置也在随后处理或封装件安装期间提供改进的翘曲控制。
图12是示出顶部RDL绝缘层1202的截面图。在一些实施例中,在蚀刻停止层502上方形成诸如PBO、氧化硅、聚酰亚胺或其他绝缘材料的绝缘材料。在绝缘层1202中形成暴露通孔1102的一个或多个RDL开口1204。在一些实施例中,绝缘层1202是喷涂或旋涂的PBO,并且RDL开口1204是利用光刻工艺通过曝光和显影PBO形成的。在其他实施例中,通过CVD等沉积绝缘层1202和蚀刻、激光钻孔、铣削或以其他方式图案化绝缘层1202。
图13是根据实施例的示出在顶部RDL绝缘层1202中形成顶部RDL导电元件1302的截面图。例如,通过溅射、PVD、CVD、镀或其他沉积工艺在RDL开口1204中的绝缘层1202上方沉积诸如铜的导电材料。通过掩蔽和蚀刻或通过沉积之前掩蔽来图案化沉积的导电材料。虽然为了清楚起见,所示出的顶部RDL导电元件1302被示出为基本上垂直延伸,但是应当理解,在一些实施例中,顶部RDL导电元件1302具有横向延伸的部分以为随后形成的层或连接件提供期望的布局。
图14是示出形成额外的绝缘层和导电元件以形成顶部RDL1406的截面图。在堆叠件中具有导电元件1302的一个或多个顶部RDL绝缘层1202以在外部器件和通孔1102之间提供电连接。此外,在最上面的顶部RDL绝缘层1202上方形成保护层1402并且保护层1402具有暴露顶部RDL导电元件1302的开口。在一些实施例中,保护层1402是PBO、环氧树脂、氧化物、氮化物、碳化物、氮氧化物、聚酰亚胺或其他绝缘或保护材料并且根据以上描述被沉积和图案化。
图15是根据实施例的示出连接件1502的形成的截面图。一个或多个连接件1502安装在顶部RDL导电元件1302的暴露部分上。在一些实施例中,连接件1502是焊球、柱、导电凸块或其他导电连接件。连接件1502配置为允许将该封装件安装至诸如管芯、封装件、晶圆、PCB等的目标衬底。因此,晶圆104和管芯102通过连接件1502和通孔1102与目标衬底进行信号连接。然后,从该封装件去除载体402。
虽然,晶圆上芯片封装件被示出为使用后通孔工艺以形成通孔1102,通孔1102从封装件的晶圆侧延伸穿过晶圆衬底112至RDL 108和114,但是应当理解,所公开的实施例不限制于这样的布置。在其他实施例中,通孔1102形成为从封装件的管芯侧穿过管芯衬底106和模塑料302至RDL108和114。此外,在一些实施例中,从封装件的晶圆侧和管芯侧形成通孔1102。
此外,上述公开的实施例不限于上述结构和步骤的顺序。图16至图20示出了根据实施例的在形成具有部分高度自对准间隔件的晶圆上芯片结构中的中间处理步骤的截面图。
图16示出了根据实施例的在封装件的模塑料1622中掩蔽和蚀刻通孔开口1618的截面图。例如,如上所述,管芯1602和晶圆1604接合在一起。管芯1602和晶圆1604分别具有管芯衬底1612和晶圆衬底1620,并且衬底1612和1620具有一个或多个有源器件。管芯RDL1614和晶圆RDL1616设置在相应的衬底1612和1620上并且包括其中设置有导电元件1610的介电层,其中一些导电元件1610与相应的衬底1612和1620中的有源器件接触。管芯1602和晶圆1604接合在一起,从而使得管芯RDL 1614与晶圆RDL1616接触并且形成接合界面1628。在一些实施例中,如上所述,采用直接表面接合、金属至金属接合或混合接合来接合管芯1602和晶圆1604。模塑料1622形成在管芯1602上方,并且在一些实施例中,延伸到管芯1602上方。蚀刻停止层1606形成在模塑料1622上方。
掩模1608沉积在蚀刻停止层1606上方并且图案为具有设置在一个或多个导电元件1610上方的开口。使用控制通孔开口1618的位置的掩模1608,穿过模塑料1622蚀刻通孔开口1618。在实施例中,通孔开口1618延伸穿过模塑料1622,并且通孔开口1618设置在管芯衬底1612上方并且延伸穿过管芯衬底1612至管芯RDL 1614。邻近但未设置在管芯衬底1612上方的通孔开口1618部分地延伸穿过模塑料1622。
图17是根据实施例的示出形成隔离层1702的截面图。去除掩模1608(见图16),并且在蚀刻停止层1606上方形成共形的介电隔离层1702。在实施例中,根据以上描述形成隔离层1702。隔离层1702延伸到每个通孔开口1618内并且覆盖通孔开口1618的侧壁,包括覆盖暴露在通孔开口1618中的部分的管芯衬底1612。此外,隔离层1702覆盖例如管芯RDL1614和模塑料1622的暴露在开口1618的底部处的横向表面。
图18是根据实施例的示出部分高度自对准间隔件1802的形成的截面图。在一些实施例中,如上所述,蚀刻隔离层1702(见图17)。蚀刻暴露间隔件1802之间的通孔开口1618中的管芯RDL 1614的部分横向表面。此外,对于邻近但没有设置在管芯RDL 1614上方的通孔开口1618而言,该蚀刻暴露形成通孔开口1618的底部的模塑料1622的表面。
图19示出了根据实施例的在形成间隔件1802之后的第二蚀刻的截面图。在一些实施例中,如结合图8的以上描述,选择性地蚀刻隔离层1702。通孔开口1618延伸至下面的RDL1614和1616中的导电元件1610,从而暴露导电元件1610的上表面。在这样的实施例中,间隔件1802只部分地延伸穿过通孔开口1618,其中,间隔件1802的底面设置在管芯RDL1614上或设置在模塑料1622内。然而,间隔件1802设置在管芯衬底1612的侧壁上的通孔开口1618中,将管芯衬底1612与通孔开口1618和随后形成的通孔电绝缘。已发现,部分高度自对准间隔件1802允许利用单个掩模蚀刻管芯RDL1614和RDL1616。在第二蚀刻期间,间隔件1802掩蔽管芯RDL1614的侧壁。生成的通孔开口1618具有下部,下部的侧壁与间隔件1802的内表面基本上共面、平齐或甚至对准。在一些实施例中,其中,模塑料1622延伸在管芯衬底1612的顶面上方,间隔件1802从大约管芯衬底1612的底面延伸至模塑料1622的顶面或延伸至模塑料1622的顶面之上。
图20示出了根据实施例的通孔2002的形成的截面图。在一些实施例中,如结合图11的以上描述,在通孔开口1618(见图17)中形成通孔2002。通孔2002通过间隔件1802与管芯衬底1612绝缘,并且从封装件的顶面延伸穿过管芯衬底1612至RDL1614和1616中的导电元件1610。
虽然,所描述的实施例被示出为具有将通孔2002与管芯衬底1612绝缘的部分高度间隔件1802,但是该实施例不限制于那些描述。例如,在一些实施例中,部分高度间隔件1802设置在晶圆衬底1620中,其中,通孔2002从封装件的晶圆侧延伸至RDL1614和1616。
图21至图30示出了根据实施例的在使用双镶嵌后通孔工艺形成晶圆上芯片结构中的中间处理步骤的截面图。图21示出了在接合至晶圆2104的管芯2102上方形成模塑料2116的截面图。管芯2102和晶圆2104分别具有管芯衬底2106和晶圆衬底2112,并且管芯衬底2106和晶圆衬底2112具有一个或多个有源器件。管芯RDL2108和晶圆RDL2114设置在相应的衬底2106和2112上并且包括其中设置有导电元件2110的介电层,其中一些导电元件2110与相应的衬底2106和2112中的有源器件接触。如以上描述,接合管芯2102和晶圆2104,从而使得管芯RDL 2108与晶圆RDL2114接触并且形成接合界面2118。如以上描述,在管芯2102和晶圆2104上方形成模塑料2116,并且在一些实施例中,模塑料2116延伸在管芯2102上方。
图22示出了根据实施例的在封装件上形成第一掩模2202的截面图。在这样的实施例中,第一掩模2202形成在模塑料2116上方并且被图案化以形成开口2204。在一些实施例中,第一掩模2202是被沉积,曝光和显影的光刻胶。在第一掩模2202中的开口2204在RDL2108和2114中的导电元件2110上方对准。已经发现,用于形成通孔开口的双镶嵌技术允许蚀刻停止层的消除和蚀刻停止层的相关蚀刻。在这样的实施例中,第一掩模2202设置在模塑料2116上。
图23示出了根据实施例的蚀刻管芯衬底2106的截面图。通孔开口2302形成为穿过模塑料2116以及穿过管芯衬底2106以暴露管芯RDL 2108。在实施例中,如以上描述,蚀刻通孔开口2302。邻近但没有设置在管芯衬底2106上方的通孔开口2302部分地延伸穿过模塑料2116。
图24示出了根据实施例的应用第二掩模2402的截面图。在一些实施例中,在穿过管芯衬底2106进行通孔开口2302的第一蚀刻之后,去除第一掩模2202。在衬底上方形成的第二掩模2402延伸到通孔开口2302内。在一些实施例中,第二掩模2402是通过例如旋涂、喷涂等沉积的光刻胶。
图25示出了根据实施例的图案化第二掩模2402的截面图。在一些实施例中,曝光和显影第二掩模2402以使第二掩模2402图案化为具有第二掩模开口2502。在一些实施例中,第二掩模开口2502比第一蚀刻之后的通孔开口2302宽,其中,第二掩模开口2502设置在通孔开口2302上方。此外,在一些实施例中,第二掩模开口2502限定用于金属线的开口,金属线从通孔开口横向延伸以提供至随后在通孔开口2302的下部中形成的通孔的电连接。
图26示出了根据实施例的蚀刻RDL 2108和2114的截面图。蚀刻RDL2108和2114并且去除第二掩模2402。在一些实施例中,使用时间模式蚀刻工艺,从而使得蚀刻工艺蚀刻一预定深度。利用第二掩模的蚀刻导致通孔开口2302的上部的宽度宽于通孔开口2302的下部的宽度。时间模式蚀刻控制通孔开口2302的上部的深度,并且导致通孔开口2302的下部向下延伸以暴露出下面的导电元件2110。
图27是根据实施例的示出隔离层2702的形成的截面图。共形的介电隔离层2702形成在模塑料2116上方并且延伸到通孔开口2302内。在实施例中,如以上描述,形成隔离层2702。隔离层2702延伸到每个通孔开口2308内并且覆盖通孔开口2308的侧壁,包括覆盖暴露在通孔开口2302中的部分的管芯衬底2106。
图28是根据实施例的示出自对准间隔件2802的形成的截面图。在一些实施例中,如上所述,蚀刻隔离层2702(见图27),去除隔离层2702的横向部分并且留下位于通孔开口2302的侧壁上的间隔件2802。间隔件2802将管芯衬底2106与通孔开口2302绝缘并且暴露导电元件2110的顶面的部分。在一些双镶嵌实施例中,单独的间隔件2802形成在通孔开口2302的上部和下部中,上部和下部间隔件2802彼此横向分离并且暴露模塑料2116的横向表面。此外,下部间隔件2802从管芯衬底2106之上的RDL2108和2114中的导电元件2110延伸至模塑料2116内。
图29是根据实施例的示出在通孔开口2302中的通孔2902的形成。在一些实施例中,如上描述,形成通孔2902。通孔2902通过间隔件2802与管芯衬底2106绝缘并且从模塑料2116的顶面延伸至导电元件2110。在一些实施例中,通孔2902的顶部横向延伸穿过模塑料2116的顶部,从而在模塑料2116中形成用于顶部RDL的第一层。在第二蚀刻之后形成间隔件2802允许在通孔开口2302内形成全高度间隔件。在一些实施例中,在通孔开口2302中形成阻挡层、晶种层和金属层,和然后通过CMP等进行降低。由此,形成顶部RDL的第一层的导电元件的离散步骤形式可以合并到通孔形成工艺内,从而降低成本和增加产量。
图30是根据实施例的示出顶部RDL 3006和连接件3008的形成的截面图。在一些实施例中,如以上描述,形成具有一个或多个顶部RDL绝缘层3002和导电元件3004的顶部RDL3006。此外,如以上描述,在顶部RDL 3006上方形成保护层3010和一个或多个连接件3008。虽然顶部RDL3006中的导电元件3004被示出为在通孔2902的下部上方直接对准,但是应当理解,在一些实施例中,通孔2902的上部从通孔的下部横向延伸。在这样的实施例中,顶部RDL导电元件3004对准在通孔2902的下部的外侧。
图31A是根据一些实施例的示出形成晶圆上芯片结构的方法3100的流程图。在框3102中,首先将一个或多个管芯接合至晶圆,或将两个晶圆接合在一起。在框3104中,在接合的管芯和晶圆上方形成模塑料。在一些实施例中,在框3106中反转封装件和在框3108中将反转的封装件安装至载体。在框3110中,通过CMP、研磨、抛光或以其他方式降低管芯、晶圆或模塑料来降低封装件。在一些实施例中,在框3112中形成蚀刻停止层。在框3114中形成和图案化第一掩模以及在框3116中图案化蚀刻停止层。在框3118中蚀刻管芯或晶圆的衬底以及在框3126中蚀刻晶圆和管芯之间的RDL。在框3122中形成隔离层并且在框3124中蚀刻隔离层以形成间隔件。在框3134中用导电材料填充通过蚀刻形成的通孔开口。在框3136中,形成顶部RDL。在框3138中,在一些实施例中,在顶部RDL上方形成保护层。在框3140中,在顶部RDL上方形成与顶部RDL的导电元件接触的连接件。
图31B是根据其他实施例的示出形成晶圆上芯片结构的方法3160的流程图。在这样的实施例中,通过类似于以上描述的工艺形成部分高度间隔件。在一些实施例中,跳过反转封装件和将封装件安装至载体的步骤。此外,在框3118中蚀刻衬底之后,在框3122中形成隔离层。在框3124中蚀刻隔离层,和在框3126中,将间隔件用作用于蚀刻RDL的掩模蚀刻RDL。在框31314中填充由蚀刻形成的通孔开口,以及如以上描述,继续该工艺。
图31C是根据其他实施例的示出形成晶圆上芯片结构的方法3180的流程图。在这样的实施例中,双镶嵌技术用于形成具有上部的通孔,上部宽于通孔的下部或从通孔的下部横向延伸。在一些实施例中,在框3118中蚀刻衬底,并且在框3120中形成并且图案化第二掩模。在框3128中,利用限定通孔开口的上部的第二掩模来蚀刻RDL。在框3122中,形成隔离层,以及如以上描述,继续该工艺。
因此,根据实施例中,一种封装件包括设置在第一半导体衬底的第一侧上的第一重分布层(RDL)和设置在第二半导体衬底上的第二RDL,其中,第一RDL接合至第二RDL。第一导电元件设置在第一RDL和第二RDL中。第一通孔从一个或多个第一导电元件延伸穿过第一半导体衬底至与第一侧相对的第一半导体衬底的第二侧。第一间隔件插入在第一半导体衬底和第一通孔之间并且每个第一间隔件从相应的一个第一导电元件延伸穿过第一半导体衬底。
根据另一个实施例,一种封装件包括:具有设置在第一衬底的第一侧上的第一重分布层(RDL)的第一衬底,其中,第一RDL具有设置在第一RDL中的一个或多个第一导电元件。管芯具有第二衬底和设置在第二衬底的第一侧上的第二RDL,其中,第二RDL具有设置在第二RDL中的一个或多个第二导电元件。第一RDL接合至第二RDL。模塑料设置在第一RDL上方和管芯上方,模塑料的第一部分延伸在与第一侧相对的第二衬底的第二侧上方。间隔件设置在第二衬底中,每个间隔件从第二衬底的至少第一侧延伸穿过模塑料的第一部分。通孔延伸穿过模塑料的第一部分和延伸穿过第二衬底,每个通孔与一个或多个第一导电元件或者一个或多个第二导电元件的至少一个接触,并且每个通孔通过间隔件的相应一个与第二衬底电绝缘。
根据实施例的一种方法包括:提供第一衬底,第一衬底具有设置在第一衬底上的第一重分布层(RDL),其中,导电元件设置在第一RDL中;以及提供第二衬底,第二衬底具有设置在第二衬底上的第二RDL,其中,第一RDL接合至第二RDL,并且导电元件设置在第二RDL中。穿过至少第一衬底蚀刻第一通孔开口以及在第一衬底上方形成延伸至第一通孔开口内的隔离层。蚀刻隔离层,蚀刻在第一通孔开口的侧壁上形成间隔件。至少一个间隔件延伸穿过第一衬底并且具有设置在至少一个导电元件上的底面。在第一通孔开口中形成电连接至至少一个导电元件的第一通孔。第一通孔从一个导电元件延伸穿过第一衬底至与第一RDL相对的第一衬底的至少顶侧。一个或多个间隔件插入在第一衬底和第一通孔之间并且将第一通孔与第一衬底电绝缘。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (19)
1.一种封装件,包括:
第一重分布层,设置在第一半导体衬底的第一侧上;
第二重分布层,设置在第二半导体衬底上,其中,所述第一重分布层接合至所述第二重分布层;
第一导电元件,设置在所述第一重分布层和所述第二重分布层中;
第一通孔,从一个或多个所述第一导电元件延伸穿过所述第一半导体衬底至与所述第一侧相对的所述第一半导体衬底的第二侧,所述第一通孔的至少第一个与设置在所述第一重分布层中的一个所述第一导电元件接触,并且其中,所述第一通孔的至少第二个与设置在所述第二重分布层中的一个所述第一导电元件的接触;以及
第一间隔件,插入在所述第一半导体衬底和所述第一通孔之间,并且每个所述第一间隔件从相应的一个所述第一导电元件延伸穿过所述第一半导体衬底。
2.根据权利要求1所述的封装件,其中,所述第一通孔的至少一个与所述第一重分布层中的所述第一导电元件的第一个以及所述第二重分布层中的所述第一导电元件的第二个均接触。
3.根据权利要求1所述的封装件,还包括:
模塑料,设置在所述第二重分布层上方以及所述第一重分布层和所述第一半导体衬底周围。
4.根据权利要求3所述的封装件,还包括:
第二通孔,邻近所述第一半导体衬底并且从一个或多个所述第一导电元件延伸穿过所述模塑料。
5.根据权利要求4所述的封装件,其中,所述第一通孔延伸穿过所述第一重分布层的至少一部分,并且其中,所述第二通孔延伸穿过所述第二重分布层的至少一部分。
6.根据权利要求3所述的封装件,还包括:
顶部重分布层,形成在所述第一半导体衬底的所述第二侧上方,所述顶部重分布层具有设置在一个或多个介电层中的第二导电元件,并且其中,所述第一通孔的每个均与所述第二导电元件的相应一个电接触。
7.根据权利要求3所述的封装件,其中,所述模塑料的第一部分在所述第一半导体衬底的所述第二侧上方延伸,并且其中,所述第一通孔延伸穿过所述模塑料的第一部分。
8.一种封装件,包括:
第一衬底,具有设置在所述第一衬底的第一侧上的第一重分布层,所述第一重分布层具有设置在所述第一重分布层中的一个或多个第一导电元件;
管芯,具有第二衬底和设置在所述第二衬底的第一侧上的第二重分布层,所述第二重分布层具有设置在所述第二重分布层中的一个或多个第二导电元件,其中,所述第一重分布层接合至所述第二重分布层;
模塑料,设置在所述第一重分布层上方和所述管芯上方,所述模塑料的第一部分在所述第二衬底的与所述第一侧相对的第二侧上方延伸;
间隔件,设置在所述第二衬底中,每个所述间隔件从所述第二衬底的至少所述第一侧延伸穿过所述模塑料的第一部分;以及
通孔,延伸穿过所述模塑料的第一部分并且延伸穿过所述第二衬底,每个所述通孔与所述一个或多个第一导电元件或者所述一个或多个第二导电元件的至少一个接触,每个所述通孔通过所述间隔件的相应一个与所述第二衬底电绝缘,所述通孔的至少第一个与设置在所述第一重分布层中的一个所述第一导电元件接触,并且其中,所述通孔的至少第二个与设置在所述第二重分布层中的一个所述第二导电元件的接触。
9.根据权利要求8所述的封装件,其中,每个所述通孔的下部延伸穿过所述第二重分布层的一部分并且延伸穿过所述第二衬底至所述模塑料的第一部分内;
其中,每个所述通孔的上部设置在所述模塑料的第一部分中;以及
其中,每个所述通孔的上部具有大于所述通孔的相应一个的所述下部的宽度。
10.根据权利要求9所述的封装件,还包括:
第三重分布层,设置在所述模塑料上,所述第三重分布层具有设置在所述第三重分布层中的第三导电元件,每个所述第三导电元件与所述通孔的相应一个电接触。
11.根据权利要求10所述的封装件,其中,所述间隔件的第一间隔件设置在邻近所述通孔的相应一个的顶部的所述模塑料的第一部分中。
12.根据权利要求8所述的封装件,其中,一个或多个所述间隔件设置在所述第二重分布层中。
13.根据权利要求8所述的封装件,其中,至少一个所述通孔与所述第一导电元件的一个以及所述第二导电元件的至少一个接触。
14.一种形成晶圆上芯片结构的方法,包括:
提供第一衬底,所述第一衬底具有设置在所述第一衬底上的第一重分布层,其中,第一导电元件设置在所述第一重分布层中;
提供第二衬底,所述第二衬底具有设置在所述第二衬底上的第二重分布层,所述第一重分布层接合至所述第二重分布层,其中,所述第一导电元件设置在所述第二重分布层中;
穿过至少所述第一衬底蚀刻出第一通孔开口;
在所述第一衬底上方形成延伸至所述第一通孔开口内的隔离层;
蚀刻所述隔离层,所述蚀刻在所述第一通孔开口的侧壁上形成间隔件,至少一个所述间隔件延伸穿过所述第一衬底并且具有设置在至少一个所述第一导电元件上的底面;以及
在所述第一通孔开口中形成电连接至至少一个所述第一导电元件的第一通孔;
其中,所述第一通孔从一个所述第一导电元件延伸穿过所述第一衬底至所述第一衬底的与所述第一重分布层相对的至少顶侧,所述第一通孔的至少第一个与设置在所述第一重分布层中的一个所述第一导电元件接触,并且其中,所述第一通孔的至少第二个与设置在所述第二重分布层中的一个所述第一导电元件的接触;以及
其中,一个或多个所述间隔件插入在所述第一衬底和所述第一通孔之间,并且将所述第一通孔与所述第一衬底电绝缘。
15.根据权利要求14所述的形成晶圆上芯片结构的方法,还包括:
在所述第二重分布层上方形成模塑料,从而使得所述第二重分布层设置在所述模塑料和所述第二衬底之间;
穿过至少所述模塑料蚀刻出第二通孔开口;以及
在所述第二通孔开口中形成电连接至至少一个所述第一导电元件的第二通孔;
其中,在所述第一衬底周围形成所述模塑料;以及
其中,在同一工艺步骤中形成所述第一通孔和所述第二通孔。
16.根据权利要求15所述的形成晶圆上芯片结构的方法,其中,所述模塑料的第一部分在所述第一衬底上方延伸,并且其中,所述第一通孔延伸穿过所述模塑料的第一部分。
17.根据权利要求16所述的形成晶圆上芯片结构的方法,还包括:
蚀刻至所述第一重分布层内以使所述第一通孔开口延伸穿过所述第一重分布层的至少一部分;
其中,蚀刻出所述第一重分布层开口包括蚀刻所述模塑料的第一部分以形成所述第一通孔开口的上部,所述第一通孔开口的上部比所述第一通孔开口的下部具有更大的宽度;以及
其中,在蚀刻所述第一重分布层之后,实施形成所述隔离层。
18.根据权利要求17所述的形成晶圆上芯片结构的方法,其中,蚀刻所述隔离层在所述第一通孔开口的上部中形成所述间隔件的至少第一个,所述间隔件的至少第一个与所述第一通孔开口的下部中的所述间隔件的第二个间隔开。
19.根据权利要求15所述的形成晶圆上芯片结构的方法,还包括:
在所述模塑料上形成第三重分布层;以及
在所述第三重分布层上形成连接件,所述连接件通过所述第三重分布层电连接至所述第一通孔。
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