CN107622992B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN107622992B
CN107622992B CN201610555077.4A CN201610555077A CN107622992B CN 107622992 B CN107622992 B CN 107622992B CN 201610555077 A CN201610555077 A CN 201610555077A CN 107622992 B CN107622992 B CN 107622992B
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dielectric layer
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CN107622992A (zh
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魏铭德
林俊贤
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该制作方法包括：首先提供一基底，然后形成一第一介电层于基底上，其中第一介电层中具有一第一导体。接着形成一第二介电层于第一介电层上，去除部分第二介电层以形成一接触洞，然后再进行一横向蚀刻制作工艺扩张该接触洞以形成一漏斗状开口。之后形成一金属层并填满漏斗状开口，再平坦化金属层以形成一第二导体。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作接触插塞电熔丝的方法。
背景技术
随着半导体制作工艺的微小化以及复杂度的提高，半导体元件也变得更容易受各式缺陷或杂质所影响，而单一金属连线、二极管或晶体管等的失效往往即构成整个芯片的缺陷。因此为了解决这个问题，现行技术便会在集成电路中形成一些可熔断的连接线(fusible links)，也就是熔丝(fuse)，以确保集成电路的可利用性。
一般而言，熔丝是连接集成电路中的冗余电路(redundancy circuit)，一旦检测发现部分电路具有缺陷时，这些连接线就可用于修复(repairing)或取代这些有缺陷的电路。另外，目前的熔丝设计还可以提供编程(programming elements)的功能，以使各种客户可依不同的功能设计来编程电路。而从操作方式来说，熔丝大致分为热熔丝和电熔丝(eFuse)两种。所谓热熔丝，是通过一激光切割(laser zip)的步骤来切断；至于电熔丝则是利用电致迁移(electro-migration)的原理使熔丝出现断路，以达到修补的效果或编程的功能。此外，半导体元件中的电熔丝可为例如多晶硅电熔丝(poly efuse)、MOS电容反熔丝(MOS capacitor anti-fuse)、扩散电熔丝(diffusion fuse)、接触插塞电熔丝(contactefuse)、接触插塞反熔丝(contact anti-fuse)等等。
现行通常利用例如双镶嵌等制作工艺来制作用来当作电熔丝的金属导线或接触插塞。然而，依据此方式所形成的导线容易在导线中形成气室(void)并影响电熔丝的效能。因此如何改良现行制作工艺来确保电熔丝的品质即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成一第一介电层于基底上，其中第一介电层中具有一第一导体。接着形成一第二介电层于第一介电层上，去除部分第二介电层以形成一接触洞，然后再进行一横向蚀刻制作工艺扩张该接触洞以形成一漏斗状开口。之后形成一金属层并填满漏斗状开口，再平坦化金属层以形成一第二导体。
本发明另一实施例公开一种半导体元件，其包含：一基底；一第一介电层设于基底上；以及一第一导体设于第一介电层中，其中第一导体为漏斗状。
附图说明
图1至图5为本发明较佳实施例制作一接触插塞电熔丝的方法示意图；
图6为本发明较佳实施例从另一角度所视的接触插塞电熔丝的结构示意图；
图7为本发明一实施例的接触插塞电熔丝的整体架构图；
图8为本发明一实施例的接触插塞电熔丝的整体架构图；
图9为图7的接触插塞电熔丝的上视图；
图10为本发明一实施例的接触插塞电熔丝的整体架构图图。
主要元件符号说明
12 基底 14 层间介电层
16 介电层 18 介电层
20 导体 22 阻障层
24 金属层 26 停止层
28 介电层 30 介电层
32 第一掩模层 34 图案化第一掩模层
36 第二掩模层 38 有机介电层
40 含硅硬掩模与抗反射层 42 图案化光致抗蚀剂
44 接触洞 46 漏斗状开口
48 阻障层 50 金属层
52 导体 54 第一部分
56 第二部分 58 部分
60 部分 62 第一斜率
64 第二斜率 66 第三斜率
68 第二斜率
72 沟槽导体 74 接触洞导体
76 浅沟隔离 78 多晶硅栅极
80 掺杂区 82 接触插塞电熔丝
84 沟槽导体 86 接触洞导体
88 金属内连线结构
A 距离 B 距离
具体实施方式
请参照图1至图5，图1至图5为本发明较佳实施例制作一用来作为电熔丝的接触插塞或导线的方法示意图。如图1所示，首先提供一基底12，例如一硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。基底上可设有例如金属氧化物半导体晶体管(图未示)的主动元件，其可包含栅极结构、间隙壁、源极/漏极区域、金属硅化物以及外延层等标准晶体管组成。然后形成一层间介电层14于基底12上并覆盖金属氧化物半导体晶体管。
接着依序形成介电层16与介电层18于基底12上，并形成一导体20镶嵌于介电层18、介电层16以及层间介电层14中，其中导电20上表面较佳切齐介电层18上表面，而导体20下表面则可通过其他导体(图未示)连接基底12上的掺杂区或栅极结构，例如前述金属氧化物半导体晶体管的源极/漏极区域或栅极结构。在本实施例中，介电层16较佳为一有机介电材料层(organic dielectric coating,ODC)，介电层18较佳为一超低介电常数(ultralow-k,ULK)介电层，其中介电层18的厚度较佳介于650埃至850埃，或最佳约750埃。导体20较佳为一沟槽导体(trench conductor)或接触洞导体(via conductor)，其可包含一阻障层22与一金属层24，其中阻障层22可选自由钛(Ti)、氮化钛(TiN)、钽(Ta)以及氮化钽(TaN)所构成的群组，而金属层24可选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等所构成的群组，但不局限于此。
然后依序形成一停止层26、一介电层28、一介电层30以及一第一掩模层32于介电层18上并完全覆盖导体20，在本实施例中，停止层26较佳由氮碳化硅(silicon carbonnitride,SiCN)所构成，介电层28较佳由超低介电常数介电层所构成，介电层30较佳由氮氧化硅(silicon oxynitride,SiON)所构成，而第一掩模层32可选自由钛(Ti)以及氮化钛(TiN)所构成的群组。其中本实施例的第一掩模层32虽以单层为例，但又可依据产品需求为一复合层，例如可更细部包含一由钛所构成的掩模层以及另一由氮化钛所构成的掩模层，此实施例也属本发明所涵盖的范围。
如图2所示，接着先利用一含氯气体对第一掩模层32进行一蚀刻制作工艺，以于第一掩模层32中形成一开口(图未示)暴露介电层30表面并同时形成一图案化第一掩模层34。然后形成一第二掩模层36于图案化第一掩模层34上并填满开口，其中第二掩模层36较佳包含一有机介电层(organic dielectric layer,ODL)38、一含硅硬掩模与抗反射(silicon-containing hard mask bottom anti-reflective coating,SHB)层40以及一图案化光致抗蚀剂42。
随后如图3所示，利用图案化光致抗蚀剂42为掩模进行一蚀刻制作工艺，利用一含氟气体去除部分SHB层40、部分ODL 38、部分介电层30、部分介电层28以及部分停止层26以形成一接触洞44并同时暴露出部分导体20表面。之后再去除图案化光致抗蚀剂42、SHB层40以及ODL 38并暴露出图案化第一掩模层34。
如图4所示，然后利用图案化第一掩模层34为掩模进行一横向蚀刻制作工艺，扩张原本的接触洞44以形成一约略漏斗状开口46。值得注意的是，本实施例利用横向蚀刻方式来扩大接触洞44的手段主要取决于两个条件，其中一者是选用包含氮气以及/或氦气所构成的蚀刻气体来进行上述横向蚀刻制作工艺。
除此之外，本实施例较佳以上述蚀刻气体进行横向蚀刻的同时调整蚀刻制作工艺的偏差值(etching bias)，例如可通过调整射频功率(RF power)来控制漏斗状开口所形成的大小与角度。在本实施例中，可调整的射频功率较佳介于1000瓦至2000瓦，但不局限于此。整体而言，通过上述蚀刻气体成分来进行上述横向蚀刻以及/或搭配调整蚀刻所需的射频功率，本发明可使原本呈现约略倾斜但平坦的接触洞侧壁以上下不均匀方式向外扩张，进而形成如图中所示约为漏斗状的开口。
之后如图5所示，依序形成一阻障层48以及一金属层50并填满漏斗状开口46，然后搭配进行一平坦化制作工艺，例如利用化学机械研磨制作工艺去除部分金属层50、部分阻障层48、图案化第一硬掩模32以及介电层30，以形成一接触插塞或导体52于介电层28与停止层26内。其中阻障层48可选自由钛(Ti)、氮化钛(TiN)、钽(Ta)以及氮化钽(TaN)所构成的群组，而金属层50可选自由钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等所构成的群组，但不局限于此。至此即完成本发明较佳实施例的一接触插塞电熔丝的制作。
请继续参照图5，图5为本发明较佳实施例的一接触插塞电熔丝的结构示意图。如图5所示，本发明的接触插塞电熔丝主要包含一导体52镶嵌于介电层28与介电层26中以及另一导体20镶嵌于介电层18、停止层16及层间介电层14中。从细部来看，导体主要包含一第一部分54与第二部分56，其中第一部分54镶嵌于停止层26中，第二部分56镶嵌于第一介电层28中，且第二部分56又更细部包含部分58与部分60。在本实施例中，由部分58的上表面至停止层26上表面的距离A较佳介于750埃至850埃或最佳约800埃，而由部分60下表面至介电层28上表面的距离B较佳介于950埃至1050埃或最佳约1000埃。
更具体而言，设在停止层26内的第一部分54包含一第一斜率62，设在介电层28内的第二部分56则包含一第二斜率64与一第三斜率66。在本实施例中，第一斜率62不同于第二斜率64且第二斜率64不同于第三斜率66，或是第一斜率62、第二斜率64与第三斜率66三者均不相同。在本实施例中，第一斜率62相对于一水平面的夹角较佳介于80度至90度，或更佳约80度，第二斜率64相对于一水平面的夹角较佳介于30度至50度，或更佳约40度，第三斜率66相对于一水平面的夹角较佳介于85度至90度，或更佳约85度。
请继续参照图6，图6为本发明较佳实施例的接触插塞电熔丝从另一角度所视的结构示意图。如图6所示，相较于图5中接触插塞电熔丝第二部分56中的第二斜率64为左右对称，图6中若从另一角度来看接触插塞电熔丝第二部分56的第二斜率64又可呈现左右不对称的态样。更具体而言，靠近整个电熔丝尾端部分的第二斜率68相对于一水平面的夹角较佳略小于另一侧第二斜率64相对于一水平面的夹角。例如在本实施例中，第二斜率68相对于一水平面的夹角较佳介于30度至50度，或更佳约40度，而第二斜率64相对于一水平面的夹角较佳介于40度至60度，或更佳约50度。
请参照图7至图9，图7与图8为本发明不同实施例的接触插塞电熔丝的整体架构图，而图9为图7的接触插塞电熔丝的上视图。其中前述图5的结构即为图9沿着切线AA’方向所视的剖面示意图，而图6的结构即为图9沿着切线BB’方向所视的剖面示意图。
如图7至图9所示，本发明所公开的接触插塞电熔丝主要包含沟槽导体72与接触洞导体74设于基底12或浅沟隔离76上，其中电熔丝的沟槽导体72即为前述图5或图6实施例中的部分60，而接触洞导体74则为连接部分60的部分58。以图7的架构来看，接触洞导体74可选择实体连接浅沟隔离76上的多晶硅栅极78，例如不同金属氧化物半导体晶体管的栅极结构。而以图8的架构来看，接触洞导体74可选择连接基底12上的掺杂区80，例如不同金属氧化物半导体晶体管的源极/漏极区域，这两种实施例态样均属本发明所涵盖的范围。
请再参照图10，图10为本发明一实施例的接触插塞电熔丝的整体架构图图。如图10所示，相较于图7与图8中仅以单一接触洞导体连接多晶硅栅极78或掺杂区80，本实施例的接触插塞电熔丝82较佳包含多层沟槽导体与多层接触洞导体，其中最上层的沟槽导体即为图6所示的部分60与部分58，而部分58更通过下层的沟槽导体84与接触洞导体86连接多晶硅栅极78或掺杂区。另外接触插塞电熔丝82两侧可伴随形成其他依据标准双镶嵌制作工艺的金属内连线结构88，且金属内连线结构88较佳包含不具漏斗状的沟槽导体84与接触洞导体86。
综上所述，本发明主要以双镶嵌制作工艺制作接触插塞电熔丝时利用新的蚀刻气体成分并搭配调整蚀刻时所需的射频功率，由此形成约略漏斗状的沟槽或接触洞开口，并于后续形成具有漏斗状的导体结构。一般而言，以现行双镶嵌制作工艺所制作出的接触洞导体或导线容易因气室(void)的存在使电熔丝过于容易断裂，而依据上述制作工艺方式所制作出具有漏斗状导体结构的接触插塞电熔丝即可改善此缺点并确保电熔丝的品质。

Claims (16)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成第二介电层于该基底上；
形成第一导体在该第二介电层中；
形成停止层于该第一导体和该第二介电层上；
形成一第一介电层于该停止层上；
形成一接触洞于该停止层和该第一介电层内，并暴露出该第一导体；
进行一横向蚀刻制作工艺扩张该接触洞以形成一漏斗状开口；
形成一金属层于该漏斗状开口；以及
平坦化该金属层以形成一第二导体，该第二导体包含设在该停止层内的第一部分和设在该第一介电层内的第二部分，其中该第一部分具有第一侧壁，该第二部分具有第二侧壁和第三侧壁，该第一侧壁相对于水平面的夹角介于80度至90度，该第二侧壁相对于水平面的夹角介于30度至50度，该第三侧壁相对于水平面的夹角介于85度至90度。
2.如权利要求1所述的方法，其中该第一导体的上表面切齐该第二介电层的上表面。
3.如权利要求1所述的方法，另包含：
形成一第一掩模层于该第一介电层上；
进行一第一蚀刻制作工艺图案化该第一掩模层以形成一图案化第一掩模层；
形成一第二掩模层于该图案化第一掩模层上；以及
进行一第二蚀刻制作工艺以于该第二掩模层及该第一介电层中形成该接触洞。
4.如权利要求3所述的方法，另包含利用一含氯气体进行该第一蚀刻制作工艺。
5.如权利要求3所述的方法，另包含利用一含氟气体进行该第二蚀刻制作工艺。
6.如权利要求1所述的方法，其中进行该横向蚀刻制作工艺的蚀刻气体选自由氮气以及氦气所构成的群组。
7.如权利要求1所述的方法，其中该第二导体为漏斗状。
8.如权利要求7所述的方法，其中该第二导体包含一第一斜率以及一第二斜率，其中该第一斜率不同于该第二斜率。
9.一种半导体元件，包含：
基底；
停止层，设于该基底上；
第一介电层，设于该停止层上；以及
第一导体，设于该停止层和该第一介电层中，其中该第一导体为漏斗状，该第一导体包含设在该停止层内的第一部分和设在该第一介电层内的第二部分，其中该第一部分具有第一侧壁，该第二部分具有第二侧壁和第三侧壁，该第一侧壁相对于水平面的夹角介于80度至90度，该第二侧壁相对于水平面的夹角介于30度至50度，该第三侧壁相对于水平面的夹角介于85度至90度。
10.如权利要求9所述的半导体元件，另包含：
第二介电层，设于该基底上；
第二导体，镶嵌于该第二介电层中；
该停止层设于该第二介电层上；
该第一介电层设于该停止层上；以及
该第一导体设于该停止层和该第一介电层中并接触该第二导体。
11.如权利要求10所述的半导体元件，其中该第一部分镶嵌于该停止层中。
12.如权利要求10所述的半导体元件，其中该第一部分包含第一斜率。
13.如权利要求10所述的半导体元件，其中该第二部分镶嵌于该第一介电层中。
14.如权利要求13所述的半导体元件，其中该第二部分包含第二斜率以及第三斜率。
15.如权利要求14所述的半导体元件，其中该第二斜率不同于该第三斜率。
16.如权利要求14所述的半导体元件，其中该第二部分左右侧壁的该第二斜率不对称。
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