CN106601623A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN106601623A CN106601623A CN201610702018.5A CN201610702018A CN106601623A CN 106601623 A CN106601623 A CN 106601623A CN 201610702018 A CN201610702018 A CN 201610702018A CN 106601623 A CN106601623 A CN 106601623A
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- component
- conductive pole
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- semiconductor
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Classifications
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Abstract
一种半导体器件包括多个半导体管芯以及围绕堆叠的半导体管芯的电介质,多个半导体管芯垂直地堆叠以具有垂直高度。半导体器件还具有位于堆叠的半导体管芯外部以及延伸穿过电介质的导电柱。在半导体器件中,导电柱的高度大于垂直高度。本发明实施例涉及半导体器件和制造半导体器件的方法。
Description
技术领域
本申请涉及半导体器件和制造半导体器件的方法。
背景技术
包括半导体器件的电子设备对我们的日常生活是必不可少的。随着电子技术的进步,电子器件变得越来越复杂以及需要更多数量的集成电路系统以用于执行期望的多功能。因此,电子器件的制造包括一个或多个组装和加工的步骤以及用于生产电子设备中的半导体器件的材料。因此,持续地需要简化生产步骤、提高生产效率以及降低在电子设备上的相关的制造成本。
在制造半导体前的操作中,半导体器件安装有包括具有不同热性能的各个材料的许多集成组件。如此,在半导体器件的固化之后,集成组件在不期望的配置中。不期望的配置可以导致半导体器件的良率损失、组件之间差的粘结性、裂缝的发展、组件的分层等。此外,半导体器件的组件包括各个金属层,各个金属层的数量有限制以及因此成本较高。组件的不期望的配置和半导体器件的良率损失可能进一步加剧材料损耗以及因此增加制造成本。
随着包括具有不同材料的更多的不同组件以及半导体器件的制造操作的复杂度增加,改进半导体器件以及改进制造操作更具挑战。如此,持续地需要改进用于制造半导体的方法以及解决上述缺点。
发明内容
根据本发明的一个实施例,提供了一种半导体器件,包括:多个半导体管芯,垂直地堆叠以具有垂直高度;电介质,围绕堆叠的所述半导体管芯;以及导电柱,位于堆叠的所述半导体管芯外部以及延伸穿过所述电介质;其中,所述导电柱的高度大于所述垂直高度。
根据本发明的另一实施例,还提供了一种制造半导体器件100的方法,包括:提供衬底;在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;在所述衬底上方并且邻近所述导电柱垂直地堆叠多个半导体管芯;设置电介质以围绕所述导电柱和所述多个半导体管芯;以及通过所述导电柱电连接所述多个半导体管芯。
根据本发明的另一实施例,还提供了一种制造半导体器件的方法,包括:垂直地堆叠多个半导体管芯;提供衬底;在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;邻近所述导电柱放置所述多个半导体管芯;以及设置电介质以围绕所述导电柱和所述多个半导体管芯;以及通过所述导电柱电连接所述多个半导体管芯。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例的半导体器件的示意图。
图2是根据一些实施例的半导体器件的示意图。
图3是根据一些实施例的半导体器件的示意图。
图4是根据一些实施例的半导体器件的示意图。
图5A至图5D是根据一些实施例的制造堆叠的组件的方法的流程图。
图6A至图6F是根据一些实施例的制造半导体器件的方法的流程图。
图7A至图7G是根据一些实施例的制造半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
在本发明中,提供3D半导体器件以集聚多个半导体组件。半导体组件顺序地垂直堆叠以减小半导体器件所需的面积。半导体器件中的半导体组件通过至少一个导电柱彼此电连接,其中,导电柱沿着堆叠的组件的厚度向上延伸。导电柱可以延伸至基本上高于半导体组件的堆叠的高度。堆叠的高度可以包括每个组件的各自的厚度以及设置在半导体组件之间或设置在半导体组件下或上方的其他粘合或绝缘材料的厚度。通过高导电柱,提供更多的有效的方法以制造3D半导体器件。
在图1中,示出了具有多个半导体组件的半导体器件100。半导体器件100包括第一组件102和第二组件104。在一些实施例中,第一组件102可以是芯片上系统(SoC),以及SoC是将计算机或其他系统的所有组件集成至单个芯片内的集成电路(IC)。在一些实施例中,第二组件104可以是像闪速存储器或动态随机存取存储器(DRAM)的存储器件,以及DRAM是存储在集成电路内的单独的电容器中的每位数据的随机存取存储的类型。第一组件102和第二组件104可以沿着每个组件的厚度垂直地堆叠。在一些实施例中,垂直的方向限定为沿着第一组件102的有源表面102a的法线方向的方向。在一些实施例中,堆叠的组件可以具有如图1所示的垂直的高度H1。有源表面102a限定为包括配置为与第一组件102外部的其他组件或导电迹线连接的诸如接合焊盘、RDL、UBM等的主要接触件的表面。
在本发明中,第一组件102和第二组件104可以背部面向背部(背靠背地堆叠)地堆叠,以及第一组件102具有面对与第二组件104的有源表面104a面向的方向相对的方向的有源表面102a。类似于有源表面102a,有源表面104a限定为包括配置为与第二组件104外部的其他组件或导电迹线连接的诸如接合焊盘、RDL、UBM等的主要接触件的表面。在一些实施例中,粘合剂可以设置在第一组件102和第二组件104之间以阻止相对移动。
在本发明中,第一组件102的侧壁102b和第二组件104的侧壁104b被中层模制材料103围绕。在一些实施例中,中层模制材料103的第一表面103a与第一组件102的顶面102a基本上共面。在一些实施例中,电介质106位于第一组件102的有源表面102a和中层模制材料103的第一表面103a上方。在一些实施例中,另一电介质108位于第二组件104的有源表面104a和中层模制材料103的第二表面103c上方。中层模制材料103夹在电介质106和电介质108之间。在一些实施例中,电介质106和电介质108包括诸如环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)、阻焊剂(SR)、ABF膜等的材料。
如图1中所示,半导体器件100还包括位于堆叠的组件外部以及延伸穿过中层模制材料103的导电柱132。在一些实施例中,导电柱132设置在最接近第一组件102和第二组件104的堆叠的组件的区域周围。在一些实施例中,导电柱132邻近包括第一组件102和第二组件104的堆叠的组件。在一些实施例中,导电柱132具有高度H2,以及高度H2大于第一组件102和第二组件104的堆叠的组件的高度H1。在一些实施例中,高度H2可以大于250μm。在一些实施例中,高度H2可以大于300μm。
在一些实施例中,导电柱132从一个端形成以及沿着平行于堆叠的组件的厚度的方向连续地向上延伸。仅一个晶种层包括在整个导电柱132中。例如,如图1所示,在每个导电柱132中仅观察到一个晶种层132b,其中,晶种层132b最靠近导电迹线的第二部分107b。在一些实施例中,晶种层在每个导电柱132的另一端中。尽管导电柱132的高度大于250μm或甚至大于300μm,但是导电柱132在单个镀操作中不连续地生长,本发明随后将详细地解释。因此,在导电柱132的仅一个端中观察到仅一个晶种层。
在一些实施例中,存在一个以上的导电柱132,以及导电柱132配置为围绕用于集聚第一组件102和第二组件104的堆叠的组件的区域。在一些实施例中,导电柱132配置为位于电介质106和电介质108之间的支撑件。在一些实施例中,导电柱132可以是TIV(集成扇出式穿孔)。在一些实施例中,导电柱132可以包括铜、铝、钨、镍、焊料、金、银、钯、铂、钛或它们的合金。
在一些实施例中,导电柱132是具有诸如圆形、四边形、矩形、正方形、多边形等的各个截面形状的圆柱体。在一些实施例中,导电柱132的Wt可以小于285μm。在一些实施例中,邻近的导电柱132之间的间隔Ws大于约2300μm。在一些实施例中,导电柱132和第二组件104的侧壁104b之间的间隔Wd大于约150μm。
在一些实施例中,集聚比例限定为物质的体积与特定空间的比率。在一些实施例中,第一组件102和第二组件104的堆叠的组件与位于两个邻近的导电柱132之间的空间的集聚比例是65%至95%。在一些实施例中,集聚比例是约75%至85%。在一些实施例中,第一组件102的侧壁102b和第二组件104的侧壁104b基本上是共面的。在一些实施例中,第一组件102的宽度和第二组件104的宽度基本上相同。在一些实施例中,导电柱132基本上平行于第一组件102的侧壁102b和第二组件104的侧壁104b。
电介质106和电介质108内部的导电结构包括导电结构的若干部分。在一些实施例中,导电迹线的第一部分107a形成在电介质106中以将第一导电组件102电连接至导电柱132或导电体115。第一部分107a位于堆叠的组件的一侧上方或位于第一组件102的有源表面102a上方。第一部分107a配置为第一组件102的扇出式导电焊盘。在一些实施例中,导电迹线的第一部分107a可以延伸至电介质106的第一表面106a。第一表面106a是半导体器件100的外表面的部分。在一些实施例中,接合焊盘114形成在第一表面106a上以接收导电体115。接合焊盘114也电连接至导电迹线的第一部分107a。在一些实施例中,接合焊盘114是凸块下金属(UBM)焊盘,凸块下金属(UBM)焊盘是可固化的表面以用于接收导电体115。在一些实施例中,接合焊盘114包括金、银、铜、镍、钨、铝、钯和/或它们的合金。在堆叠的组件的另一侧上,导电迹线的第二部分107b形成在电介质108中以将第二组件104电连接至导电柱132。导电迹线的第二部分107b位于堆叠的组件的另一侧上或位于第二组件104的有源表面104a上方。第二部分107b配置为第二组件104的扇出式导电焊盘。在一些实施例中,导电迹线的第二部分107b可以延伸至电介质108内从而电连接至散热焊盘111。在一些实施例中,导电迹线的第一部分107a和导电迹线的第二部分107b分别是集成的半导体封装件的RDL(再分布层)、PPI(后钝化互连件)或互连通孔。
导电迹线的第一部分107a和第二部分107b通过堆叠的组件物理地分开以及通过导电柱132电连接。第一组件102和第二组件104通过导电迹线的第一部分107a、导电柱132和导电迹线的第二部分107b电连接。在一些实施例中,第一组件102和第二组件104一起实施各个功能,诸如无线电信号传输、处理、解释(illuminating)等。
在一些实施例中,散热焊盘111可选地设置在电介质108中。导电迹线的第二部分107b将散热焊盘111连接至导电柱132和第二组件104。来自第一组件102和第二组件104的热可以通过散热焊盘111通过导电迹线的第一部分107a、导电迹线的第二部分107b的路径而被驱散。
图2是半导体器件300的实施例。半导体器件300包括类似于图1的半导体100的结构。在此不再重复利用相同数字标记示出的元件的这样的细节。在一些实施例中,第一组件102的宽度可以小于第二组件104宽度。在一些实施例中,第一组件102的宽度可以比第二组件104的宽度小100μm。在一些实施例中,第一组件102的中心线和第二组件104的中心线是共线的。在一些实施例中,距离W1可以限定为第一组件102的侧壁102b和第二组件104的侧壁104b之间的距离。在一些实施例中,距离W1可以大于约50μm。在一些实施例中,距离W1可以是约50μm至100μm。
图3是半导体器件500的实施例。半导体器件500包括类似于图2的半导体300的结构。在此不再重复利用相同数字标记示出的元件的这样的细节。在一些实施例中,底部填充110设置在第二组件104和电介质108之间。底部填充110部分地覆盖有源表面104a。在一些实施例中,底部填充110可以配置为应力缓冲剂。在一些实施例中,底部填充110可以包括环氧树脂、硅和金属微粒。在一些实施例中,可以通过诸如注射的各个操作来设置底部填充110。
图4是半导体器件700的实施例。半导体器件700包括类似于图2的半导体300的结构。在此不再重复利用相同数字标记示出的元件的这样的细节。在一些实施例中,半导体器件700还包括第三组件105。在一些实施例中,第三组件105垂直地堆叠在第二组件104上并且邻近第一组件102。在一些实施例中,将第一组件102和第三组件105横向地设置为具有间隔W2。在一些实施例中,间隔W2可以大于约100μm。在一些实施例中,第一组件102的侧壁102b和第二组件104的侧壁104b的宽度W3可以大于约50μm。在一些实施例中,存在两个以上的设置在第二组件104上方的组件。类似于位于第二组件104上方的第一组件102和第三组件105,第一组件102和第三组件105横向地布置在伪表面(与有源表面104a相对的表面)上方。在一些实施例中,第一组件102和第三组件105可以是不同类型的组件。在一些实施例中,第二组件104的宽度基本上等于或大于第一组件102的宽度和第三组件105的宽度的和。
图5A至图5D包括制造图2中的第一组件102和第二组件104的堆叠的组件的方法的操作。方法包括许多操作(201、202、203和204)。在操作201中,如图5A所示,提供若干第一组件102。在操作202中,如图5B所示,提供晶圆级封装件101。在一些实施例中,晶圆级封装件101包括若干第二组件104。在一些实施例中,晶圆级封装件101具有设置在晶圆级封装件101的有源表面101a上的若干凸块。在一些实施例中,翻转晶圆级封装件101,以及晶圆级封装件101的与有源表面101a相对的底面101b朝向上以用于堆叠图5A中的第一组件102。在操作203中,如图5C所示,拾取图5A中的第一组件102并且将其放置在晶圆级封装件101的底面101b上。将第一组件102放置为具有间隔W4。在一些实施例中,间隔W4可以大于约100μm。在一些实施例中,可以如图5A的第一组件102来分割第二组件104,同时第一组件102为晶圆级形式。将第二组件104拾取和放置在第一组件102上。在操作204中,如图5D所示,沿着间隔W4分割晶圆级封装件101以形成第一组件102和第二组件104的若干堆叠的组件。在一些实施例中,通过机械或激光剑来分割晶圆级封装件101。
图6A至图6F包括制造图2中的半导体器件300的方法的操作。方法包括许多操作(401、402、403、404、405和406)。在操作401中,提供作为载体或支撑的衬底400。如图6A所示,在衬底400上方设置电介质108、散热焊盘111和导电迹线的第二部分107b。在一些实施例中,导电迹线的第二部分107b从散热焊盘111向上延伸至电介质108的顶面108b。稍后,晶种层132b设置在导电迹线的第二部分107b的暴露部分上。导电柱132形成在晶种层132b上且从电介质108的顶面108b进一步向上延伸。在晶圆级工艺中,如图6A所示,在预定图案中形成导电柱132。一些相邻的导电柱132以最优的间隔布置以具有设置在其间的一些电子组件。
在操作402中,如图6B所示,图5D中的包括第一组件102和第二组件104的堆叠的组件设置在电介质108的顶面108b上以及设置在导电柱132之间。在一些实施例中,第二组件104的顶面104a设置在电介质108的顶面108b上。在一些实施例中,第二组件104电连接至导电迹线的第二部分107b。
在操作403中,如图6C所示,中层模制材料103设置在顶面108b上以及填充位于导电柱132和第一组件102与第二组件104的堆叠的组件之间的间隙。可以过填充中层模制材料103以覆盖导电柱132以及第一组件102和第二组件104的堆叠的组件。引入去除或平坦化操作以去除中层模制材料103的部分从而暴露导电柱132的顶面132a和第一组件102的顶面102a,使得没有中层模制材料103保留在导电柱132和第一组件102上。图6C是示出了去除工艺之后的结构的实施例。在一些实施例中,通过诸如蚀刻或研磨的工艺同时地去除中层模制材料103、导电柱132和第一组件102的顶部以使其是共面的。
在操作404中,如图6D所示,电介质106设置在中层模制材料103、导电柱132和第一组件102上方。在一些实施例中,中层模制材料103包括诸如环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)、阻焊剂(SR)、ABF膜等的聚合物材料。在一些实施例中,如图6D所示,凹进的部分106b形成在导电柱132的顶面132a和第一组件102的顶面102a之上。在一些实施例中,通过光刻去除电介质106的位于顶面132a和顶面102a之上的部分。
如图6D所示,设置导电迹线的第一部分107a。在一些实施例中,通过镀或溅射将导电迹线的第一部分107a设置在电介质106上。在一些实施例中,如图6D所示,电介质106和导电迹线的第一部分107a可以包括至少一个层以及可以顺序地设置在层中。
在一些实施例中,电介质106设置在导电迹线的第一部分107a上以及覆盖半导体器件的顶部。在一些实施例中,如图6D所示,形成通孔106c以及设置接合焊盘114。在一些实施例中,通过去除电介质106的位于导电迹线的第一部分107a之上的部分来形成通孔106c。在一些实施例中,通过光刻去除电介质106的部分来形成通孔106c。在一些实施例中,通孔106c是锥形结构。
在一些实施例中,接合焊盘114形成在导电迹线的第一部分107a的部分107a-1和电介质106之上。在一些实施例中,接合焊盘114填充通孔106c,并且从电介质106的顶面106a延伸至导电迹线的第一部分107a的部分107a-1使得接合焊盘114与导电迹线的第一部分107a电连接。在一些实施例中,接合焊盘114是凸块下金属(UBM)焊盘,凸块下金属(UBM)焊盘是可固化的表面以用于接收凸块以及将接合焊盘114与第一组件102外部的电路系统电连接。
在操作405中,如图6E所示,凸块115设置在接合焊盘114上。在一些实施例中,凸块115是焊料凸块、焊料球和焊料柱等。在一些实施例中,凸块115配置为用于与另一管芯、另一衬底或另一半导体封装件上的焊盘附接。在一些实施例中,凸块115是导电凸块或导电接合点。在一些实施例中,第一组件102通过导电迹线的第一部分107a和接合焊盘114与凸块115电连接。
在操作406中,如图6F所示,从半导体器件去除图6E中的衬底400。在一些实施例中,半导体器件从衬底400脱离以用于随后的操作。
上下翻转图6E中的结构以及将图6E中的结构附接至在图6F的底部处的另一衬底120。衬底120可以是封装件衬底、板(印刷电路板(PCB))、晶圆、管芯、插入器衬底或其他合适的衬底。凸块结构通过各个导电附接点连接至衬底120。例如,在衬底120上形成并且图案化导电区122。通过掩模层124呈现的导电区122是接触焊盘或部分导电迹线。在一个实施例中,掩模层124是在衬底120上形成并且图案化的阻焊层以暴露导电区122。掩模层124具有提供用于焊料接合点形成的窗口的掩模开口。例如,可以在导电区122上提供包括锡、铅、银、铜、镍、铋或它们的组合的合金的焊料层。半导体器件可以通过位于接合焊盘114和导电区122之间的接合焊料结构126连接至衬底120。示例性连接工艺包括应用焊剂(flux)、放置芯片、熔融的焊料接合点的回流和/或焊剂残留的清洗。半导体衬底102、接合焊料结构126和其他衬底120可以被称为封装组件,或在本实施例中称为倒装芯片封装组件。
在一些实施例中,半导体器件通过封装凸块与另一封装件接合以变为叠层封装件(PoP)。在一些实施例中,半导体器件通过封装凸块与另一封装件接合。在一些实施例中,半导体器件的若干导电构件通过若干封装凸块相应地与另一封装件的若干封装焊盘接合以变成PoP。
图7A至图7G包括制造图1中的半导体器件100的方法的操作。方法包括许多操作(601、602、603、604、605、606和607)。在操作601中,如图7A所示,提供图6A中的半导体制造的半导体器件。在操作602中,如图7B所示,焊料柱设置在电介质108的顶面上。在操作603中,如图7C所示,第二组件104插入在导电柱132之间以及通过焊料柱电连接至导电迹线的第二部分107b。在一些实施例中,一些凸块设置在第二组件104的顶面104a上以及连接至焊料柱以将第二组件104电连接至导电迹线的第二部分107b。在操作604中,如图7D所示,第一组件102堆叠在第二组件104的底面104b上。
在操作605中,如图7E所示,中层模制材料103设置在顶面108b上以及填充位于导电柱132和第一组件102与第二组件104的堆叠的组件之间的间隙。引入研磨操作以去除过量的模塑料以暴露导电柱132的顶面132a和第一组件102的顶面102a。如图7E所示,形成平坦的表面以及暴露导电柱132和第一组件102的接触点以接收设置在其上的其他导电结构。在操作606中,如图7E所示,形成电介质106、导电迹线的第一部分107a和接合焊盘114。在操作607中,如图7G所示,设置凸块以及将半导体器件连接至另一衬底。
在一些实施例中,一种半导体器件包括多个半导体管芯以及围绕堆叠的半导体管芯的电介质,多个半导体管芯垂直地堆叠以具有垂直高度。半导体器件还具有位于堆叠的半导体管芯外部以及延伸穿过电介质的导电柱。在半导体器件中,导电柱的高度大于垂直高度。
在一些实施例中,一种制造半导体器件的方法包括提供衬底以及在衬底上方设置导电柱,其中,导电柱的高度大于约250μm。方法还包括在衬底上方并且邻近导电柱垂直地堆叠多个半导体管芯,设置电介质以围绕导电柱和多个半导体管芯以及通过导电柱电连接多个半导体管芯。
在一些实施例中,一种制造半导体器件的方法包括垂直地堆叠多个半导体管芯,提供衬底以及在衬底上方设置导电柱,其中,导电柱的高度大于约250μm。方法还包括邻近导电柱放置多个半导体管芯,设置电介质以围绕导电柱和多个半导体管芯,以及通过导电柱电连接多个半导体管芯。
根据本发明的一个实施例,提供了一种半导体器件,包括:多个半导体管芯,垂直地堆叠以具有垂直高度;电介质,围绕堆叠的所述半导体管芯;以及导电柱,位于堆叠的所述半导体管芯外部以及延伸穿过所述电介质;其中,所述导电柱的高度大于所述垂直高度。
在上述半导体器件中,所述导电柱的所述高度大于250μm。
在上述半导体器件中,所述导电柱的宽度小于285μm。
在上述半导体器件中,所述多个半导体管芯包括第一组件和第二组件,以及所述第一组件垂直地堆叠在所述第二组件上。
在上述半导体器件中,所述第一组件的宽度和所述第二组件的宽度相同。
在上述半导体器件中,所述第一组件的宽度小于所述第二组件的宽度。
在上述半导体器件中,所述第一组件的所述宽度和所述第二组件的所述宽度的差值大于100μm。
在上述半导体器件中,还包括第三组件,其中,所述第三组件垂直地堆叠在所述第二组件上并且邻近所述第一组件。
在上述半导体器件中,所述第二组件的宽度大于所述第一组件的宽度和所述第三组件的宽度的和。
在上述半导体器件中,还包括散热焊盘111,所述散热焊盘电连接至所述多个半导体管芯以及配置为驱散来自所述多个半导体管芯的热量。
在上述半导体器件中,所述导电柱配置为用于所述多个半导体管芯的支撑件。
在上述半导体器件中,还包括多个导电柱,其中,所述多个导电柱围绕所述多个半导体管芯。
根据本发明的另一实施例,还提供了一种制造半导体器件100的方法,包括:提供衬底;在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;在所述衬底上方并且邻近所述导电柱垂直地堆叠多个半导体管芯;设置电介质以围绕所述导电柱和所述多个半导体管芯;以及通过所述导电柱电连接所述多个半导体管芯。
在上述方法中,堆叠所述多个半导体管芯包括将第一半导体管芯垂直地堆叠在第二半导体管芯上。
在上述方法中,所述第二半导体管芯的宽度大于所述第一半导体管芯的宽度。
在上述方法中,所述第二半导体管芯的所述宽度和所述第一半导体管芯的所述宽度的差值大于100μm。
根据本发明的另一实施例,还提供了一种制造半导体器件的方法,包括:垂直地堆叠多个半导体管芯;提供衬底;在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;邻近所述导电柱放置所述多个半导体管芯;以及设置电介质以围绕所述导电柱和所述多个半导体管芯;以及通过所述导电柱电连接所述多个半导体管芯。
在上述方法中,堆叠所述多个半导体管芯包括将晶圆级封装件分割成所述多个半导体管芯。
在上述方法中,还包括去除所述电介质的部分以暴露所述导电柱的顶面以及所述多个半导体管芯的顶面。
在上述方法中,通过蚀刻或研磨实施去除所述电介质的部分。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体器件,包括:
多个半导体管芯,垂直地堆叠以具有垂直高度;
电介质,围绕堆叠的所述半导体管芯;以及
导电柱,位于堆叠的所述半导体管芯外部以及延伸穿过所述电介质;其中,
所述导电柱的高度大于所述垂直高度。
2.根据权利要求1所述的半导体器件,其中,所述导电柱的所述高度大于250μm。
3.根据权利要求1所述的半导体器件,其中,所述导电柱的宽度小于285μm。
4.根据权利要求1所述的半导体器件,其中,所述多个半导体管芯包括第一组件和第二组件,以及所述第一组件垂直地堆叠在所述第二组件上。
5.根据权利要求4所述的半导体器件,其中,所述第一组件的宽度和所述第二组件的宽度相同。
6.根据权利要求4所述的半导体器件,其中,所述第一组件的宽度小于所述第二组件的宽度。
7.根据权利要求6所述的半导体器件,其中,所述第一组件的所述宽度和所述第二组件的所述宽度的差值大于100μm。
8.根据权利要求4所述的半导体器件,还包括第三组件,其中,所述第三组件垂直地堆叠在所述第二组件上并且邻近所述第一组件。
9.一种制造半导体器件100的方法,包括:
提供衬底;
在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;
在所述衬底上方并且邻近所述导电柱垂直地堆叠多个半导体管芯;
设置电介质以围绕所述导电柱和所述多个半导体管芯;以及
通过所述导电柱电连接所述多个半导体管芯。
10.一种制造半导体器件的方法,包括:
垂直地堆叠多个半导体管芯;
提供衬底;
在所述衬底上方设置导电柱,其中,所述导电柱的高度大于250μm;
邻近所述导电柱放置所述多个半导体管芯;以及
设置电介质以围绕所述导电柱和所述多个半导体管芯;以及
通过所述导电柱电连接所述多个半导体管芯。
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CN109390325A (zh) * | 2017-08-09 | 2019-02-26 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
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TWI560784B (en) * | 2009-11-05 | 2016-12-01 | Stats Chippac Ltd | Semiconductor device and method of forming wlcsp using wafer sections containing multiple die |
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CN108878396A (zh) * | 2017-05-16 | 2018-11-23 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
CN108878396B (zh) * | 2017-05-16 | 2020-11-06 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
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CN107507816A (zh) * | 2017-08-08 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | 扇出型晶圆级多层布线封装结构 |
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CN112309998A (zh) * | 2019-07-30 | 2021-02-02 | 华为技术有限公司 | 封装器件及其制备方法、电子设备 |
WO2022012538A1 (zh) * | 2020-07-13 | 2022-01-20 | 矽磐微电子(重庆)有限公司 | 多芯片3d封装结构及其制作方法 |
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US9620482B1 (en) | 2017-04-11 |
TWI720035B (zh) | 2021-03-01 |
US20170110438A1 (en) | 2017-04-20 |
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