CN115588651A - 半导体封装件以及其制造方法 - Google Patents
半导体封装件以及其制造方法 Download PDFInfo
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- CN115588651A CN115588651A CN202211091480.8A CN202211091480A CN115588651A CN 115588651 A CN115588651 A CN 115588651A CN 202211091480 A CN202211091480 A CN 202211091480A CN 115588651 A CN115588651 A CN 115588651A
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Abstract
本发明实施例的半导体封装件包含电路板结构、第一重布线层结构、第二重布线层结构、第一包封体、封装结构、总线管芯以及导电柱。电路板结构包含核心层、第一叠层以及第二叠层。第一重布线层结构在电路板结构上方,第一重布线层结构包括第一介电层。第二重布线层结构在电路板结构上方,第二重布线层结构包括第二介电层。第一包封体位于第一介电层与第二介电层之间。封装组件在第一重布线层结构上方,包括多个封装组件。第一包封体沿着总线管芯的整个侧壁延伸,总线管芯的表面与第一包封体及多个导电柱的上表面共面,总线管芯电连接多个封装组件中的两个或更多个,以及多个封装组件分别通过多个导电柱与第一重布线层结构电连接。
Description
本发明是2019年11月28日所提出的申请号为201911191820.2、发明名称为《半导体封装件以及其制造方法》的发明专利申请的分案申请。
技术领域
本发明实施例涉及半导体封装件以及其制造方法。
背景技术
半导体封装件用于各种电子应用中,例如个人计算机、手机、数码相机以及其它电子设备。就用于集成电路组件或半导体管芯的封装来说,一或多个芯片封装件通常接合到电路载体(例如,系统板、印刷电路板或类似者),以用于电连接到其它外部器件或电子组件。
近年来,高性能计算(high-performance computing;HPC)变得更加流行,且广泛用于高级网络和服务器应用,特别是用于需要高数据速率、逐渐增加的带宽以及逐渐降低的时延的人工智能(artificial intelligence;AI)相关的产品。然而,随着包含HPC组件的封装件的封装大小变得更大,管芯之间的通信已成为更具挑战性的问题。
发明内容
本发明实施例的一种半导体封装件包含电路板结构、第一重布线层结构、第二重布线层结构、第一包封体、封装结构、总线管芯以及多个导电柱。电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层。第一重布线层结构在所述电路板结构上方,所述第一重布线层结构包括第一介电层。第二重布线层结构在所述电路板结构上方,所述第二重布线层结构包括第二介电层。第一包封体位于所述第一介电层与所述第二介电层之间。封装组件在所述第一重布线层结构上方,包括多个封装组件。所述第一包封体沿着所述总线管芯的整个侧壁延伸,所述总线管芯的表面与所述所述第一包封体及所述多个导电柱的上表面共面,所述总线管芯电连接所述多个封装组件中的两个或更多个,以及所述多个封装组件分别通过所述多个导电柱与所述第一重布线层结构电连接。
本发明实施例的一种半导体封装件包含第一重布线层结构、多个导电件以及管芯、第二重布线层结构和封装结构。多个导电柱以及所述管芯由第一包封体包封,其中所述管芯的底表面与所述第一重布线层结构的表面粘合。第二重布线层结构安置在所述第一包封体上方,其中所述第一重布线层结构包括第一通孔以及与所述第一通孔一体成形且具有宽度大于所述第一通孔的第一导线,所述第二重布线层结构包括第二通孔以及与所述第二通孔一体成形且具有宽度大于所述第二通孔的第二导线,所述第二通孔位于所述第一导线及所述第二导线之间且所述第一导线位于所述第一通孔与所述第二通孔之间。封装结构安置在所述第二重布线层结构上方且包括多个封装组件,包所述管芯通过所述第二重布线层结构与所述封装结构电连接,且所述多个导电件电连接所述第一重布线层结构与所述第二重布线层结构,其中所述第一重布线层结构的侧壁、所述第二重布线层结构的侧壁以及所述第一包封体的侧壁齐平。
本发明实施例的一种制造半导体封装件的方法包含以下步骤。提供电路板结构,所述电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层。直接在所述第一叠层上形成多个第一介电层和位于所述多个第一介电层中且交替地堆叠的多个第一金属线和多个第一通孔,以形成第一重布线层结构。直接在所述第一重布线层结构上形成多个导电柱。将管芯安装到所述第一重布线层结构上且位于两相邻所述导电柱之间。形成第一包封体以包封所述管芯以及所述多个导电柱,所述多个导电柱环绕所述管芯。直接在所述第一包封体上方形成第二重布线层结构,以电连接所述管芯以及所述多个导电柱。将多个封装组件接合到所述第二重布线层结构上,其中所述管芯电连接到所述多个封装组件中的至少两个。
附图说明
当结合附图阅读时,从以下详细描述最好地理解本公开的各方面。应注意,根据业界中的标准惯例,各种特征未按比例绘制。实际上,出于论述清楚起见,可任意增大或减小各种特征的关键尺寸。
图1A到图1I为根据本公开的一些实施例的制造半导体封装件的方法中的不同阶段的示意性截面图。
图2为根据本公开的一些实施例的示出半导体封装件的示意性横截面图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来简化本公开。当然,这些组件和布置只是实例且并不意欲为限制性的。举例来说,在以下描述中,第二特征在第一特征上方或上的形成可包含第二特征和第一特征直接接触地形成的实施例,且还可包含额外特征可在第二特征与第一特征之间形成使得第二特征与第一特征可不直接接触的实施例。另外,本公开可在各种实例中重复附图标号和/或字母。此重复是出于简单和清晰的目的,且本身并不指示所论述的各种实施例和/或配置之间的关系。
另外,为易于描述,在本文中可使用例如“在……下方”、“在……之下”、“下部”、“在……上”、“在……上方”、“上覆”、“在……之上”、“上部”以及类似者的空间相对术语来描述一个元件或特征与另一元件或特征如图式中所示的关系。除了图中所描绘的定向之外,空间相对术语意图涵盖器件在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词可同样相应地进行解释。
此外,为易于描述,在本文中可使用例如“第一”、“第二”、“第三”、“第四”以及类似者的术语来描述如图式中所示的类似或不同元件或特征,且可取决于存在次序或描述的上下文而互换使用所述术语。
还可包含其它特征和工艺。举例来说,可包含测试结构以辅助对3D封装或3DIC器件的校验测试。测试结构可包含例如形成于重布线层中或衬底上的测试垫,所述衬底允许对3D封装或3DIC进行测试,使用探针和/或探针卡以及类似操作。可对中间结构以及最终结构执行校验测试。另外,本文中所公开的结构和方法可与并有已知良好管芯的中间校验的测试方法结合使用以增加良率并降低成本。
图1A到图1I为根据本公开的一些实施例的制造半导体封装件的方法中的不同阶段的示意性截面图。参看图1A,提供电路板结构CBS。在一些实施例中,电路板结构CBS包含核心层CL以及第一叠层BL1和第二叠层BL2,所述第一叠层(build-up layer)BL1和第二叠层BL2分别位于核心层CL的两个表面上。在一些实施例中,核心层CL包含核心介电层102、核心导电层104A和核心导电层104B、导电盖106A和导电盖106B以及电镀穿孔TH。在一些实施例中,核心介电层102包含半固化片(含有环氧树脂、树脂、二氧化硅填料及/或玻璃纤维)、味之素积层膜(Ajinomoto Buildup Film;ABF)、涂树脂铜箔(resincoated copper foil;RCC)、聚酰亚胺、光成像介电(photo image dielectric;PID)、陶瓷芯体、玻璃芯体、模制化合物、其组合或类似者。然而,本公开并不限于此,且还可使用其它介电材料。核心导电层104A和核心导电层104B分别形成在核心介电层102的相对侧上。在一些实施例中,核心导电层104A和核心导电层104B包括铜、金、钨、铝、银、金、其组合或类似者。导电盖106A和导电盖106B分别位于核心导电层104A和核心导电层104B的上方。在一些实施例中,导电盖106A和导电盖106B包括例如铜或其它合适的导电材料。
在一些实施例中,电镀穿孔TH安置在核心介电层102中且穿过所述核心介电层102,所述核心介电层102提供核心导电层104A与核心导电层104B之间的电连接。换句话说,电镀穿孔TH提供位于核心介电层102的两个相对侧上的电路之间的电路径。在一些实施例中,电镀穿孔TH可内衬有导电材料且用绝缘材料填满。在一些实施例中,形成电镀穿孔TH的方法包含以下操作。首先,穿孔(未绘示)通过(例如)机械或激光钻孔、蚀刻或另一合适的去除技术形成在核心介电层102中的预定位置处。可以执行去污处理以去除穿孔中剩余的残留物。随后,穿孔的侧壁可电镀一或多个导电材料到预定厚度,从而提供电镀穿孔TH。举例来说,可用电镀敷或无电电镀的铜或其它导电材料电镀穿孔。
在一些实施例中,核心导电层104A和核心导电层104B、导电盖106A和导电盖106B以及电镀穿孔TH可由以下步骤所形成。首先,第一导电材料(未绘示)分别形成在核心介电层102的两个相对表面上。接着,形成电镀穿孔TH以穿透如之前所提到的核心介电层102,且提供分别形成在核心介电层102的两个表面上的第一导电材料之间的电连接。其后,第二导电材料分别形成在核心介电层102的相对表面上的第一导电材料上方,其中第二导电材料可不同于第一导电材料。在一些实施例中,可通过使用任何合适的方法(例如,化学气相沉积(chemical vapor deposition;CVD)、溅镀、打印、电镀或类似者)形成第一导电材料和第二导电材料。接着,可将第一导电材料和第二导电材料一起图案化以分别形成核心导电层104A和核心导电层104B以及导电盖106A和导电盖106B。在一些实施例中,可使用光刻和蚀刻工艺或另一合适的去除技术来部分去除第一导电材料和第二导电材料。
第一叠层BL1和第二叠层BL2分别安置在核心层CL的相对侧上。确切地说,第一叠层BL1形成在核心层CL的核心导电层104A上方,且第二叠层BL2形成在核心层CL的核心导电层104B上方。在一些实施方式中,第一叠层BL1的形成可包括连续形成多个第一介电层108A和多个第一导电图案110A,其中第一介电层108A和第一导电图案110A交替地堆叠在核心层CL的第一表面上方。类似地,第二叠层BL2的形成可包括连续形成多个第二介电层108B和多个第二导电图案110B,其中第二介电层108B和第二导电图案110B交替地堆叠在核心层CL的第二表面上方。在一些实施例中,介电层108A和介电层108B的材料可为ABF、半固化片、RCC、聚酰亚胺、PID、模制化合物、其组合或类似者。介电层108A和介电层108B可藉层合工艺、涂布工艺或类似者形成。尽管对于第一叠层BL1和第二叠层BL2中的每一个仅示出三层导电图案和三层介电层,但本公开的范围并不限于此。在其它实施例中,可根据本设计要求调整介电层(介电层108A/108B)的数目和导电图案(导电图案110A/110B)的数目。在一些实施例中,核心层CL的厚度在例如30微米到2000微米范围内。在一些实施例中,介电层108A和介电层108B的厚度在10微米到20微米范围内,且导电图案110A和导电图案110B的厚度在例如10微米到20微米范围内。导电图案110A、导电图案110B包括金属线和通孔。在一些实施例中,通孔的临界尺寸在60微米到70微米范围内。在一些实施例中,对于导电图案和介电层,第一叠层BL1的总层数目可总计为0到8层,对于导电图案和介电层,第二叠层BL2的总层数目可总计为0到8层。在一些替代实施例中,可省略第一叠层BL1和第二叠层BL2中的至少一者。在一些实施例中,第一叠层BL1中的层的数目等于第二叠层BL2中的层的数目。在一些替代实施例中,第一叠层BL1和第二叠层BL2的总数目可不同。在一些实施例中,电路板结构CBS中的第一叠层BL1和第二叠层BL2的总层数目小于传统电路板结构中的叠层的总层数目,所述叠层可为28到36层。因此,在一些实例中,电路板结构CBS也可称为半完成电路衬底或半完成电路载体。
在一些实施例中,图案化掩模层112形成在第二叠层BL2上方。如图1A中所示,图案化掩模层112形成在最外面的第二介电层108B和最外面的第二导电图案110B上方。在一些实施例中,图案化掩模层112包含部分暴露最外面的第二导电图案110B的多个开口。在一些实施例中,图案化掩模层112可以由具有二氧化硅、硫酸钡以及环氧树脂及/或类似者的化学组成的材料形成。举例来说,图案化掩模层112可用作焊料掩模且可选定以承受随后安置在开口内的熔融导电材料(例如,焊料、金属及/或金属合金)的温度。在一些替代实施例中,图案化掩模层112的材料可为模制化合物或其它合适的材料。
参看图1B,电路板结构CBS放置在载体C上。在一些实施例中,载体C为玻璃衬底或任何用于承载半导体晶片或用于半导体封装件的制造方法的重建晶片的任何合适的载体。在一些实施例中,第二叠层BL2安置在核心层CL与载体C之间。在一些替代实施例中,胶体层(未绘示)可形成在电路板结构CBS与载体C之间的图案化掩模层112上。
参看图1C,重布线层结构RDL1形成在第一叠层BL1上方且电连接到第一叠层BL1。在一些实施例中,重布线层结构RDL1的形成可包括连续形成多个介电层114和多个导电图案116,其中介电层114和多个导电图案116交替地堆叠在第一叠层BL1的最外面的第一电介质层108A上方。在一些实施例中,最下面的介电层114与最外面的第二介电层108A接触,且最下面的导电图案116与最外面的第一导电图案110A接触以电连接重布线层结构RDL1和第一叠层BL1。在一些实施例中,介电层114的厚度在2微米到10微米范围内。在一些实施例中,介电层114的材料为聚酰亚胺、聚苯并恶唑(PBO)、苯环丁烷(BCB)、例如氮化硅的氮化物、例如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅玻璃(BSG)、硼经掺杂磷硅酸盐玻璃(BPSG)、模制化合物、其组合或类似者。在一些替代实施例中,可交替地安置由有机化合物制成的介电层114和由模制化合物制成的介电层114。在一些实施例中,介电层114由例如旋涂式涂布法、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或类似者的合适的制造技术形成。本公开并不限于此。导电图案116包含金属线和通孔。在一些实施例中,重布线层结构RDL1的通孔的临界尺寸在7微米到35微米范围内。在一些实施例中,导电图案116包含金属,例如铝、钛、铜、镍、钨及/或其合金。在一些实施例中,导电图案116可由沉积,然后光刻和蚀刻工艺形成。在一些实施例中,导电图案116可由电镀敷或无电电镀形成。在一些替代实施例中,可省略第一叠层BL1,且重布线层结构RDL1可直接形成在核心层CL上。
在一些实施例中,重布线层结构RDL1的介电层114的材料不同于第一叠层BL1的介电层108A的材料。重布线层结构RDL1的介电层114的厚度可小于或实质上等于第一叠层BL1的介电层108A的厚度。另外,重布线层结构RDL1的通孔的临界尺寸小于第一叠层BL1的通孔的临界尺寸。通过在半完成电路衬底上方形成重布线层,形成的结构具有高模数和减小的厚度。此外,整个半导体封装件的硬度、电感以及电阻得到增强且成本降低。
参看图1D,多个连接件118和多个管芯120A、120B安置在重布线层结构RDL1上方。在一些实施例中,连接件118形成在重布线层结构RDL1的最顶部导电图案116上,以便为重布线层结构RDL1提供与安置在其上的其它组件的电连接。连接件118可为导电柱,且连接件118可由电镀敷或无电电镀形成。
在一些实施例中,在形成连接件118之后,管芯120A、120B可分别安装到两个邻近的连接件118之间的最顶部导电图案116上。在一些实施例中,管芯120A、120B可为总线管芯,所述总线管芯在组装在晶片级封装中的其它半导体管芯之间提供较短电连接路径。在一些实施例中,管芯120A、120B包含内连线结构且可不含任何有源器件及/或无源器件。管芯120A(或管芯120B)也可包含衬底122和衬底122上的多个导电图案124。在一些实施例中,衬底122为例如硅衬底或类似者的半导体衬底。管芯120A(或管芯120B)也可包含导电图案或衬底122中的迹线(未绘示),且导电图案或迹线可与管芯120A(或管芯120B)的导电图案124电连接。在一些实施例中,导电图案或迹线可安置在衬底122中或衬底122上。在一些实施例中,可密集地布置导电图案124,使得管芯120A、120B可提供高密度的内连线元件。在一些实施例中,导电图案124可具有单个或多个层状结构。导电图案124的材料包含铜、铝、其组合或类似者。在一些实施例中,管芯120A、120B的厚度在10微米到100微米范围内,且管芯120A、120B的x-y尺寸在2毫米×3毫米到40毫米×80毫米范围内。在一些实施例中,管芯120A、120B可通过粘合层126(例如管芯附接膜(die attach film;DAF)安装到导电图案116上。在一些实施例中,管芯120A、120B不电连接到重布线层结构RDL1。然而,本公开并不限于此。在一些替代实施例中,管芯120A、120B可具有硅穿孔,且管芯120A、120B可由焊料球接合到重布线层结构RDL1以直接电连接到重布线层结构RDL1。在一些实施例中,连接件118的顶部表面可与管芯120A、120B的导电图案124的顶部表面实质上共面。然而,在一些替代实施例中,连接件118的顶部表面可低于或高于管芯120A、120B的导电图案124的顶部表面。
参看图1E,包封体128形成在重布线层结构RDL1上方以包封连接件118和管芯120A、120B。在一些实施例中,绝缘材料形成在重布线层结构RDL1上方以覆盖连接件118和管芯120A、120B。接着,研磨绝缘材料直到暴露管芯120A、120B的连接件118和导电图案124,以便形成包封体128。包封体128包封管芯120A、120B的侧壁和安置在其上的导电图案124,且暴露管芯120A、120B的导电图案124的顶部表面。换句话说,管芯120A、120B包埋在包封体128中,且具有暴露的顶部表面。在一些实施例中,管芯120A、120B的导电图案124可被包封体128包封且与包封体128接触。连接件118安置在包封体128中且穿透所述包封体。在一些实施例中,包封体128包含例如由模制工艺形成的环氧模制化合物的模制化合物。在一些替代实施例中,包封体128可包括环氧树脂、树脂或类似者。在一些实施例中,包封体128的厚度在5微米到100微米范围内。连接件118和管芯120A、120B的顶部表面与包封体128的顶表面实质上共面。
参看图1F,在形成包封体128之后,重布线层结构RDL2形成在包封体128上方,所述重布线层结构RDL2电连接到连接件118和管芯120A、120B。在一些实施例中,重布线层结构RDL2可包括交替地堆叠在包封体128上方的多个介电层130和多个导电图案132、132a。在一些实施例中,介电层130的厚度在2微米到50微米范围内。在一些实施例中,最顶部导电图案132a为导电端,所述导电端可包括多个导电柱和用于球安装的多个球下金属(under-ballmetallurgy;UBM)图案。在一些实施例中,最顶部导电图案132a的直径小于下部导电图案132的直径。在一些实施例中,最顶部导电图案132a之间的间距可为20微米到80微米,且最顶部导电图案132a的直径可在10微米到25微米之间。在一些实施例中,介电层130的材料可类似于介电层114的材料且不同于包封体128的材料。此时,制造集成封装衬底100。在一些实施例中,集成封装衬底100包含电路板结构CBS(即,半完成电路衬底)、重布线层结构RDL1、RDL2以及图案化掩模层112,其中重布线层结构RDL1、RDL2和图案化掩模层112安置在电路板结构CBS的两个相对表面上。在一些实施例中,集成封装衬底100具有例如15吉帕到50吉帕的范围中的高模数。
参看图1G,多个封装组件134A、134B、134C接合到集成封装衬底100的重布线层结构RDL2。在一些实施例中,封装组件134A、134B、134C可通过接合元件140接合到重布线层结构RDL2的暴露的导电图案132a。在一些实施例中,接合元件140可形成在重布线层结构RDL2或封装组件134A、134B、134C上。在一些实施例中,接合元件140为例如微型凸块的焊料区域。在一些实施例中,接合元件140之间的间距可为20微米到80微米,且接合元件140的直径可为5微米到55微米之间。在接合之后,接合元件140通过重布线层结构RDL2电连接到连接件118和管芯120A、120B。
在一些实施例中,封装组件134A、134B、134C中的每一个为封装、器件管芯、管芯堆叠及/或类似者。器件管芯可以是高效能集成电路,例如系统芯片(SoC)管芯、中央处理单元(central processing unit;CPU)、图形处理单元(Graphic Processing Unit;GPU)管芯、现场可编程栅极阵列(field-programmablegate array;FPGA)管芯、移动应用管芯、存储器管芯或管芯堆叠。在一些实施例中,存储器管芯为例如高带宽存储器(High BandwidthMemory;HBM)立方体的存储器立方体。封装组件134A、134B、134C可在各自管芯中具有各自半导体衬底(未绘示)。在一些实施例中,半导体衬底的后表面为根据图1G中所示的定向朝上的表面。封装组件134A、134B、134C更包含在各自半导体衬底的前表面(例如,图1G中面向下的表面)处的集成电路器件(例如包含晶体管的有源器件,未绘示)。在实施例中的一个中,封装组件134A与封装组件134B为SoC管芯,且封装组件134C为HBM立方体。在实施例中,封装组件134C包含管芯堆叠136和在管芯堆叠136底部的控制器138,其中底部填充物可形成在管芯堆叠136的管芯之间和管芯堆叠136与控制器138之间。上文所描述的封装组件134A、134B、134C是出于说明的目的,然而,本公开不意欲限于此。在一些其它实施例中,封装组件134A、134B、134C可具有上文所描述的任何类型的器件或管芯的组合。另外,根据本设计要求,封装组件134A、134B、134C可具有相同或不同大小和功能。
在一些实施例中,封装组件134A、134B、134C分别具有例如接合垫的多个连接件142。在一些实施例中,如图1H中所绘示,在连接件142电连接到重布线层结构RDL2之后,可暴露连接件142的侧壁。在一些替代实施例中,封装组件134A、134B、134C可更包含绝缘层,且连接件142可包埋在绝缘层中,其中绝缘层覆盖每一连接件142的侧壁。在一些替代实施例中,在封装组件134A、134B、134C接合到重布线层结构RDL2之后,底部填充物可形成在封装组件134A、134B、134C旁边,且底部填充物覆盖连接件142的侧壁。在一些实施例中,封装组件134A、134B、134C通过使用倒装芯片接合接合到重布线层结构RDL2。详细地说,封装组件134A、134B、134C的连接件142接合到接合元件140,且封装组件134A、134B、134C的有源表面面向电路板结构CBS。
在一些实施例中,封装组件134A、封装组件134B以及封装组件134C也称为第一封装组件134A、第二封装组件134B以及第三封装组件134C,其中第一封装组件134A与第二封装组件134B相邻,且第二封装组件134B与第三封装组件134C相邻。管芯120A、120B安置在封装组件134A、134B、134C之下和之间,且电连接到封装组件134A、134B、134C。举例来说,在一些实施例中,管芯120A安置在封装组件134A和封装组件134B之下和之间的部位,以便在第一封装组件134A和第二封装组件134B之间提供或建立简短而快速的电连接。类似地,管芯120B可安置在第二封装组件134B和第三封装组件134C之下和之间的部位,以便在第二封装组件134B和第三封装组件134C之间提供或建立简短而快速的电连接。详细地说,第一封装组件134A可通过电路径(或通信路径)与第二封装组件134B通信,所述电路径(或通信路径)由连接件142、接合元件140以及管芯120A的导电图案124形成。在一些实施例中,举例来说,管芯120A、120B在封装组件134A、134B、134C的两个邻近列之间延伸。在其它实施例中,管芯120A和管芯120B内连不彼此邻接的封装组件。举例来说,管芯120A可将第一封装组件134A内连到第三封装组件134C,第二封装组件134B安置在它们之间。
参看图1H,包封体144形成在重布线层结构RDL2上方以包封封装组件134A、134B、134C从而形成封装结构PKS。在一些实施例中,绝缘材料形成在重布线层结构RDL2上方以覆盖封装组件134A、134B、134C。接着,研磨绝缘材料直到暴露封装组件134A、134B、134C,以便形成包封体144。在一些实施例中,包封体144可包含模制底部填充物。包封体144可以是模制化合物、环氧树脂、树脂或类似者。包封体144包封封装组件134A、134B、134C的侧壁,且暴露封装组件134A、134B、134C的后表面。在一些实施例中,包封体144在重布线层结构RDL2的整个顶部表面上方延伸,且包封体144的侧壁实质上与重布线层结构RDL2的侧壁齐平。在一些实施例中,包封体144可以是由模制工艺形成的模制化合物。封装结构PKS的厚度可在50微米到1500微米范围内,且封装结构PKS的宽度可在30毫米到500毫米范围内。在一些实施例中,包封体144在封装组件134A、134B、134C接合到电路板结构CBS上方的重布线层结构RDL2之后形成。换句话说,封装结构PKS在连续形成封装组件134A、134B、134C和电路板结构CBS上方的包封体144之后形成。然而,本公开并不限于此。在一些替代实施例中,预成型封装结构PKS可接合到电路板结构CBS上方的重布线层结构RDL2。
参看图1I,其上具有封装电路板结构CBS自载体C分离。接着,多个导电端146形成在第二叠层BL2上方的图案化掩模层112的开口中。导电端146电连接到电路板结构CBS的第二叠层BL2中的最外面的第二导电图案110B。导电端146可为球栅阵列(ball grid array:BGA)连接件、焊料球、金属柱及/或类似者。在一些实施例中,导电端146可由安装工艺和回焊工艺形成。在一些实施例中,如图1I中所绘示,图案化掩模层112的开口用导电端146填充且图案化掩模层112的顶部表面由导电端146覆盖而导电端146彼此分离。然而,本公开并不限于此。在一些替代实施例中,图案化掩模层112的顶部表面可不由导电端146部分地覆盖。举例来说,图案化掩模层112的开口可部分地用导电端146填充。也就是说,间隙可形成在导电端146与图案化掩模层112之间。在某些实施例中,导电端146可用以安装到额外电组件上(例如,电路载体、系统板、底板等)。在一些替代实施例中,垫可形成在导电端146与最外面的第二导电图案110B之间的图案化掩模层112的开口中。
此时,制造半导体封装件10。在一些实施例中,半导体器件10包含电路板结构CBS、封装结构PKS以及重布线层结构RDL1、RDL2和连接件118以及电路板结构CBS与封装结构PKS之间的管芯120A、120B。在一些实施例中,两个紧邻封装组件(封装组件134A/封装组件134B或封装组件134B/封装组件134C)由其间和其下的管芯120A或管芯120B彼此通信)。然而,本公开并不限于此,且在一些替代实施例中,管芯可安置在封装结构与电路板结构之间的任何部位以将邻近的或彼此不邻近的封装组件进行通信。在一些实施例中,满足封装组件之间的高性能计算和高带宽通信要求,且改良半导体封装件的可靠性。因此,可应用技术以形成具有等于70毫米×70毫米或更大(例如100毫米×100毫米)的超大大小的半导体封装件。另外,半导体封装件的制造通过在例如标准硅制造环境的环境中的一站式(one-stopshop)工艺流程执行。因此,可改良制造半导体封装件的效率,且可增加半导体封装件的良率。此外,通过在半完成电路衬底上方形成RDL,最终衬底具有高模数和降低的厚度,且全部半导体封装件的硬度、电感以及电阻得到增强且成本降低。
图2为根据本公开的一些示例性实施例的半导体封装件的示意性截面图。图2中所示的半导体封装件10A类似于图1I中所示的半导体封装件件10,因此相同附图标号用以指相同和相似部分,且将在本文中省略其实施方式。半导体封装件10与半导体封装件10A之间的差异在于管芯、封装结构以及重布线层结构的配置。举例来说,在图1I中示出的实施例中,管芯120A和管芯120B经设计以电连接到邻近的封装组件134A/封装组件134B以及封装组件134B/封装组件134C。然而,在图2中示出的实施例中,管芯120'可电到全部封装结构PKS而非邻近的封装组件134A、134B、134C。在一些实施例中,管芯120'可安置在包封体128中的重布线层结构RDL1与重布线层结构RDL2之间的任何部位。管芯120'通过重布线层结构RDL2电连接到封装结构PKS。在一些实施例中,管芯120'包含衬底122和在其上的导电图案124。管芯120'为器件管芯,且器件管芯为集成电压调节器(integrated voltageregulator;IVR)管芯、集成无源器件(integrated passive device;IPD)管芯、例如静态随机存取存储器(staticrandom access memory;SRAM)管芯的存储器管芯或类似者,所述管芯是实现具有封装结构PKS的封装组件134A、134B、134C的晶片上系统封装的组件。在一些实施例中,管芯120'可通过其间的粘合层126附接到重布线层结构RDL1上,且管芯120'可通过导体而非与重布线层结构RDL1直接连接。然而,在一些替代实施例中,管芯120'可电连接到重布线层结构RDL1。在一些实施例中,重布线层结构RDL2形成在包封体128上方以电连接到连接件118和管芯120'。在一些实施例中,重布线层结构RDL2的最顶部导电图案132a可为用于球安装的UBM图案。最顶部导电图案132a的直径可类似于下部导电图案132的直径。
在一些实施例中,封装结构PKS可包含系统芯片(SoC)封装、芯片上晶片(Chip-On-Wafer;CoW)封装、集成扇出型(InFO)封装、晶片衬底芯片(Chip-On-Wafer-On-Substrate;CoWoS)封装、其它三维集成电路(3DIC)封装及/或类似者。在一些实施例中,封装结构PKS在接合到重布线层结构RDL2之前可预成型。详细地说,封装结构PKS包含两个或多于两个封装组件(例如如图2中所绘示的三个封装组件134A、封装组件134B以及封装组件134C)、包封封装组件134A、134B、134C的包封体144以及重布线层结构150。在一些实施例中,封装组件134A、134B、134C的连接件142可由如图2中所绘示的包封体144包封,或可交替地安置在随后由包封体144包封的介电层(未绘示)中。在一些实施例中,封装组件134A、封装组件134C可为存储器立方体,且封装组件134B可为CPU、GPU、FPGA或其它合适的高性能集成电路。在一些实施例中,重布线层结构150横越封装组件134A、134B、134C和包封体144且电连接到封装组件134A、134B、134C。重布线层结构150包含交替地堆叠横越封装组件134A、134B、134C上的多个介电层152和多个导电图案154、154a。最外面的导电图案154a用作导电端,所述导电端可包含多个导电柱和多个球下金属(UBM)图案,用于球安装到重布线层结构RDL2。在一些实施例中,封装结构PKS可通过接合元件140接合到重布线层结构RDL2的最顶部导电图案132a。在一些实施例中,接合元件140为例如可控塌陷芯片连接(C4)凸块的焊料区域。接合元件140可形成在重布线层结构RDL2的最顶部导电图案132a或封装结构PKS的最外面的导电图案154a上。在接合之后,可分配(dispense)底部填充物156以保护封装结构PKS与重布线层结构RDL2之间的接合结构。在一些实施例中,包封体144在接合到重布线层结构RDL2之前形成,且因此包封体144的侧壁实质上与重布线层结构150的侧壁齐平而非与重布线层结构RDL2的侧壁齐平。在一些实施例中,从底部填充物156的底部到封装结构PKS的顶部的总厚度可在50微米到1500微米范围内。
在一些实施例中,例如IVR管芯、IPD管芯或SRAM管芯的管芯120'包埋在重布线层结构RDL1与重布线层结构RDL2之间的包封体128中,且电连接到封装结构PKS。换句话说,管芯120'与封装结构PKS整合,且因此可实现晶片上系统或系统级封装(system in package;SiP)。
在一些实施例中,半导体封装件包含电路衬底、在电路衬底上方的重布线层结构、包埋在重布线层结构之间的包封体中的管芯和连接件以及包含在重布线层结构上方的多个封装组件的封装结构。在一些实施例中,管芯为总线管芯或例如IVR管芯、IPD管芯或SRAM的器件管芯,且管芯通过在其周围形成包封体而包埋于重布线层结构与之间。在一些实施例中,通过以上配置,管芯电连接到邻近的封装组件以在没有芯片与封装相互作用的情况下与封装组件通联,且因此可以执行芯片之间的高带宽通信。另外,因为可满足高数据速率、增大带宽以及降低时延的要求,且增加组件之间的可靠性,所以高带宽通信同样可应用到具有超大大小的封装。在一些实施例中,管芯电连接到封装结构以整合封装结构从而提供额外功能,并且因此可实现晶片上系统结构或封装级系统。因此,以上配置可用在高性能计算应用程序中。
根据本公开的一些实施例,一种半导体封装件包含第一重布线层结构、封装结构、总线管芯以及多个连接件。封装结构安置在第一重布线层结构上方,且包含多个封装组件。总线管芯和连接件由封装结构与第一重布线层结构之间的第一包封体包封。总线管芯电连接到多个封装组件中的两个或两个以上,且封装结构通过多个连接件电连接到第一重布线层结构。
在一些实施例中,所述半导体封装件更包括电路板结构,其中所述第一重布线层结构安置在所述电路板结构上方,且所述电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层。
在一些实施例中,所述第一包封体包括模制化合物。
在一些实施例中,所述半导体封装件更包括第二包封体,其中所述多个封装组件由所述第二包封体包封。
在一些实施例中,所述第二包封体的侧壁与所述第一包封体的侧壁齐平。
在一些实施例中,所述半导体封装件更包括第二重布线层结构以及所述第一包封体与所述多个封装组件之间的多个微型凸块,其中所述第二重布线层结构安置在所述第一包封体与所述多个微型凸块之间,且所述总线管芯通过所述第二重布线层结构以及所述多个微型凸块电连接到所述多个封装组件。
在一些实施例中,所述总线管芯通过粘合层粘合到所述第一重布线层结构。
根据本公开的各种实施例,一种半导体封装件包含第一重布线层结构、多个连接件和管芯、第二重布线层结构和封装结构。连接件和管芯由第一包封体包封且安置在第一重布线层结构上方。第二重布线层结构安置在第一包封体上方。封装结构包含多个封装组件且安置在第二重布线层结构上方。管芯通过第二重布线层结构电连接到封装结构且多个连接件电连接第一重布线层结构和第二重布线层结构。
在一些实施例中,所述管芯安置在所述多个封装组件中的两个之间的下方。
在一些实施例中,所述封装结构更包括包封所述多个封装组件的第二包封体。
在一些实施例中,所述封装结构更包括所述多个封装组件与所述第二重布线层结构之间的第三重布线层结构。
在一些实施例中,所述管芯电连接到所述第一重布线层结构。
在一些实施例中,所述半导体封装件更包括电路板结构,其中所述第一重布线层结构安置在所述电路板结构上方,且所述电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层。
在一些实施例中,所述管芯为集成电压调节器管芯、集成无源器件管芯或存储器管芯。
根据本公开的一些实施例,一种制造半导体封装件的方法包含以下步骤。多个连接件形成在第一重布线层结构上方。将管芯安装到第一重布线层结构上。形成第一包封体以包封管芯和多个连接件。第二重布线层结构形成在第一包封体上方以电连接到管芯和连接件。多个封装组件接合到第二重布线层结构上,其中管芯电连接到多个封装组件中的至少两个。
在一些实施例中,所述方法更包括形成第二包封体来包封所述多个封装组件。
在一些实施例中,所述管芯电连接到所述多个封装组件中的邻近的两个。
在一些实施例中,所述将多个封装组件接合到所述第二重布线层结构上包括将封装结构接合到所述第二重布线层结构上,且所述封装结构包括所述多个封装组件、包封所述多个封装组件的第二包封体以及在所述多个封装组件以及所述第二包封体上方的第三重布线层结构。
在一些实施例中,所述方法更包括在所述第二重布线层结构上方形成多个接合元件,其中所述多个封装组件通过所述多个接合元件接合到所述第二重布线层结构。
在一些实施例中,所述方法更包括形成第二包封体来包封所述多个封装组件以及所述接合元件。
在一些实施例中,所述总线管芯包含衬底和所述衬底上的多个导电图案,所述第一包封体位于所述导电图案之间且与所述导电图案的侧壁直接接触,其中所述导电图案的上表面与所述第一包封体和所述导电柱的上表面齐平。
在一些实施例中,所述封装结构包括在水平方向上通过第一间隔隔开的两个相邻封装组件,其中所述两个相邻封装组件通过所述第二重布线层以及安置在所述第一间隔直接下方的所述管芯而彼此电性连接,且所述多个导电柱电连接所述第一重布线层结构以及所述第二重布线层结构。
前文概述数个实施例的特征以使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解,其可容易地将本公开用作设计或修改用于实现本文中引入的实施例的相同目的及/或达成相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到,这些等效构造并不脱离本公开的精神和范围,且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代以及更改。
Claims (10)
1.一种半导体封装件,包括:
电路板结构,包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层;
第一重布线层结构,在所述电路板结构上方,所述第一重布线层结构包括第一介电层;
第二重布线层结构,在所述电路板结构上方,所述第二重布线层结构包括第二介电层;
第一包封体,位于所述第一介电层与所述第二介电层之间;
封装组件,在所述第一重布线层结构上方,包括多个封装组件;以及
总线管芯以及多个导电柱,其中所述第一包封体沿着所述总线管芯的整个侧壁延伸,所述总线管芯的表面与所述所述第一包封体及所述多个导电柱的上表面共面,所述总线管芯电连接所述多个封装组件中的两个或更多个,以及所述多个封装组件分别通过所述多个导电柱与所述第一重布线层结构电连接。
2.根据权利要求1所述的半导体封装件,其中所述第一包封体包括模制化合物。
3.根据权利要求1所述的半导体封装件,更包括第二包封体,其中所述多个封装组件由所述第二包封体包封。
4.根据权利要求3所述的半导体封装件,其中所述第二包封体的侧壁与所述第一包封体的侧壁齐平。
5.根据权利要求1所述的半导体封装件,更包括多个微型凸块,所述多个微型凸块位于所述第一包封体与所述第一封装组件之间以及所述第一包封体与所述多个封装组件之间,其中所述第二重布线层结构安置在所述第一包封体与所述多个微型凸块之间,且所述总线管芯通过所述第二重布线层结构以及所述多个微型凸块电连接所述第一封装组件与所述第二封装组件。
6.根据权利要求1所述的半导体封装件,其中所述总线管芯通过粘合层粘合到所述第一重布线层结构,以及所述粘合层与所述第一重布线层结构的多个导电图案直接接触。
7.一种半导体封装件,包括:
第一重布线层结构;
多个导电件以及管芯,所述多个导电柱以及所述管芯由第一包封体包封,其中所述管芯的底表面与所述第一重布线层结构的表面粘合;
第二重布线层结构,安置在所述第一包封体上方,其中所述第一重布线层结构包括第一通孔以及与所述第一通孔一体成形且具有宽度大于所述第一通孔的第一导线,所述第二重布线层结构包括第二通孔以及与所述第二通孔一体成形且具有宽度大于所述第二通孔的第二导线,所述第二通孔位于所述第一导线及所述第二导线之间且所述第一导线位于所述第一通孔与所述第二通孔之间;以及
封装结构,安置在所述第二重布线层结构上方且包括多个封装组件,包所述管芯通过所述第二重布线层结构与所述封装结构电连接,且所述多个导电件电连接所述第一重布线层结构与所述第二重布线层结构,其中所述第一重布线层结构的侧壁、所述第二重布线层结构的侧壁以及所述第一包封体的侧壁齐平。
8.根据权利要求7所述的半导体封装件,更包括电路板结构,其中所述第一重布线层结构安置在所述电路板结构上方,且所述电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层,所述第一叠层位于所述第一重布线层结构与所述第二重布线层结构之间且包括第三通孔以及与所述第三通孔一体成形且具有宽度大于所述第三通孔的第三导线,且所述第三通孔位于所述第三导线与所述核心层之间。
9.一种制造半导体封装件的方法,包括:
提供电路板结构,所述电路板结构包含核心层、在所述核心层的第一表面上的第一叠层以及在与所述第一表面相对的所述核心层的第二表面上的第二叠层;
直接在所述第一叠层上形成多个第一介电层和位于所述多个第一介电层中且交替地堆叠的多个第一金属线和多个第一通孔,以形成第一重布线层结构;
直接在所述第一重布线层结构上形成多个导电柱;
将管芯安装到所述第一重布线层结构上且位于两相邻所述导电柱之间;
形成第一包封体以包封所述管芯以及所述多个导电柱,所述多个导电柱环绕所述管芯;
直接在所述第一包封体上方形成第二重布线层结构,以电连接所述管芯以及所述多个导电柱;以及
将多个封装组件接合到所述第二重布线层结构上,其中所述管芯电连接到所述多个封装组件中的至少两个。
10.根据权利要求9所述的制造半导体封装件的方法,其中,更包括
在形成第一重布线层结构之前,在所述第二叠层上形成图案化掩模层,所述图案化掩模层包括多个开口;以及
在将多个封装组件接合到所述第二重布线层结构上之后,分别在所述开口中形成导电端,所述导电端电连接到所述电路板结构,所述导电端部分地填充所述开口,使得间隙形成在所述导电端与所述图案化掩模层之间。
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