CN109390325A - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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Publication number
CN109390325A
CN109390325A CN201810105515.6A CN201810105515A CN109390325A CN 109390325 A CN109390325 A CN 109390325A CN 201810105515 A CN201810105515 A CN 201810105515A CN 109390325 A CN109390325 A CN 109390325A
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electronic building
building brick
conducting element
top surface
circuit layer
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CN201810105515.6A
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CN109390325B (zh
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方仁广
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装装置包含：电路层，其具有顶部表面；第一电子组件，其安置于所述电路层的所述顶部表面上；以及第一导电元件，其安置于所述电路层的所述顶部表面上，所述第一导电元件具有顶部表面。所述第一电子组件具有作用表面和面向所述电路层的所述顶部表面的后表面。所述第一电子组件的所述作用表面与所述电路层的所述顶部表面之间的距离大于所述第一导电元件的所述顶部表面与所述电路层的所述顶部表面之间的距离。

Description

半导体封装装置及其制造方法
技术领域
本发明大体上涉及一种半导体封装装置及其制造方法,且涉及一种包含堆叠结构的半导体封装装置及其制造方法。
背景技术
半导体封装装置可包含多个芯片以增加其性能和功能性。所述多个芯片可垂直堆叠，以减少半导体封装装置的水平占用面积。在此配置中，顶部芯片的第一表面可附接到底部芯片的第一表面，而顶部芯片的第二作用表面暴露。为了在后续制造工艺中移动堆叠芯片，可使用具有相对较宽开口的喷嘴来避免对顶部芯片的暴露作用表面上的电路结构的损害(注意，暴露的电路结构可邻近于顶部芯片的作用表面的中心)。所述喷嘴的相对较宽的开口可占用封装中相对较大的空间。举例来说，可使若干导电元件(其可环绕堆叠芯片)中的每一者与所述堆叠芯片之间的距离较大，以避免在挑选或放入堆叠芯片时与喷嘴碰撞，这可妨碍半导体封装装置的小型化。
发明内容
在一或多个实施例中，根据一个方面，一种半导体封装装置包含：电路层，其具有顶部表面；第一电子组件，其安置于所述电路层的所述顶部表面上；以及第一导电元件，其安置于所述电路层的所述顶部表面上，所述第一导电元件具有顶部表面。所述第一电子组件具有作用表面和面向所述电路层的所述顶部表面的后表面。第一电子组件的作用表面与电路层的顶部表面之间的距离大于第一导电元件的顶部表面与电路层的顶部表面之间的距离。
在一或多个实施例中，根据另一方面，一种半导体封装装置包含电路层和安置于所述电路层上的第一电子组件，所述第一电子组件具有第一侧表面和与所述第一侧表面相对的第二侧表面。所述半导体封装装置进一步包含接合线，其越过包含第一电子组件的第一侧表面的平面，且将第一电子组件连接到电路层。所述半导体封装装置进一步包含：第一导电元件，其安置于所述电路层上，且邻近于所述第一侧表面；以及第二导电元件，其安置于所述电路层上，且邻近于所述第二侧表面。第一导电元件的高度小于第二导电元件的高度。
在一或多个实施例中，根据另一方面，一种半导体封装装置包含：电路层；第一电子组件，其安置于所述电路层上；以及第一导电元件，其安置于所述电路层上，且具有顶部表面。所述半导体封装装置进一步包含：第二导电元件，其安置于所述电路层上，且具有顶部表面；以及封装主体，其包封所述第一电子组件、所述第一导电元件和所述第二导电元件。所述封装主体具有顶部表面，且界定：第一凹部，其从封装主体的顶部表面延伸到第一导电元件的顶部表面；以及第二凹部，其从封装主体的顶部表面延伸到第二导电元件的顶部表面。第一凹部的深度不同于第二凹部的深度。
在一或多个实施例中，根据另一方面，一种制造半导体封装装置的方法包含：提供电路层；以及在所述电路层上形成第一导电元件和第二导电元件的第一部分。所述制造半导体封装装置的方法进一步包含：在第二导电元件的第一部分上形成第二导电元件的第二部分；以及将第一电子组件安置在所述电路层上以及第一导电元件与第二导电元件之间。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本发明的各方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述的清楚起见而任意增大或减小。
图1说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图2A、图2B、图2C、图2D、图2E、图2F和图2G说明根据本发明的一些实施例的制造半导体封装装置的方法。
图3A说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图3B说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图3C说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图3D说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图3E说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图4A和图4B说明根据本揭示的一些实施例的半导体封装装置的不同类型。
图5说明根据本发明的一些实施例的半导体封装装置的横截面视图。
图6A、图6B、图6C、图6D、图6E、图6E'、图6F、图6G、图6H和图6I说明根据本发明的一些实施例的制造半导体封装装置的方法。
贯穿图式和具体实施方式使用共同参考数字来指示相同或类似元件。根据以下结合附图进行的详细描述将容易地理解本发明。
具体实施方式
图1说明根据本发明的一些实施例的半导体封装装置1的横截面视图。半导体封装装置1包含电路层10；电子组件11a、11b、11c；封装元件12和导电元件13。
电路层10包含电介质层，或由电介质层10d至少部分地包封或覆盖的绝缘层10d和导电层10r1、10r2(其可包含例如金属层)。导电层10r1和10r2物理上彼此分离，且通过导电互连10v1(例如通孔)电连接。在一些实施例中，电路层10可包含任何数目的电介质层和导电层。举例来说，电路层10可包含N个电介质层和导电层，其中N为整数。在一些实施例中，电介质层10d可包含有机组件、焊接掩模、聚酰亚胺(PI)、环氧树脂、味之素堆积膜(ABF)或模制化合物。
导电层10r2从电介质层10d暴露，以提供电路层10的顶部表面101(还被称作第一表面)上或处的电连接。电路层10可包含其底部表面102(还被称作第二表面)的多个导电垫10p。电接点10b安置于电路层10的导电垫10p上。在一些实施例中，电接点10b包含可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)或栅格阵列封装(LGA)。
电子组件11a安置于电路层10的顶部表面101上。电子组件11a具有面朝电路层10的顶部表面101的作用表面11a1，以及与作用表面11a1相对的后表面11a2。电子组件11a可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。
电子组件11b安置于电子组件11a的后表面11a2上。电子组件11b具有作用表面11b1，以及面朝电子组件11a的后表面11a2的后表面11b2。在一些实施例中，电子组件11b的后表面11b2通过粘合剂11h(例如胶水或胶带)附接到电子组件11a的后表面11a2。电子组件11b可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。在一些实施例中，电子组件11b的面积(例如电子组件11b的占用面积，或后表面11b2的面积)可大于、等于或小于电子组件11a的面积，取决于设计规范。
导电元件13(例如导电柱)安置于电路层10的导电层10r2上，且物理上与电子组件11a分开。在一些实施例中，导电元件13包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钛(Ti)、钨(Wu)、镍(Ni)或其它合适的金属或合金。在一些实施例中，导电元件的顶部表面131可为大体上圆形、正方形、矩形或三角形。
在一些实施例中，电子组件11b的作用表面11b1与电路层10的顶部表面101之间的距离D1大于导电元件13的顶部表面131与电路层10的顶部表面101之间的距离D2(例如导电元件13的高度)。举例来说，导电元件13的顶部表面131安置在比电子组件11b的作用表面11b1低的位置处。在一些实施例中，D2至多约D1的0.98倍或以下，至多约D1的0.95倍或以下，或至多约D1的0.9倍或以下。在一些实施例中，D1与D2之间的差小于或等于约220微米(μm)。在一些实施例中，导电元件13与电子组件11a之间的距离D3(例如最短距离)在从约1.89μm到约1432.2μm的范围内。
封装主体12安置于电路层10的顶部表面101上，且覆盖或包封导电层10r2、电子组件11a、电子组件11b和导电元件13。电子组件11b的作用表面11b1上的电接点11bc以及导电元件13的顶部表面131从封装主体12暴露。举例来说，封装主体12界定开口12h1、12h2或凹部，其分别暴露电子组件11b的作用表面11b1和导电元件13的顶部表面131上的电接点11bc。在一些实施例中，开口12h1、12h2中的至少一者的宽度可大于、等于或小于导电元件13的宽度，取决于设计规范。在一些实施例中，封装主体12包含(例如)有机材料(例如模制化合物、双马来酰亚胺三嗪(BT)、PI、聚苯并恶唑(PBO)、阻焊剂、ABF、聚丙烯(PP)或基于环氧树脂的材料)、无机材料(例如硅、玻璃、陶瓷或石英)、液体和/或干式膜材料或其组合。
晶种层13s安置于封装主体12的顶部表面121上，且在开口12h1、12h2内延伸。导电层13m安置于晶种层13s上。举例来说，导电层13m安置在封装主体12的顶部表面121之上，且在开口12h1、12h2内延伸，以将电子组件11b的作用表面11b1上的电接点11bc电连接到导电元件13的顶部表面131。在一些实施例中，导电层13m包含Cu、Ag、Au、Pt、Al或焊料合金。
电子组件11c安置于封装主体12的顶部表面121上。电子组件11c具有面朝封装主体12的顶部表面121的作用表面11c1。在一些实施例中，电子组件11c安置于封装主体12的顶部表面121上的导电层13m上，且通过导电层13m电连接到电子组件11b和/或导电元件13。电子组件11c可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。
在一些实施例中，底填充料13u可安置于封装主体12的顶部表面121上，以覆盖电子组件11c的作用表面11c1。在一些实施例中，底填充料13u包含环氧树脂、模制化合物(例如环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底填充料13u可包含毛细管底填充料(CUF)或模塑底填充料(MUF)。
图2A、2B、2C、2D、2E、2F和2G是根据本发明的一些实施例的各个制造阶段处的半导体结构的横截面视图。各图已简化，以提供对本发明的各方面的较好理解。在一些实施例中，图2A、2B、2C、2D、2E、2F和2G中所示的结构用以制造图1中所示的半导体封装装置1。或者，图2A、2B、2C、2D、2E、2F和2G中所示的结构可用以制造其它半导体封装裝置。
参看图2A，提供载体29。金属层29m形成于载体29上，且接着电路层10形成于金属层29m上。电路层10包含电介质层，或由电介质层10d至少部分地包封或覆盖的绝缘层10d和导电层10r1、10r2(其可包含例如金属层)。导电层10r1和10r2物理上彼此分离，且通过导电互连10v1(例如通孔)电连接。在一些实施例中，电路层10可通过以下操作形成：(i)在金属层29m上形成光致抗蚀剂或掩模；(ii)例如通过光刻技术，在光致抗蚀剂或掩模上界定预定图案；(iii)电镀导电材料以形成经图案化的导电层10r1、10r2；以及(iv)去除所述光致抗蚀剂或掩模。在一些实施例中，导电层10r1的间距大于导电层10r2的间距。
参看图2B，光致抗蚀剂或掩模28安置于电路层10的顶部表面101上。光致抗蚀剂28界定多个开口，其暴露导电层10r2的一部分。导电元件13例如通过电镀或其它合适的工艺形成于开口内。
参看图2C，去除光致抗蚀剂28，且将电子组件11a放置在电路层10的顶部表面101上。电子组件11a具有面朝电路层10的顶部表面101的作用表面11a1，以及与作用表面11a1相对的后表面11a2。在一些实施例中，电子组件11a通过使用真空喷嘴27a放置在电路层10的顶部表面101上。
为了避免真空喷嘴27a与导电元件13之间的碰撞，电子组件11a与导电元件13之间的距离D3可设定成满足以下等式：
其中D2是导电元件13的高度；T1是电子组件的厚度；G1是电子组件11a的作用表面11a1与电路层10的顶部表面101之间的距离；Tc是对应于电子组件11a的大小的变化的术语(例如对应于其制造方法的电子组件11a的宽度的标准偏差)；Wt是对应于导电元件13的宽度的变化的术语(例如以上文所描述的方式制造的导电元件13的宽度的标准偏差)；以及θ1是由真空喷嘴27a的侧表面和电子组件11a的后表面11a2的延长部分界定。在一些实施例中，θ1在从约2o和约88o的范围内。举例来说，在T1在从约50μm到约100μm的范围内的情况下，D2在从约30μm到约100μm的范围内，G1在从约10μm到约30μm的范围内，Wt在从约0.1μm到约0.2μm的范围内，且Tc在从约0.05μm到约10μm的范围内，电子组件11a与导电元件13之间的距离D3可从等式(1)到处为在从约1.89μm到约1432.2μm的范围内。
参看图2D，电子组件11b放置在电子组件11a的后表面11a2上。电子组件11b具有作用表面11b1，以及面朝电子组件11a的后表面11a2的后表面11b2。在一些实施例中，电子组件11b的后表面11b2通过粘合剂11h(例如胶水或胶带)附接到电子组件11a的后表面11a2。在一些实施例中，电子组件11b通过使用真空喷嘴27b放置在电子组件11a的后表面11a2上。
如图2D所示，电子组件11b的作用表面11b2与真空喷嘴27b的底部表面27b1之间的距离D4可通过以下等式来表达：
Tc2×tanθ2≤D4≤T2 Eq.(2)，
其中Tc2是电子组件11b的大小的变化(例如对应于其制造方法的电子组件11b的宽度的标准偏差)；θ2是由真空喷嘴27b的内部侧表面和电子组件11b的作用表面11b1界定的角度；且T2是电子组件11b的厚度。在一些实施例中，θ2在从约2o和约88o的范围内。举例来说，在T2在从约50μm到约100μm的范围内且Tc2在从约0.05μm到约10μm的范围内的情况下，电子组件11b的作用表面11b2与真空喷嘴27b的底部表面27b1之间的距离D4可从等式(2)导出为在从约0.35μm到约100μm的范围内。
为了避免真空喷嘴27b与导电元件13之间的碰撞，电子组件11b的作用表面11b1与导电元件13的顶部表面131之间的距离D5(对应于D1到D2)可设定成满足以下等式：
D5≤T1+T2+Ta+G1-D2 Eq.(3)，
其中Ta是粘合剂11h的厚度。举例来说，在T1或T2在从约50μm到约100μm的范围内的情况下，D2在从约30μm到约100μm的范围内，G1在从约10μm到约30μm的范围内，Ta在从约10μm到约20μm的范围内，电子组件11b的作用表面11b1与导电元件13的顶部表面131之间的距离D5可从等式(3)导出为在从零μm(即，电子组件11b的作用表面11b1和导电元件13的顶部表面131彼此大体上共面)到约220μm的范围内。
通过使用具有小于电子组件11b的作用表面11b1与电路层10的顶部表面101之间的距离D1的高度D2的导电元件13(例如选择大于零的距离D5)，可减小导电元件13与电子组件11a之间的距离D3，同时仍实现将电子组件11b放置在电子组件11a上。因此，还可减小半导体封装装置的尺寸。
参看图2E，封装主体12形成于电路层10的顶部表面101上，以覆盖电子组件11a、11b和导电元件13。在一些实施例中，封装主体12包含(例如)有机材料(例如模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)、无机材料(例如硅、玻璃、陶瓷或石英)、液体和/或干式膜材料或其组合。封装主体12可通过模制技术(例如，转移模制或压缩模制)形成。
参看图2F，多个开口12h1、12h2形成于封装主体12中，以暴露电子组件11b的作用表面11b1和导电元件13的顶部表面131上的电接点11bc。在一些实施例中，开口可通过激光钻孔、蚀刻或其它合适的工艺形成。在一些实施例中，开口12h1、12h2的宽度可大于、等于或小于导电元件13的宽度，取决于设计规范。
晶种层13s形成于封装主体12的顶部表面121上，且在开口12h1、12h2内延伸。导电层13m接着形成于晶种层13s上。举例来说，导电层13m形成于封装主体12的顶部表面121之上，且在开口12h1、12h2内延伸。在一些实施例中，晶种层13s和导电层13m可通过以下操作形成：(i)在封装主体12的顶部表面121上形成晶种层，且通过使用化学气相沉积(CVD)或物理气相沉积(PVD)在开口12h1、12h2内延伸；(ii)将光致抗蚀剂或掩模放置在晶种层上；(iii)例如通过光刻技术在光致抗蚀剂或掩模上界定预定图案；(iv)将导电材料安置或形成在晶种层上，以形成经图案化的导电层；(v)去除所述光致抗蚀剂或掩模；以及(vi)去除晶种层的不由经图案化的导电层覆盖的部分。在一些实施例中，在操作(iv)中，可通过电镀、无电极电镀、溅镀、膏体印刷、撞击或接合，在晶种层上形成导电材料。
参看图2G，电子组件11c放置在封装主体12的顶部表面121上的导电层13m上，且通过导电层13m电连接到电子组件11b和/或导电元件13。在一些实施例中，底填充料13u可形成于封装主体12的顶部表面121上，以覆盖电子组件11c的作用表面11c1。在一些实施例中，底填充料13u包含环氧树脂、模制化合物(例如环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底填充料13u可包含CUF或MUF。
去除载体29，且去除金属层29m的一部分，以形成导电层10的导电垫10p。在一些实施例中，可例如通过蚀刻或其它合适的工艺来去除金属层29m的所述部分。接着在导电垫10p上形成电接点10b，以形成如图1中所示的半导体封装装置1。在一些实施例中，电接点10b可包含C4凸块、BGA或LGA。在一些实施例中，可通过电镀、无电极电镀、溅镀、膏体印刷、撞击或接合来形成电接点10b。
图3A说明根据本发明的一些实施例的半导体封装装置3A的横截面视图。半导体封装装置3A类似于图1中所示的半导体封装装置1，不同之处在于半导体封装装置3A进一步包含焊料31。
焊料31安置于图1中所示的封装主体12的开口12h2内。焊料31电连接到导电元件13的顶部表面131。在一些实施例中，可省略开口12h2内的晶种层13s和导电层13m，且焊料31可直接接触导电元件13的顶部表面131。或者，晶种层13s和导电层13m安置于开口12h2内，且接触导电元件13的顶部表面131，且因此焊料31安置于导电层13m上。
图3B说明根据本发明的一些实施例的半导体封装装置3B的横截面视图。半导体封装装置3B类似于图1中所示的半导体封装装置1，不同之处在于电子组件11c包含一或多个焊料球32，其安置于图1中所示的封装主体12的开口12h2内，且电连接到导电元件13的顶部表面131。
图3C说明根据本发明的一些实施例的半导体封装装置3C的横截面视图。半导体封装装置3C类似于图1中所示的半导体封装装置1，不同之处在于半导体封装装置3C包含在适当的位置处的电子组件31c或电子组件11c。电子组件31c的后表面31c2面朝封装主体12的顶部表面121。电子组件31c具有与后表面31c2相对的前表面31c1。半导体封装装置3C的电子组件31c通过接合线31w电连接到导电层13m。接合线31w可附接到前表面31c1。
图3D说明根据本发明的一些实施例的半导体封装装置3D的横截面视图。半导体封装装置3D类似于图1中所示的半导体封装装置1，不同之处在于半导体封装装置3D进一步包含电子组件31d，其安置于电子组件11a的后表面11a2上，且邻近于电子组件11b。在一些实施例中，电子组件11a上的电子组件的数目或电路层10上的电子组件的数目取决于设计规范而变化。
图3E说明根据本发明的一些实施例的半导体封装装置3E的横截面视图。半导体封装装置3E类似于图1中所示的半导体封装装置1，不同之处在于半导体封装装置3E进一步包含电子组件31e和电子组件31d。电子组件31e安置于电路层10上，且与电子组件11a隔开。电子组件31d安置在电子组件31e上。
图4A和4B说明根据本发明的一些实施例的不同类型的半导体封装裝置。
如图4A所示，多个芯片40或裸片放置在大体上正方形的载体41上。在一些实施例中，载体41可包含有机材料(例如，模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)和/或无机材料(例如，硅、玻璃、陶瓷或石英)。
如图4B所示，多个芯片40或裸片放置在大体上圆形的载体42上。在一些实施例中，载体42可包含有机材料(例如模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)或无机材料(例如硅、玻璃、陶瓷或石英)。
图5说明根据本发明的一些实施例的半导体封装装置5的横截面视图。半导体封装装置5包含电路层50；电子组件51a、51b、51c、51d；封装主体52和导电元件53a、53b。
电路层50包含电介质层，或至少部分地由电介质层50d包封或覆盖的绝缘层50d和导电层50r1、50r2(其可包含例如金属层)。导电层50r1和50r2物理上彼此分离，且通过导电互连50v1(例如通孔)电连接。在一些实施例中，电路层50可包含任何数目的电介质层和导电层。举例来说，电路层50可包含N个电介质层和导电层，其中N为整数。在一些实施例中，电介质层50d可包含有机化合物、焊接掩模、PI、环氧树脂、ABF或模制化合物。
导电层50r2从电介质层50d暴露，以提供电路层50的顶部表面501(还被称作第一表面)上的电连接。电路层50可包含其底部表面502(还被称作第二表面)的多个导电垫50p。电接点50b安置于电路层50的导电垫50p上。在一些实施例中，电接点50b包含C4凸块、BGA或LGA。
电子组件51a安置于电路层50的顶部表面501上。电子组件51a具有作用表面51a1、面朝电路层50的顶部表面501的后表面51a2、在作用表面51a1与后表面51a2之间延伸的第一侧表面51a3，以及与第一侧表面51a3相对的第二侧表面51a4。电子组件51a可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。在一些实施例中，电子组件51a的作用表面51a1上的一或多个导电接点通过接合线51w连接到导电层50r2。在一些实施例中，接合线51w横穿平面，所述平面包含电子组件51a的第一侧表面51a3或与之对准，以将电子组件51a连接到电路层50。
电子组件51b安置于电子组件51a的作用表面51a1上。电子组件51b具有面朝电子组件51a的作用表面51a1的作用表面51b1，以及与作用表面51a1相对的后表面51b2。在一些实施例中，电子组件51b的作用表面51b1上的一或多个导电接点电连接到电子组件51a的作用表面51a1上的导电接点，其不通过接合线51w电连接到电路层50的导电层50r2。电子组件51b可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。
电子组件51c安置于电子组件51b的后表面51b2上。电子组件51c具有作用表面51c1以及面朝电子组件51b的后表面51b2的后表面51c2。在一些实施例中，电子组件51c的后表面51c2通过粘合剂51h(例如胶水或胶带)附接到电子组件51b的后表面51b2。电子组件51c可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。
导电元件53a(例如导电柱，还称为“第一导电元件”)安置于电路层50的导电层50r2上。导电元件53a邻近于电子组件51a的侧表面51a3，且物理上与电子组件51a隔开。举例来说，导电元件53a邻近于接合线51w。在一些实施例中，导电元件53a包含Au、Ag、Cu、Pt、Ti、Wu、Ni或其它合适的金属或合金。在一些实施例中，导电元件53a的顶部表面53a1可为大体上圆形、正方形、矩形或三角形。
导电元件53b(例如导电柱，还称为“第二导电元件”)安置于电路层50的导电层50r2上。导电元件53b邻近于电子组件51a的侧表面51a4，且物理上与电子组件51a隔开。举例来说，导电元件53b更远离接合线51w(例如与导电元件53a相比，更远离接合线w1)。在一些实施例中，导电元件53b包含Au、Ag、Cu、Pt、Ti、Wu、Ni或其它合适的金属或合金。在一些实施例中，导电元件53b的顶部表面53b1可为大体上圆形、正方形、矩形或三角形。
在一些实施例中，导电元件53b的高度D51(例如导电元件53b的顶部表面53b1与电路层50的顶部表面501之间的距离)大于导电元件53a的高度D52(例如导电元件53a的顶部表面53a1与电路层50的顶部表面501之间的距离)。在一些实施例中，D51与D52之间的差(例如导电元件53b的顶部表面53b1与导电元件53a的顶部表面53a1之间垂直位置的差异)大于约5μm。在一些实施例中，D52至多约D51的0.98倍或以下，至多约D51的0.95倍或以下，或至多约D51的0.9倍或以下。在一些实施例中，作用表面51c1与电路层50的顶部表面501之间的距离大于导电元件53b的高度D51。在一些实施例中，电子组件51a与导电元件53b之间的距离D53小于电子组件51a与导电元件53a之间的距离D54。在一些实施例中，电子组件51a与导电元件53b之间的距离D53大于约100μm。在一些实施例中，电子组件51a与导电元件53a之间的距离D54大于约200μm。
封装主体52安置于电路层50的顶部表面501上，且覆盖或包封导电层50r2；电子组件51a、51b；电子组件51c；导电元件53a和导电元件53b。电子组件51c的作用表面51c1上的电接点51cc、导电元件53a的顶部表面53a1以及导电元件53b的顶部表面53b1从封装主体52暴露。举例来说，封装主体52界定开口52h1、52h2、53h3或凹部，其暴露电子组件51c的作用表面51c1、导电元件53a的顶部表面53a1和导电元件53b的顶部表面53b1上的电接点51cc。
在一些实施例中，开口52h2的宽度可大于、等于或小于导电元件53a的宽度，取决于设计规范。在一些实施例中，开口52h3的宽度可大于、等于或小于导电元件53b的宽度，取决于设计规范。在一些实施例中，开口52h2的深度D55(例如封装主体52的顶部表面521与导电元件53a的顶部表面53a1之间的距离)大于开口53h3的深度D56(例如封装主体52的顶部表面521与导电元件53b的顶部表面53b1之间的距离)。在一些实施例中，封装主体52的顶部表面521与电子组件51c的作用表面51c1之间的距离D57小于开口53h3的深度D56和/或开口53h2的深度D55。
在一些实施例中，封装主体52包含(例如)有机材料(例如模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)、无机材料(例如硅、玻璃、陶瓷或石英)、液体和/或干式膜材料或其组合。
晶种层53s安置于封装主体52的顶部表面521上，且在开口52h1、52h2和52h3内延伸。导电层53m安置于晶种层53s上。举例来说，导电层53m安置在封装主体52的顶部表面521之上，且在开口52h1、52h2和52h3内延伸，以将电子组件51c的作用表面51c1上的电接点51cc电连接到导电元件53a的顶部表面53a1和/或导电元件53b的顶部表面53b1。在一些实施例中，导电层53m包含Cu、Ag、Au、Pt、Al或焊料合金。
电子组件51d安置于封装主体52的顶部表面521上。电子组件51d具有面朝封装主体52的顶部表面521的作用表面51d1。在一些实施例中，电子组件51d安置于封装主体52的顶部表面521上的导电层53m上，且通过导电层53m电连接到电子组件51c和/或导电元件51a、51b。电子组件51d可包含芯片或裸片，其包含半导体衬底、一或多个集成电路装置以及其中的一或多个上覆互连结构。所述集成电路装置可包含有源装置，例如晶体管和/或无源装置，例如电阻器、电容器、电感器或其组合。
在一些实施例中，底填充料53u可安置于封装主体52的顶部表面521上，以覆盖电子组件51d的作用表面51d1。在一些实施例中，底填充料53u包含环氧树脂、模制化合物(例如环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底填充料53u可包含CUF或MUF。
图6A、6B、6C、6D、6E、6E'、6F、6G、6H和6I是根据本发明的一些实施例的各个制造阶段处的半导体结构的横截面视图。各图已简化，以提供对本发明的各方面的较好理解。在一些实施例中，图6A、6B、6C、6D、6E、6F、6G、6H和6I中所示的结构用以制造图5中所示的半导体封装装置5。或者，图6A、6B、6C、6D、6E、6F、6G、6H和6I中所示的结构可用以制造其它半导体封装裝置。
参看图6A，提供载体69。金属层69m形成于载体69上，且接着电路层50形成于金属层69m上。电路层50包含电介质层，或至少部分地由电介质层50d包封或覆盖的绝缘层50d和导电层50r1、50r2(其可包含例如金属层)。导电层50r1和50r2物理上彼此分离，且通过导电互连50v1(例如通孔)电性连接。在一些实施例中，电路层50可通过以下操作形成：(i)在金属层69m上形成光致抗蚀剂或掩模；(ii)例如通过光刻技术，在光致抗蚀剂或掩模上界定预定图案；(iii)电镀导电材料以形成经图案化的导电层50r1、50r2；以及(iv)去除所述光致抗蚀剂或掩模。在一些实施例中，导电层50r1的间距大于导电层50r2的间距。
参看图6B，光致抗蚀剂或掩模68a安置于电路层50的顶部表面501上。光致抗蚀剂68a界定多个开口，其暴露导电层50r2的一部分。导电元件53a和53b'例如通过电镀或其它合适的工艺形成于所述开口内。在一些实施例中，导电元件53b'是图5中所示的导电元件53b的第一部分。
参看图6C，光致抗蚀剂或掩模68b安置于光致抗蚀剂68a上。光致抗蚀剂68b界定暴露图6B中形成的导电层53b'的开口。导电元件53b”例如通过电镀或其它合适的工艺形成于开口内。在一些实施例中，导电元件53b”是图5中所示的导电元件53b的第二部分。导电元件53b'和导电元件53b”连接以形成导电元件53b。
参看图6D，去除光致抗蚀剂68a和68b，且将电子组件51a放置在电路层50的顶部表面501上。电子组件51a具有作用表面51a1，以及面朝电路层10的顶部表面501的后表面51a2。在一些实施例中，电子组件51a通过使用真空喷嘴67a放置在电路层50的顶部表面501上。
电子组件51b放置在电子组件51a上。电子组件51b具有面朝电子组件51a的作用表面51a1的作用表面51b1，以及后表面51b2。在一些实施例中，电子组件51b通过使用真空喷嘴67a放置在电子组件51a上。
参看图6E，接合线51w形成或安置成将电子组件51a的作用表面51a1上的导电接点的一部分电连接到电路层50的导电层50r2。在一些实施例中，接合线51w由接合机67b形成。如上文所描述，导电元件53a的高度D52小于导电元件53b的高度D51，且电子组件51a与导电元件53a之间的距离D54大于电子组件51a与导电元件53b之间的距离D53。这可帮助防止接合机67b与导电元件53a或电子组件51a之间的碰撞。
在其它实施例中，如图6E'所示，电子组件51b'放置在电子组件51a上。图6E'中所示的操作类似于图6D和图6E中所示的那些操作，不同之处在于在图6E'中，电子组件51b'的后表面51b1面朝电子组件51a的作用表面51a1。在一些实施例中，电子组件51b'通过使用真空喷嘴放置在电子组件51a上。接着形成或安置接合线51w，以将电子组件51a的作用表面51a1上的导电接点的一部分电连接到电路层50的导电层50r2。
参看图6F，电子组件51c放置在电子组件51b上。电子组件51c具有作用表面51c1，以及面朝电子组件51b的后表面51b2的后表面51c2。在一些实施例中，电子组件51c通过使用真空喷嘴67c放置在电子组件51b上。
参看图6G，封装主体52形成于电路层50的顶部表面501上，以覆盖电子组件51a、51b、51c和导电元件53a、53b。在一些实施例中，封装主体52包含(例如)有机材料(例如模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)、无机材料(例如硅、玻璃、陶瓷或石英)、液体和/或干式膜材料或其组合。封装主体52可通过模制技术(例如，转移模制或压缩模制)形成。
参看图6H，多个开口52h1、52h2和52h3形成于封装主体52中，以暴露电子组件51c的作用表面51c1、导电元件53a的顶部表面53a1和导电元件53b的顶部表面53b1上的电接点51cc。在一些实施例中，开口可通过激光钻孔、蚀刻或其它合适的工艺形成。
晶种层53s形成于封装主体52的顶部表面521上，且在开口52h1、52h2、52h3内延伸。导电层53m接着形成于晶种层53s上。举例来说，导电层53m形成于封装主体52的顶部表面521之上，且在开口52h1、52h2、52h3内延伸。在一些实施例中，晶种层53s和导电层53m可通过以下操作形成：(i)在封装主体52的顶部表面521上形成晶种层，且其通过使用CVD或PVD在开口52h1、52h2、52h3内延伸；(ii)将光致抗蚀剂或掩模放置在晶种层上；(iii)例如通过光刻技术，在光致抗蚀剂或掩模上界定预定图案；(iv)在晶种层上安置或形成导电材料以形成经图案化的导电层；(v)去除所述光致抗蚀剂或掩模；以及(vi)去除晶种层的不由经图案化的导电层覆盖的部分。在一些实施例中，在操作(iv)中，可通过电镀、无电极电镀、溅镀、膏体印刷、撞击或接合，在晶种层上形成导电材料。
参看图6I，电子组件51d放置在封装主体52的顶部表面521上的导电层53m上，且通过导电层53m电连接到电子组件51c和/或导电元件53a、53b。在一些实施例中，底填充料53u可形成于封装主体52的顶部表面521上，以覆盖电子组件51d的作用表面51d1。在一些实施例中，底填充料53u包含环氧树脂、模制化合物(例如环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。
去除载体69，且去除金属层69m的一部分，以形成导电层50的导电垫50p。在一些实施例中，可例如通过蚀刻或其它合适的工艺来去除金属层69m的所述部分。接着在导电垫50p上形成电接点50b，以形成如图5中所示的半导体封装装置5。在一些实施例中，电接点50b包含C4凸块、BGA或LGA。在一些实施例中，可通过电镀、无电极电镀、溅镀、膏体印刷、撞击或接合来形成电接点50b。
如本文中所使用，使用术语“大致”、“大体上”以及“约”来描述和考虑较小变化。当与事件或情形结合使用时，所述术语可指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，所述术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差值小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同。举例来说，“大体上”并行可指相对于0°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。举例来说，“大体上”垂直可指代相对于90°小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°的角度变化范围。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么可认为所述两个表面是共面的或大体上共面的。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”指代输送电流的能力。导电材料通常指示展现对于电流流动的极少或零对抗的材料。电导率的一个量度为西门子每米(S/m)。通常，导电材料为电导率大于约104S/m(例如至少105S/m或至少106S/m)的一种材料。材料的电导率有时可可随温度而变化。除非另外指定，否则材料的电导率是在室温下测量。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述(the)”包括多个参考物。在一些实施例的描述中，提供于另一组件“上”或“之上”的组件可涵盖前者组件直接在后者组件上(例如，与后者组件物理接触)上的情况，以及一或多个介入组件位于前者组件与后者组件之间的情况。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内替代等效组件而不脱离如由所附权利要求书定义的本发明的真实精神和范围。所述说明可能未必按比例绘制。归因于制造工艺和公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改，以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (22)

1.一种半导体封装装置，其包括：
电路层，其具有顶部表面；
第一电子组件，其安置于所述电路层的所述顶部表面上，所述第一电子组件具有作用表面和面向所述电路层的所述顶部表面的后表面；以及
第一导电元件，其安置于所述电路层的所述顶部表面上，所述第一导电元件具有顶部表面，
其中所述第一电子组件的所述作用表面与所述电路层的所述顶部表面之间的距离大于所述第一导电元件的所述顶部表面与所述电路层的所述顶部表面之间的距离。
2.根据权利要求1所述的半导体封装装置，其进一步包括安置于所述第一电子组件与所述电路层之间的第二电子组件，其中所述第二电子组件具有面向所述电路层的所述顶部表面的作用表面，以及面向所述第一电子组件的所述后表面的后表面。
3.根据权利要求2所述的半导体封装装置，其中从所述第二电子组件到所述第一导电元件的距离在1.89微米μm到1432.2μm的范围内。
4.根据权利要求1所述的半导体封装装置，其进一步包括包封所述第一电子组件和所述第一导电元件的封装主体，其中所述封装主体界定暴露所述第一导电元件的所述顶部表面的凹部。
5.根据权利要求4所述的半导体封装装置，其进一步包括：
晶种层，其安置于所述凹部内，且电连接到所述第一导电元件的所述顶部表面；
以及
金属层，其安置于所述凹部内以及所述晶种层上。
6.根据权利要求1所述的半导体封装装置，其中所述第一电子组件的所述作用表面与所述导电元件的所述顶部表面之间的距离小于220μm。
7.根据权利要求1所述的半导体封装装置，其进一步包括：
第三电子组件，其安置于所述第一电子组件与所述电路层之间；
接合线，其将所述第三电子组件电连接到所述电路层；以及
第二导电元件，其邻近于所述接合线，
其中所述第一导电元件比所述第二导电元件离所述接合线远，且
其中所述第一导电元件的高度大于所述第二导电元件的高度。
8.根据权利要求7所述的半导体封装装置，其中所述第三电子组件与所述第二导电元件之间的距离大于所述第三电子组件与所述第一导电元件之间的距离。
9.一种半导体封装装置，其包括：
电路层；
第一电子组件，其安置于所述电路层上，所述第一电子组件具有第一侧表面以及与所述第一侧表面相对的第二侧表面；
接合线，其越过包含所述第一电子组件的所述第一侧表面的平面，且将所述第一电子组件连接到所述电路层；
第一导电元件，其安置于所述电路层上且邻近于所述第一侧表面；以及
第二导电元件，其安置于所述电路层上且邻近于所述第二侧表面；
其中所述第一导电元件的高度小于所述第二导电元件的高度。
10.根据权利要求9所述的半导体封装装置，其中所述第一电子组件的所述第一导电元件与第一侧表面之间的距离大于所述第一电子组件的所述第二导电元件与所述第二侧表面之间的距离。
11.根据权利要求9所述的半导体封装装置，其进一步包括安置于所述第一电子组件上的第二电子组件，其中所述第二电子组件具有作用表面和面向所述第一电子组件的后表面，且其中所述第二电子组件的所述作用表面与所述电路层的顶部表面之间的距离大于所述第二导电元件的高度。
12.根据权利要求11所述的半导体封装装置，其进一步包括安置于所述第一电子组件与所述第二电子组件之间的第三电子组件，其中所述第三电子组件具有面向所述第一电子组件的作用表面的作用表面。
13.根据权利要求11所述的半导体封装装置，其进一步包括：
封装主体，其包封所述第一电子组件、所述第二电子组件、所述第一导电元件和所述第二导电元件，且暴露所述第二电子组件的所述作用表面、所述第一导电元件的顶部表面和所述第二导电元件的顶部表面；
导电层，其安置于所述第二电子组件的所述作用表面、所述第一导电元件的所述顶部表面和所述第二导电元件的所述顶部表面上；以及
第三电子组件，其安置于所述导电层上。
14.一种半导体封装装置，其包括：
电路层；
第一电子组件，其安置于所述电路层上；
第一导电元件，其安置于所述电路层上且具有顶部表面；
第二导电元件，其安置于所述电路层上且具有顶部表面；以及
封装主体，其包封所述第一电子组件、所述第一导电元件和所述第二导电元件，
其中所述封装主体具有顶部表面，且界定：第一凹部，其从所述封装主体的所述顶部表面延伸到所述第一导电元件的所述顶部表面；以及第二凹部，其从所述封装主体的所述顶部表面延伸到所述第二导电元件的所述顶部表面；且
其中所述第一凹部的深度不同于所述第二凹部的深度。
15.根据权利要求14所述的半导体封装装置，其中所述第一电子组件具有面向所述封装主体的所述顶部表面的作用表面，且所述封装主体的所述顶部表面与所述第一电子组件的所述作用表面之间的距离不同于所述第一凹部的所述深度和所述第二凹部的所述深度。
16.根据权利要求15所述的半导体封装装置，其中所述封装主体的所述顶部表面与所述第一电子组件的所述作用表面之间的距离小于所述第一凹部的所述深度和所述第二凹部的所述深度。
17.根据权利要求14所述的半导体封装装置，其进一步包括：
第二电子组件，其安置于所述第一电子组件与所述电路层之间；以及
接合线，其将所述第二电子组件连接到所述电路层，
其中所述接合线邻近于所述第一导电元件，且与离所述第一导电元件相比，离所述第二导电元件较远，且
其中所述第一凹部的所述深度大于所述第二凹部的所述深度。
18.根据权利要求17所述的半导体封装装置，其中所述第一导电元件与所述第二电子组件之间的距离大于所述第二导电元件与所述第二电子组件之间的距离。
19.一种制造半导体封装装置的方法，其包括：
提供电路层；
在所述电路层上形成第一导电元件和第二导电元件的第一部分；
在所述第二导电元件的所述第一部分上形成所述第二导电元件的第二部分；以及
将第一电子组件安置在所述电路层上以及所述第一导电元件与所述第二导电元件之间。
20.根据权利要求19所述的方法，其进一步包括接合导电线以将所述第一电子组件电连接到所述电路层上的导电垫，其中所述导电垫安置于所述第一电子组件与所述第一导电元件之间。
21.根据权利要求20所述的方法，其进一步包括将第二电子组件安置在所述第一电子组件上，其中所述第二电子组件具有作用表面和面向所述第一电子组件的后表面，
且所述作用表面与所述电路层之间的距离大于所述第一导电元件的高度，且大于所述第二导电元件的高度。
22.根据权利要求21所述的方法，其进一步包括：
形成封装主体以包封所述第一电子组件、所述第二电子组件、所述第一导电元件和所述第二导电元件；
去除所述封装主体的一部分以暴露所述第二电子组件的所述作用表面、所述第一导电元件的顶部表面和所述第二导电元件的所述第二部分的顶部表面；
在所述第二电子组件的所述作用表面、所述第一导电元件的所述顶部表面和所述第二导电元件的所述第二部分的所述顶部表面上形成导电层；以及
将第三电子组件安置在所述导电层上。
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