CN106098658A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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CN106098658A
CN106098658A CN201510422090.8A CN201510422090A CN106098658A CN 106098658 A CN106098658 A CN 106098658A CN 201510422090 A CN201510422090 A CN 201510422090A CN 106098658 A CN106098658 A CN 106098658A
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top surface
stud
district
electrical interconnection
substrate
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CN106098658B (zh
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李威弦
李菘茂
刘谦晔
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装包含衬底、一组电组件、螺柱、锥形电互连件和封装体。所述电组件安置于所述衬底的顶表面上。所述螺柱的底表面安置于所述衬底的所述顶表面上。所述电互连件的底表面安置于所述螺柱的顶表面处。所述螺柱的宽度大于或等于所述电互连件的所述底表面的宽度。所述封装体安置于所述衬底的所述顶表面上，且包封所述电组件、所述螺柱和一部分所述电互连件。所述封装体暴露所述电互连件的顶表面。

Description

半导体装置封装及其制造方法
技术领域
本发明涉及半导体装置封装及其制造方法，且更确切来说本发明涉及具有垂直互连件结构的半导体装置封装及其制造方法。
背景技术
在至少部分地由针对更小尺寸和增强的加工速度的需求的驱动下，半导体装置已变得越来越复杂。同时，存在使含有这些半导体装置的许多电子产品进一步小型化的需求。用于小型化的新颖技术相对应地是合乎需要的。
发明内容
根据本发明的实施例，半导体装置封装包含衬底、一组电组件、一或多个螺柱、锥形电互连件和封装体。所述衬底具有顶表面。所述电组件安置于所述衬底的顶表面上。所述螺柱具有顶表面和底表面。所述螺柱的底表面安置于所述衬底的顶表面上。所述电互连件具有顶表面和底表面。所述电互连件的底表面安置于所述螺柱的顶表面处。所述螺柱的宽度大于或等于所述电互连件的底表面的宽度。所述封装体安置于所述衬底的顶表面上，且包封所述电组件、所述螺柱和一部分所述电互连件。所述封装体暴露所述电互连件的顶表面。
根据本发明的实施例，半导体装置封装包含衬底、螺柱区、电互连件和封装体。所述衬底具有顶表面。所述螺柱区具有顶表面和底表面。所述螺柱区的底表面安置于所述衬底的顶表面上。所述电互连件具有顶表面和底表面。所述电互连件从其顶表面到其底表面而成锥形。所述电互连件的底表面安置于所述螺柱区的顶表面处。所述电互连件的高度等于或大于所述螺柱区的高度。所述封装体安置于所述衬底的顶表面上，且覆盖所述螺柱区和一部分所述电互连件。所述封装体暴露所述电互连件的顶表面。
根据本发明的实施例，一种制造半导体装置封装的方法包含：提供衬底；将一组电组件附接于所述衬底上；在所述衬底上形成螺柱区；在所述衬底上形成封装体以包封所述电组件和所述螺柱；从所述封装体的顶表面形成锥形腔以暴露所述螺柱区的顶表面，其中所述腔的深度等于或大于所述螺柱区的高度；以及用导电材料来填充所述腔以形成电互连件。
附图说明
图1A说明根据本发明的实施例的半导体装置封装。
图1B说明如图1A中所展示的半导体装置封装的区。
图1C说明根据本发明的实施例的图1A中所展示的半导体装置封装的一部分的仰视图。
图2A说明根据本发明的实施例的互连件的布置。
图2B说明根据本发明的另一实施例的互连件的布置。
图2C说明根据本发明的另一实施例的互连件的布置。
图2D说明根据本发明的另一实施例的互连件的布置。
图2E说明根据本发明的实施例的实验结果。
图3A、图3B、图3C、图3D、图3E和图3F说明根据本发明的实施例的制造过程。
贯穿图式和具体实施方式使用共同参考数字以指示相同或类似元件。从以下结合附图作出的详细描述，本发明将会更加显而易见。
具体实施方式
提议堆叠式半导体装置封装以减小所述半导体装置封装的尺寸并提供更加灵活的半导体装置封装设计。根据本发明的垂直互连件结构占据堆叠式半导体装置封装内相对较小的空间，从而提供相对密集的互连件。根据本发明的垂直互连件结构进一步提供横跨相对较大距离的垂直互连件。
图1A说明根据本发明的实施例的半导体装置封装1的横截面图。半导体装置封装1包含第一模块1A和堆叠于第一模块1A上的第二模块1B。
第一模块1A包含衬底10、一组电组件11、12、螺柱区13、电互连件14和封装体15。
衬底10由例如印刷电路板形成，例如纸基铜箔层合物、复合铜箔层合物或聚合物浸渍的玻璃纤维基铜箔层合物等。衬底10可包含重布层(RDL)或迹线；举例来说，用于实现安放于衬底10的顶表面101上的组件(例如，电组件11、12)之间的电连接，或用于实现组件与螺柱区13之间的电连接，或用于实现位于衬底10的顶表面101上的组件或螺柱区13与位于衬底10的底表面上的电端子(未图示)之间的电连接。
电组件11安置于衬底10的顶表面101上(例如，直接安置于衬底10的顶表面101上并接触衬底10的顶表面101，或间接安置于衬底10的顶表面101上或上方且存在一或多个可能的介入组件)。在一或多个实施例中，电组件11是有源组件(例如，芯片或半导体裸片)。电组件11可通过倒装芯片接合、导线接合或倒装芯片接合与导线接合两者而电连接到衬底10。
电组件12安置于衬底10的顶表面101上。在一或多个实施例中，电组件12是无源组件(例如，电容器、电阻器、电感器或此些组件的组合)。
螺柱区13安置于衬底10的顶表面101上。
图1B展示被图1A中的点线所圈住的部分A的放大视图。如图1B中所展示，螺柱区13包含两个螺柱13a、13b。借助于实例说明了两个螺柱13a、13b；在其它实施例中，螺柱区13中可存在更多螺柱或更少螺柱。
参看图1B，电互连件14安置于螺柱区13的顶表面13a1处。电互连件14经形成为向下成锥形的形状(在此上下文中“向下”是指图1B中所说明的朝向螺柱区13的定向)，且因此电互连件14的顶表面141的宽度D1大于电互连件14的底表面142的宽度D2。
每一螺柱13a、13b的宽度D3大于电互连件14的底表面142的宽度D2。电互连件14的底表面142的宽度D2等于或小于螺柱区13的顶表面13a1的宽度D4，使得电互连件14并未延伸于螺柱区13的侧部分上方、延伸到螺柱区13的侧部分中或另外接触螺柱区13的侧部分。在一或多个实施例中，每一螺柱13a、13b的宽度D3大于或等于电互连件14的顶表面141的宽度D1。在另一实施例中，每一螺柱13a、13b的宽度D3小于电互连件14的顶表面141的宽度D1。在一或多个实施例中，直径D1是大致80μm到大致150μm(例如，大致80μm到大致130μm，大致80μm到大致110μm，或大致80μm到大致90μm)。在一或多个实施例中，直径D3是大致80μm到大致150μm(例如，大致80μm到大致130μm，大致80μm到110μm，或大致80μm到大致90μm)。
参看图1B，互连件14具有从顶表面141到底表面142的高度H1。高度H2被定义为从电互连件14的底表面142到螺柱区13的底表面13b2(其在图1B中所说明的实施例中是螺柱13b的底表面13b2)。在一或多个实施例中，高度H1是大致180μm到大致220μm(例如，大致180μm到大致200μm)。在一或多个实施例中，高度H2是大致120μm到大致180μm(例如，大致120μm到大致140μm，或大致120μm到大致160μm)。在一或多个实施例中，高度H1等于或大于高度H2。在一或多个实施例中，高度H1等于或大于螺柱区13中的任何一个螺柱的高度。在一或多个实施例中，高度H1等于或大于螺柱区13的总高度。
返回参看图1A，封装体15安置于衬底10的顶表面101上以包封电组件11、12、螺柱区13和一部分电互连件14。电互连件14的顶表面141从封装体15而被暴露。在一或多个实施例中，电互连件14的顶表面141从封装体15的顶表面151伸出，例如(例如)其中电互连件14的伸出部分是高度H1的大致5％到大致50％(例如，大致5％到大致30％，或大致10％到大致30％)等。但是，在其它实施例中，电互连件14的顶表面141实质上与封装体15的顶表面151共面或位于封装体15的顶表面151以下。封装体15可以是或可包含例如具有填充剂的环氧树脂、模制化合物(例如，环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、具有分散于其中的硅酮的材料，或其组合。
仍参看图1A，第二模块1B包含衬底20、电组件21、22和封装体25。
衬底20安置于第一模块1A上，且衬底20的底表面202与电互连件14的顶表面141电连接。衬底20可包含RDL或迹线；举例来说，用于实现安放于衬底20的顶表面201上的组件(例如，电组件21、22)之间的电连接，或用于实现位于衬底20的顶表面201上的组件与位于衬底20的底表面202上的电端子之间的电连接。
电组件21安置于衬底20的顶表面201上。在一或多个实施例中，电组件21是有源组件(例如，芯片或半导体裸片)。电组件21可通过倒装芯片接合、导线接合或倒装芯片接合与导线接合两者而电连接到衬底20。
电组件22安置于衬底20的顶表面201上。在一或多个实施例中，电组件22是无源组件(例如，电容器、电阻器、电感器或此些组件的组合)。
在图1A的实施例中，第一模块1A借助于螺柱区13和电互连件14而电连接到第二模块1B。在其它实施例中，第一模块1A通过焊料球的垂直互连件而不是经由螺柱区13和电互连件14来电互连到第二模块1B。但是，相对于图1A中所说明的实施例，焊料球的直径(例如，250μm)和焊料球之间的间距(例如，500μm)导致组件(例如，组件11、12、21和22)的密度减小且相对应的半导体装置封装的总尺寸增加。比较来说，如上文所指出，螺柱区13和电互连件14中的每一者可具有大致80μm到大致150μm的直径。此外，邻近螺柱区13或邻近电互连件14之间的间距等于或小于大致230μm。因此，相比于使用焊料球的装置封装，图1A的半导体装置封装1的总尺寸可减小，且制造成本也可相对应地降低。
在其它实施例中，第一模块1A通过使用铜柱的垂直互连件而不是经由螺柱区13和电互连件14来电互连到第二模块1B。在其它实施例中，在没有电互连件14的情况下，第一模块1A通过使用堆叠式螺柱(例如，螺柱区13)的垂直互连件而电互连到第二模块1B。但是，制造过程会对铜柱强加高度局限性，且可通过斜摆来限制可加以堆叠的螺柱的数目。螺柱区13与电互连件14的组合(作为如图1A中所展示的第一模块1A与第二模块1B之间的垂直互连件)考虑到垂直互连件的总高度的增加(相比于使用铜柱或堆叠式螺柱)。因此，可将更高组件安放于第一模块1A的衬底10上。
仍参看图1A，封装体25安置于衬底20的顶表面201上以包封电组件21、22。封装体25可以是或可包含例如具有填充剂的环氧树脂、模制化合物(例如，环氧树脂模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、具有分散于其中的硅酮的材料，或其组合。
图1C说明根据本发明的实施例的半导体装置封装1的第一模块1A的仰视图，所述仰视图来自于沿着封装体15的底部的平面，其中封装体15接触衬底10的顶表面101。
参看图1C，在一或多个实施例中，螺柱区13(和此图中看不见的电互连件14)布置于衬底10的外围边缘周围，并且还从外围边缘布置成朝向电组件11和12。
螺柱区13和相对应的电互连件14的精细节距和较小直径为第一模块1A内的比在使用焊料球或其它形式的互连件的情况下将否则可获得的输入/输出(I/O)连接更多的I/O连接提供连接点，且因此可为第一模块1A的电路设计提供更多灵活性。
螺柱区13和电互连件14的精细节距和较小直径允许半导体装置封装1包含第一模块1A与第二模块1B之间的比在使用焊料球或其它形式的互连件的情况下将否则可获得的互连件更多的互连件。举例来说，可添加接地路径以包围信号节点或路径，同时保持相对较小的半导体装置封装1。信号节点或路径周围的额外接地路径可减少被引入到所述信号节点或路径的例如串音、耦合效应或电磁干扰(EMI)等电干扰，且因此可提供经改进的性能。关于图2A到2D提供了对接地路径的使用的一些非限制性实例，其中一些实验结果提供于图2E中。
图2A、图2B、图2C和图2D说明被标记为S1、S2和G的互连件(例如，螺柱区13与电互连件14的组合)的不同布置，其中互连件S1和S2是指信号路径互连件，且互连件G是指接地路径互连件。
在图2A中，互连件S1安置成紧挨着另一互连件S2。互连件S1和S2可用于发射相同或不同信号。下文将如图2A中所展示的配置称为类型1。
在图2B中，接地互连件G安置于两个信号互连件S1、S2之间。换句话说，接地互连件G被插入于两个信号互连件S1、S2之间。下文将如图2B中所展示的配置称为类型2。
在图2C中，三个接地互连件G布置于信号互连件S1周围。换句话说，信号互连件S1被三个接地互连件G所包围。下文将如图2C中所展示的布置称为类型3。
在图2D中，四个接地互连件G布置于信号互连件S1周围。换句话说，信号互连件S1被四个接地互连件G所包围。下文将如图2D中所展示的布置称为类型4。
图2E说明类型1、2、3和4的耦合效应的实验结果。在图2E中，x轴表示经由互连件S1、S2所发射的信号的频率(GHz)；y轴表示互连件S1与S2之间的隔离度值(dB)。
如图2E中所展示，当以0.9GHz的频率来操作半导体装置封装1时，类型1、类型2、类型3和类型4的大致的隔离度值分别是-37.6dB、-63.8dB、-72.8dB和-77.7dB。当以2.4GHz的频率来操作半导体装置封装1时，类型1、类型2、类型3和类型4的大致的隔离度值分别是-29.1dB、-55.4dB、-65.3dB和-70.9dB。当以5GHz的频率来操作半导体装置封装1时，类型1、类型2、类型3和类型4的大致的隔离度值分别是-22.8dB、-50.5dB、-63.0dB和-76.3dB。
图2E中的实验结果展示：包围信号互连件S1的接地互连件G愈多，那么可在信号互连件S1与S2之间产生更好的隔离度。
相比于其它类型的垂直互连件，由于螺柱区13和电互连件14的直径和间距更小，所以可将更多接地路径布置于半导体装置封装1中，以便包围一或多个信号节点或路径从而实现更好的隔离度。因此，可改进半导体装置封装1的性能。
图3A到3F说明根据本发明的实施例的半导体制造过程。
参看图3A，提供衬底10。衬底10由例如印刷电路板形成，例如纸基铜箔层合物、复合铜箔层合物或聚合物浸渍的玻璃纤维基铜箔层合物等。电组件11、12放置在衬底10的顶表面101上。衬底10可包含RDL或迹线；举例来说，用于实现安放于衬底10的顶表面101上的组件(例如，电组件11、12)之间的电连接，或用于实现其它电连接。
参看图3B，使用例如导线接合技术将螺柱区13放置在衬底的顶表面101上。更确切来说，通过将螺柱13b放置在衬底10上且随后将另一螺柱13a堆叠于螺柱13b上而形成每一螺柱区13。如上文所指出，螺柱区13中可存在两个以上或两个以下的螺柱，且基于螺柱区13的所要垂直高度来确定堆叠式螺柱的数目。此外，螺柱区13中的不同者可包含不同数目个螺柱。在一或多个实施例中，螺柱13a、13b可以是或可包含导电材料，例如金、铜、铝或其它合适的导电材料等。
参看图3C，在衬底10的顶表面101上形成封装体15以包封电组件11、12和螺柱区13。可通过例如转移模制或压缩模制等模制技术来形成封装体15。
参看图3D，在封装体15中形成数个开口14h以暴露每一螺柱区13的顶表面13a1的至少一部分。每一开口14h在从封装体的顶表面151朝向螺柱区13的顶表面13a1的方向上成锥形，使得开口14h的形状是向下成锥形(在图3D的定向中)。可例如通过激光钻孔或蚀刻技术来形成开口14h。
参看图3E，将导电材料填充到每一开口14h中以形成电互连件14。在一或多个实施例中，导电材料可以是或可包含例如锡，且可通过喷射、溅镀或印刷而形成。在一或多个实施例中，电互连件14经形成为从封装体15的顶表面151稍微伸出。
随后，执行回焊过程以在每一电互连件14与相对应的螺柱区13之间形成金属互连相，以便形成图1A中所展示的半导体装置封装1的第一模块1A。在回焊过程之后，电互连件14可从封装体15的顶表面151稍微伸出，如图3E中所说明；但是，在一些实施例中，每一电互连件14的顶表面141可改为实质上与封装体15的顶表面151共面或可低于封装体15的顶表面151。
参看图3F，将第二模块1B安放于第一模块1A上，以便形成图1A中所展示的半导体封装1。每一电互连件14电连接到第二模块B的相对应的电端子(未图示)以在第一模块1A与第二模块1B之间形成电连接。因此，可经由螺柱区13和电互连件14而在第一模块1A与第二模块1B之间发射信号，且反过来也一样。
制造第二模块1B的过程类似于制造第一模块1A的过程，且因此将不加以描述。在一或多个实施例中，可针对如图3F中所说明的第二模块1B而省略关于图3D和3E所描述的过程；即，可省略在封装体25中形成开口和用导电材料来填充所述孔。应理解，可堆叠两个以上模块(例如，不止第一模块1A和第二模块1B)，且因此第二模块1B也可包含在封装体25中的用导电材料填充的开口。
如本文中所使用，术语“实质上”、“实质”、“大致”和“大约”用于表示少量变化。当与事件或情形结合使用时，所述术语可以是指其中事件或情形明确发生的情况以及其中事件或情形极近似于发生的情况。举例来说，所述术语可以是指小于或等于±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％等。
如果两个表面之间的位移不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为这两个表面是共面的或实质上是共面的。
另外，有时在本文中按范围格式呈现量、比率和其它数值。可理解，此些范围格式是用于便利和简洁起见，且应灵活地理解为不仅包含明确地指定为范围界限的数值，而且包括涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
虽然已参考本发明的特定实施例描述并说明了本发明，但这些描述和说明并不限制本发明。所属领域的技术人员可清楚地理解，可作出各种改变，且可在实施例内替代等效组件而不脱离如由所附权利要求书定义的本发明的真实精神和范围。所述说明可能未必按比例绘制。归因于制造过程的公差等等，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改，以使特定情境、材料、物质组成、方法或过程适应于本发明的目标、精神及范围。所有此些修改都打算属于在此所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组并非为本发明的限制。

Claims (20)

1.一种半导体装置封装，其包括：
第一衬底，其具有顶表面；
第一组电组件，其安置于所述第一衬底的所述顶表面上；
具有顶表面和底表面的至少一个螺柱，所述螺柱的所述底表面安置于所述第一衬底的所述顶表面上；
具有顶表面和底表面的锥形电互连件，所述电互连件的所述底表面安置于所述螺柱的所述顶表面处，所述螺柱的宽度大于或等于所述电互连件的所述底表面的宽度；以及
安置于所述第一衬底的所述顶表面上的第一封装体，其包封所述第一组电组件、所述螺柱和一部分所述电互连件，所述第一封装体暴露所述电互连件的所述顶表面。
2.根据权利要求1所述的半导体装置封装，其中所述电互连件的所述底表面的所述宽度等于或小于所述螺柱的所述顶表面的宽度。
3.根据权利要求1所述的半导体装置封装，其中所述电互连件的高度等于或大于所述一个螺柱的高度。
4.根据权利要求1所述的半导体装置封装，其中所述电互连件的所述顶表面从所述第一封装体的顶表面伸出。
5.根据权利要求1所述的半导体装置封装，其中所述至少一个螺柱是多个堆叠式螺柱。
6.根据权利要求1所述的半导体装置封装，其进一步包括：
具有顶表面和底表面的第二衬底，所述第二衬底的所述底表面安置于所述第一封装体的顶表面上；
第二组电组件，其安置于所述第二衬底的所述顶表面上；以及
第二封装体，其安置于所述第二衬底的所述顶表面上且包封所述第二组电组件。
7.一种半导体装置封装，其包括：
第一衬底，其具有顶表面；
具有顶表面和底表面的第一螺柱区，所述第一螺柱区的所述底表面安置于所述第一衬底的所述顶表面上；
具有顶表面和底表面的电互连件，所述电互连件从所述电互连件的所述顶表面到所述电互连件的所述底表面而成锥形，所述电互连件的所述底表面安置于所述第一螺柱区的所述顶表面处，其中所述电互连件的高度等于或大于所述第一螺柱区的高度；以及
安置于所述第一衬底的所述顶表面上的第一封装体，所述第一封装体覆盖所述第一螺柱区和一部分所述电互连件，且所述第一封装体暴露所述电互连件的所述顶表面。
8.根据权利要求7所述的半导体装置封装，其中所述电互连件的所述底表面的宽度等于或小于所述第一螺柱区的所述顶表面的宽度。
9.根据权利要求7所述的半导体装置封装，其中所述电互连件的所述顶表面的宽度等于或小于所述第一螺柱区的宽度。
10.根据权利要求7所述的半导体装置封装，其中所述电互连件的所述顶表面从所述第一封装体的顶表面伸出。
11.根据权利要求7所述的半导体装置封装，其进一步包括：
具有顶表面和底表面的第二衬底，所述第二衬底的所述底表面安置于所述第一封装体的顶表面上；以及
第二封装体，其安置于所述第二衬底的所述顶表面上。
12.根据权利要求11所述的半导体装置封装，其中所述第一螺柱区包含多个堆叠式螺柱。
13.根据权利要求7所述的半导体装置封装，其进一步包括安置于所述第一衬底的所述顶表面上且邻近于所述第一螺柱区的第二螺柱区，其中所述第二螺柱区被接地。
14.根据权利要求13所述的半导体装置封装，其中所述第一螺柱区经配置以提供信号路径，所述半导体装置封装进一步包括安置于所述第一衬底的所述顶表面上且经配置以提供另一信号路径的第三螺柱区，其中所述第二螺柱区安置于所述第一螺柱区与所述第三螺柱区之间。
15.一种制造半导体装置封装的方法，所述方法包括：
(a)提供衬底；
(b)将一组电组件附接于所述衬底上；
(c)在所述衬底上形成螺柱区；
(d)在所述衬底上形成封装体以包封所述组电组件和所述螺柱区；
(e)从所述封装体的顶表面形成锥形腔以暴露所述螺柱区的顶表面，其中所述腔的深度等于或大于所述螺柱区的高度；以及
(f)用导电材料来填充所述腔以形成电互连件。
16.根据权利要求15所述的方法，其中所述电互连件的顶表面的宽度等于或小于所述螺柱区的宽度。
17.根据权利要求15所述的方法，其中所述电互连件的底表面的宽度等于或小于所述螺柱区的所述顶表面的宽度。
18.根据权利要求15所述的方法，其中所述电互连件的顶表面实质上与所述封装体的顶表面共面。
19.根据权利要求15所述的方法，其进一步包括：在(f)之后，回焊所述半导体装置封装。
20.根据权利要求15所述的方法，其进一步包括将多个堆叠式螺柱安置于所述衬底上以形成所述螺柱区。
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