CN1577824A - 制造一种直接芯片连接装置及结构的方法 - Google Patents

制造一种直接芯片连接装置及结构的方法 Download PDF

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CN1577824A
CN1577824A CNA2004100600721A CN200410060072A CN1577824A CN 1577824 A CN1577824 A CN 1577824A CN A2004100600721 A CNA2004100600721 A CN A2004100600721A CN 200410060072 A CN200410060072 A CN 200410060072A CN 1577824 A CN1577824 A CN 1577824A
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李爱文
吴川家
戈元庆
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Semiconductor Components Industries LLC
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Abstract

一种用于构成直接芯片连接装置(1)的方法，包括将一个电子芯片(3)连到一个具有标记突起(18)的引线框(2)上。然后，将导电柱(22)连到电子芯片(3)的焊盘(13)及标记突起(18)上从而构成组件(24)。组件(24)然后被置于一个模塑设备(27、47)中，其包括一个第一盘(29、49)和第二盘(31、51)。第二盘(31、51)包括一个用于容纳电子芯片(3)及标记突起(18)的腔(32、52)和针(36、56)。在模塑阶段中，针(36、56)接触导电柱(22)以防止密封材料(4)盖住柱(22)。这可在随后的工艺步骤中形成开口(6)以容纳焊料球(9)。

Description

制造一种直接芯片连接装置及结构的方法
技术领域
[1]本发明一般涉及一种电子装置的封装，具体来说，涉及在倒装片封装中形成互连的方法及设备。
背景技术
[2]倒装微电子封装技术已存在30余年，是关于一种面朝下(所谓“倒装”)的电子元件或芯片与基片、电路板或载体的直接电子连接。这种电子连接是通过连在芯片和基片的各自焊盘上的导电突起或导电球实现的。相反，一种较老的技术引线接合法是采用面朝上的芯片，其在各焊盘与引线框上相应的引线或者接头之间形成线连接。
[3]倒装片元件是主要的半导体装置。然而，如无源滤波器、检测器阵列和传感器装置等元件也开始使用倒装片形式了。倒装片也称为直接芯片连接(Direct Chip Attach，DCA)——一种更具说明性的术语，因为芯片是通过导电突起直接连接到基片上、电路板或者载体上的。
[4]尽管倒装片技术已经进步到包括多种材料及方法来用于突起、连接及底部填料等装置，然而在解决关于更紧凑的空间需求、降低成本和更高的装置性能及可靠性等问题时仍存在挑战。
[5]因此，关于制造倒装片式封装仍存在对改良结构及工艺的需求。
附图说明
[6]图1图示了根据本发明制造的直接芯片连接装置的放大的轴测图；
图2图示了在最初制造阶段的图1所示实施例沿参考线1-1的放大截面图；
图3图示了在下一制造阶段中图1所示实施例的放大截面图；
图4图示了一个根据本发明的用来制造图1实施例的设备的放大截面图；
图5图示了图4所示装置的另一放大截面图；
图6图示了在随后制造阶段中图1实施例的放大截面图；
图7图示了下一制造阶段中图1实施例的放大截面图；
图8图示了根据本发明的装置的第二实施例的放大截面图。
具体实施方式
[7]一般地，本发明是关于一种在模制直接芯片连接(DCA)结构上形成开口用以连接焊料突起和密封装置的方法。具体来说，一个电子芯片连接到引线框结构上且一个导电突起连接到芯片表面上的焊盘上。然后引线框基片和电子芯片在一个模塑腔中被密封。在密封阶段，在模铸腔内的针、短柱或者凸起与导电突起接触以防止密封材料溢过导电突起从而可形成开口。在下一阶段中，焊料球通过这些开口连到导电突起上。
[8]普遍地，DCA装置是以如下方式制造的。将一电子芯片连到引线框结构上。然后，芯片由钝化材料或者模塑料通过传统的注模法密封。在模塑工序完成之后装置从模塑设备上拆卸下来，在模塑件外表面上形成开口以露出电子芯片上的接触区域。然后连接焊料球以在密封芯片与下一层组件之间形成互连。
[9]在模塑件外表面形成开口的一个方法是用激光烧制。激光烧制有几个缺陷，如较长的处理时间、昂贵的设备以及提供准直时繁琐的技术。化学蚀刻是形成开口的另一种技术。这种技术需要专门的化学制品，其非常昂贵且有害。此外，化学蚀刻技术还非常耗时且需要昂贵的工艺设备。
[10]现将参照图1至8及下文的详细说明来更好的理解本发明。为了便于理解，在说明书及附图中相似的元件或区域使用相同的附图标记。
[11]图1示出一个根据图2至7所示方法制造的DCA装置或结构1的放大的等角视图。DCA装置1包括一个引线框或者支撑基片2，一个电子芯片、装置或者元件3(图2中所示)，和一个在上表面7上具有开口6的密封层或者保护层4。焊料球或者导电球、珠或突起9通过开口6与芯片3和引线框2相连。
[12]图2图示了一个在早期制造阶段的DCA装置1沿图1中参考线1-1的放大截面图。举例来说，芯片2包括一个功率MOSFET、逻辑、传感器装置、被动器件或者双极器件。芯片3包括在上表面14上的焊盘或者焊块13。焊盘13含有，例如，铝/铝-硅/铝-硅-铜。芯片3由使用传统技术例如共晶管芯连接(eutectic die attach)、导电环氧树脂或者软焊工艺形成的一个管芯连接层17连接到引线框2上。例如，芯片3使用铅/锡(Pb/Sn)软焊工艺连接。
[13]如图2所示，引线框2进一步包括一个标记突起18，其上部或者顶端与芯片3的下表面19相接触。当芯片3包含一个功率MOSFET时，触点13构成一个源触点而标记突起18提供一个顶端漏极触点。带有引线框2包括标记突起18优选含有铜、铜合金(如，TOMAC4，TOMAC5，2ZFROFC，或者CDA194)、镀铜的铁/镍合金(如镀铜合金42)或者类似物。
[14]然后，如图3所示，导电突起、球或者短柱22连到触点13上。在一优选实施例中，导电柱22也连到标记突起18上。在另一可替代实施例中，标记突起18的高度被设计为等于短柱22与触点13的高度而短柱22未置于标记突起18上。
[15]导电突起22是通过例如超声波、热压或者热声焊接技术连接的。导电突起22含有，例如金或铜。在一实施例中，导电突起22是通过传统丝焊技术的丝焊球形成的。优选地，除去焊丝上丝焊球以上的任何剩余部分，只剩下导电柱22在焊盘13及导电突起18上，如图3所示。
[16]可替代地，导电柱22可由通过回流而与焊盘13及标记突起18构成电连接和机械连接的焊料球形成。在另一实施例中，导电柱22是通过导电环氧树脂形成。优选地，导电柱22具有从75微米到1500微米的高度。当导电柱22被连接上后，组件24就形成了。
[17]图4表示了在下一工序初始阶段的组件24的放大截面图。组件24被置于一个模塑设备27中来进行密封。磨损设备27包括一个上半部分、上盘或者第一半部分29，和一个下半部分、下盘或者第二半部分31。在一优选实施例中，下盘31还包括一个腔、井或者井状部分32，其在上表面或主要表面34上用于接收或者容纳芯片3及标记突起18。
[18]根据本发明，井32包括针、柱、凸起或者突起36，其位于、连接或者附在井32的表面37上。例如，针36是在井32的制造或者加工过程中从下盘31上除去周围的材料而形成的。也就是说，针36和下盘31是由同一块材料加工出来的。可选地，针36可通过焊接或者铜焊技术连到表面37上。在一优选实施例中，针36含有碳钢。
[19]根据本发明，针36形成在或者位于井32中与组件24上的导电柱22对齐的位置，从而在当上盘29朝着组件24下降时，针36可以与柱22接触，如图5所示。这种接触提供了一个屏蔽或隔断结构或装置，其可以防止模塑化合物或者密封材料盖过柱22的上表面从而可在模塑或密封步骤中形成开口6。在另一可选实施例中，腔及针都形成在上盘29上而组件24在模塑设备27中倒置。
[20]然后使用传统方式将模塑化合物注入到井32中来密封芯片3及标记突起18以形成图1中的保护层4。保护层4含有，例如，环氧清漆树脂。
[21]在一优选实施例中，如图4所示，针36的上表面是平的且上边缘具有倒角或者圆角，从而可在DCA装置1的开口6中形成一个斜角或者圆角的边缘。其在图6中进行了更清楚的表示，图6是模塑阶段后的组件24的放大截面图。斜切的或斜削的边缘是为了在将焊料球9放置在开口6中时可更好地对准。举例来说，当DCA装置包括如功率MOSFET芯片时，针36具有以0.05到0.15毫米(mm)顺序的高度及0.20到0.50mm顺序的直径。这些尺寸是可变的且可以根据特定的装置及封装限制来进行调整。
[22]由于在密封工序阶段中可形成开口6，模塑设备27优越于其他技术如激光烧制或化学蚀刻，因为其无需另外的工艺设备及消耗品(比如化学药品、用具等)。此外，这还减少了循环时间从而进一步降低了DCA装置1的制造成本。
[23]在模塑阶段之后，密封材料4被后固化，而后在开口6中的柱22上形成隔层41。优选地，隔层41含有一种材料，其与柱22和焊料球9在冶金学(metalurgically)上是兼容的。也就是说，隔层41防止了柱22及焊料球9的元素之间相互扩散。例如，当柱22含有金而焊料球含有铅/锡时，隔层41优选含有一个由无电镍镀或电解镍镀(electroless nickel plating orelectrolytic nickel plating)方法形成的镍层。
[24]图7表示了DCA装置1在连上焊料球9之后的放大截面图。焊料球9含有，如，铅/锡合金，并通过传统的熔化及回流技术(fluxing andre-flow)被连接。在回流后，焊料球9典型地呈现一种半球形。
[25]图8表示了一个根据本发明第二实施例的模塑设备47的放大截面图。模塑设备47包括一个上半部分或盘49和一个下半部分或盘51。下盘在其上表面54上还具有一个腔、井或井状部分52。在此第二实施例中，针56被置于井52内的开口57中。这个实施例允许针具有不同的端部几何形状(例如，圆的、平的、正方的等等)，其取决于特定的装置及封装需要。此外，模塑设备47允许在旧的针磨损或者损坏时以一种经济的方式加入新的针。
[26]因而，依照本发明，很明显已给出了一种使直接芯片连接装置在模塑封装中形成开口从而使焊料球可与密封芯片接触的方法。此外，还给出了一种模塑设备，其具有在模塑工序中可以方便地形成开口的针。这种方法和结构通过去掉了需要昂贵设备和材料的工艺步骤而优越于其他技术。
[27]尽管发明是参考其具体实施例进行描述和图示的，但并不意味着发明仅限于这些图示的实施例。本领域技术人员会认可在不偏离本发明宗旨的情况下可以作出多种改型及变化。例如，模塑设备27可以是颠倒的从而使腔和针可以形成在上盘中。因此，意味着本发明包括所有这种落在所附权利要求保护范围内的变化和改型。

Claims (10)

1.用于形成直接芯片连接装置的方法，其特征在于以下步骤：
将一电子芯片连接到一引线框结构上，其中所述电子芯片包括一焊盘；
将一导电突起连接到所述焊盘上；
将所述电子芯片和所述引线框结构置于一模塑设备中，其中所述模塑设备具有一井状部分，在该井状部分的第一表面上连有一针；
将所述针与所述导电突起相接触；并且
以密封材料模塑电子芯片；其中所述针盖住导电突起从而可在导电突起之上的密封材料中形成一开口。
2.如权利要求1所述的方法，其特征在于，将所述电子芯片及所述引线框结构置于所述模塑设备中的步骤包括将所述电子芯片及所述引线框结构放置到所述模塑设备中，其中该井状部分具有多个连到第一表面上的针。
3.如权利要求1所述的方法，其特征在于，进一步包括步骤将一焊料球连到所述开口内的电子芯片上。
4.如权利要求1所述的方法，所述将所述电子芯片及所述引线框结构置于所述模塑设备中的步骤包括将所述电子芯片及所述引线框结构放置到所述模塑设备中，其中该针具有一平的上表面和圆角的上边缘。
5.用以形成倒装片装置的方法，其特征在于采用以下步骤：
将一组件放置到一具有空腔的模塑设备中，其中该组件包括一连到支撑基片上的电子芯片，且其中，所述电子芯片包括一连到所述电子芯片上的第一导电柱；
将所述第一导电柱与空腔中的一第一隔断装置接触；并且
将密封材料注入至空腔中以密封所述电子芯片，其中第一隔断装置盖住第一导电柱，从而在所述倒装片装置中形成一开口。
6.如权利要求5所述的方法，其特征在于，具有将焊料球连接到所述开口中的倒装片装置上的步骤。
7.如权利要求5所述的方法，其特征在于，所述接触步骤包括将第一导电柱与一针相接触，该针具有一平的上表面和圆角的上边缘，从而可形成一带圆角的开口。
8.如权利要求5所述的方法，其特征在于，放置组件的步骤包括放置一组件，该组件具有连接到支撑基片上的电子芯片，且其中支撑基片包括一标记突起，在该标记突起上连有一第二导电柱。
9.用于模塑倒装片装置的设备，其特征在于：
一模塑盘，具有一主表面；
一空腔，在该主表面上的用于容纳一芯片装置；和
一针，连到该空腔的第一表面上。
10.如权利要求9所述的设备，其特征在于，该针具有一具有圆角的上边缘的平的上表面。
CNB2004100600721A 2003-06-26 2004-06-25 制造一种直接芯片连接装置及结构的方法 Expired - Fee Related CN100463152C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098658A (zh) * 2015-04-29 2016-11-09 日月光半导体制造股份有限公司 半导体装置封装及其制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928550B2 (en) * 2007-11-08 2011-04-19 Texas Instruments Incorporated Flexible interposer for stacking semiconductor chips and connecting same to substrate
US10251273B2 (en) 2008-09-08 2019-04-02 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard
US8169058B2 (en) 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8304900B2 (en) * 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US9401338B2 (en) * 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
CN108249385A (zh) * 2018-01-15 2018-07-06 烟台艾睿光电科技有限公司 一种mems封装焊接组件
DE102020208862A1 (de) * 2020-07-15 2022-01-20 Zf Friedrichshafen Ag Formwerkzeug zum verkapseln eines pin-fin-artigen leistungsmoduls und verfahren zum herstellen eines leistungsmoduls

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW344109B (en) * 1994-02-10 1998-11-01 Hitachi Ltd Methods of making semiconductor devices
US5766972A (en) * 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
MY112145A (en) * 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
US5757073A (en) * 1996-12-13 1998-05-26 International Business Machines Corporation Heatsink and package structure for wirebond chip rework and replacement
US6081997A (en) * 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
JP2001230520A (ja) * 2000-02-14 2001-08-24 Sony Corp 配線基板の製造方法及びそれにより得られた配線基板
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6660565B1 (en) * 2000-08-17 2003-12-09 St Assembly Test Services Pte Ltd. Flip chip molded/exposed die process and package structure
US6436736B1 (en) * 2000-11-13 2002-08-20 Semiconductor Components Industries Llc Method for manufacturing a semiconductor package on a leadframe

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098658A (zh) * 2015-04-29 2016-11-09 日月光半导体制造股份有限公司 半导体装置封装及其制造方法
CN106098658B (zh) * 2015-04-29 2019-08-02 日月光半导体制造股份有限公司 半导体装置封装及其制造方法

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